PROCESS FOR FABRICATING AN ISOLATED FIELD EFFECT TRANSISTOR IN AN EPI-LESS SUBSTRATE

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EP 1 543 546 B8

(12)	CORRECTED EUROPEAN PATENT SPECIFICATION
	Note: Bibliography reflects the latest situation

(15)	Correction information:
	Corrected version no 1 (W1 B1)

(48)	Corrigendum issued on:
	16.06.2010 Bulletin 2010/24

(45)	Mention of the grant of the patent:
	31.03.2010 Bulletin 2010/13

(21)	Application number: 03788439.2

(22)	Date of filing: 13.08.2003

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International Patent Classification (IPC):

H01L 21/30^(2006.01)
H01L 21/3205^(2006.01)
H01L 21/336^(2006.01)
H01L 29/72^(2006.01)
H01L 29/94^(2006.01)

H01L 21/46^(2006.01)
H01L 21/332^(2006.01)
H01L 21/425^(2006.01)
H01L 29/76^(2006.01)
H01L 31/062^(2006.01)

(86)	International application number:
	PCT/US2003/025361

(87)	International publication number:
	WO 2004/017395 (26.02.2004 Gazette 2004/09)

(54)	PROCESS FOR FABRICATING AN ISOLATED FIELD EFFECT TRANSISTOR IN AN EPI-LESS SUBSTRATE VERFAHREN ZUR HERSTELLUNG EINES ISOLIERTEN FELDEFFEKT-TRANSISTORS IN EINEM EPI-LOSEN SUBSTRAT PROCEDE D'FABRICATION D'UN TRANSISTOR A EFFET DE CHAMP ISOLE DANS UN SUBSTRAT DEPOURVU DE COUCHE EPITAXIALE

(84)	Designated Contracting States:
	DE GB IT NL

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Priority:

14.08.2002 US 218668

(43)	Date of publication of application:
	22.06.2005 Bulletin 2005/25

(60)	Divisional application:
	10158458.9

(73)	Proprietor: Advanced Analogic Technologies, Inc.
	Sanza Clara, California 95054 (US)

(72)	Inventors:
	WILLIAMS, Richard, K. Cupertino, CA 95014 (US) CORNELL, Michael, E. Campbell, CA 95008 (US) CHAN, Wai Tien Tai Po, N.T., Hong Kong (CN)

(74)	Representative: Kirschner, Klaus Dieter et al
	Puschmann Borchert Bardehle Patentanwälte Partnerschaft Postfach 10 12 31 80086 München 80086 München (DE)

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References cited: :

WO-A-02/052649
GB-A- 2 320 812
US-A- 5 286 995
US-A- 5 798 295
US-A- 2001 000 288
US-B1- 6 251 757
US-B1- 6 359 317
US-B1- 6 391 754
US-B1- 6 501 131
US-B1- 6 630 699

WO-A-03/054950
JP-A- 2000 114 361
US-A- 5 569 620
US-A- 5 817 546
US-B1- 6 184 557
US-B1- 6 297 119
US-B1- 6 365 447
US-B1- 6 406 974
US-B1- 6 586 297
US-B2- 6 617 217

CONTIERO C ET AL: "LDMOS implementation by large tilt implant in 0.6 /spl mu/m BCD5 process, flash memory compatible" POWER SEMICONDUCTOR DEVICES AND ICS, 1996. ISPSD '96 PROCEEDINGS., 8TH INTERNATIONAL SYMPOSIUM ON MAUI, HI, USA 20-23 MAY 1996, NEW YORK, NY, USA,IEEE, US, 20 May 1996 (1996-05-20), pages 75-78, XP010165456 ISBN: 0-7803-3106-0
KUROI T ET AL: "BIPOLAR TRANSISTOR WITH A BURIED LAYER FORMED BY HIGH-ENERGY ION IMPLANTATION FOR SUBHALF-MICRON BIPOLAR-COMPLEMENTARY METAL OXIDE SEMICONDUCTOR LSIS" JAPANESE JOURNAL OF APPLIED PHYSICS, JAPAN SOCIETY OF APPLIED PHYSICS, TOKYO, JP, vol. 33, no. 1B, PART 1, January 1994 (1994-01), pages 541-545, XP000596411 ISSN: 0021-4922

Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).