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(11) | EP 1 545 046 A3 |
| (12) | EUROPEAN PATENT APPLICATION |
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| (54) | Improvements to data recovery circuits using oversampling for best data sample selection |
| (57) There is disclosed an improved data recovery circuit (10) based on an oversampling
technique to select the best data sample to be kept as the data to recover that is
only based on accumulating the data edges (or transitions). The incoming serial data
stream with jitter is oversampled in an oversampling circuit (12) by means of the
multiple phases of a reference clock (clk) to produce data samples. Each sample is
compared to the sample(s) collected with the next clock phase(s) in an edge detector
circuit (13) to determine the presence of a data edge and the edge information, representative
of the data edge positions, is stored and accumulated in a data edge memory (14) in
the form of a bit map for a duration that can be tuned. A selection determination
circuit (15) uses the memorized edge information to indicate which sample is the farthest
from the data edges. A selection validation circuit (16) has the key role of validating
the selection to avoid false determination due to jitter and skew. The validated values
of the selection signals are memorized in a selection memory (17). Finally, the memorized
validated selection signals and the data samples are exploited in a data sample selection
circuit (19) to recover the data while new data edges are processed and new selection
signals updated.
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