Method of manufacturing a semiconductor device having damascene structures with air gaps

(19)

(11)

EP 1 577 939 A3

(12)	EUROPEAN PATENT APPLICATION

(88)	Date of publication A3:
	03.11.2010 Bulletin 2010/44

(43)	Date of publication A2:
	21.09.2005 Bulletin 2005/38

(21)	Application number: 05003843.9

(22)	Date of filing: 23.02.2005

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International Patent Classification (IPC):

H01L 21/768^(2006.01)

(84)	Designated Contracting States:
	AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU MC NL PL PT RO SE SI SK TR
	Designated Extension States:
	AL BA HR LV MK YU

(30)

Priority:

18.03.2004 EP 04101107

(71)	Applicants:
	IMEC 3001 Leuven (BE) NXP B.V. 5656 AG Eindhoven (NL)

(72)	Inventors:
	Daamen, Roel 6061 NE Posterholt (NL) Verheijden, Greja Johanna Adriana Maria 5551 AT Valkenswaard (NL)

(74)	Representative: Bird, Ariane et al
	Bird Goën & Co Klein Dalenstraat 42A 3020 Winksele 3020 Winksele (BE)

(54)	Method of manufacturing a semiconductor device having damascene structures with air gaps

(57) A method for manufacturing a semiconductor device having damascene structures with air gaps is provided. The method comprises the steps of providing a substantially planar layer having a first metal layer (M1), depositing a via level dielectric layer (VL), patterning the via level dielectric layer (VL), at least partly etching the via level dielectric layer (VL), depositing a disposable layer (PR) on said at least partly etched via level dielectric layer (VL), patterning said disposable layer (PR), depositing a second metal layer (M2), planarizing second metal layer (M2), depositing permeable dielectric layer (PDL) after planarizing said second metal layer (M2), and removing said disposable layer (PR) through said permeable dielectric layer (PDL) to form air gaps (AG).

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