Method and apparatus involving capacitively coupled communication within a stack of laminated chips

Description

Field of the Invention

[0001] The present invention relates to techniques for communicating between integrated circuits. More specifically, the present invention relates to a method and an apparatus for using capacitively coupled communication techniques to communicate between stacked assemblies of laminated integrated circuit (IC) chips.

Background of the Invention

[0002] Advances in semiconductor technology have made it possible to fabricate a single IC (Integrated Circuit) chip that contains hundreds of millions of transistors. One of the advantages of integrating systems onto a single IC chip is that it increases the operating speed of the overall system. This is because in a multiple chip solution, the signals between system components have to cross chip boundaries, which typically reduces the system's operating speed due to the lengthy chip-to-chip propagation delays and limited chip-to-chip wires. In contrast, in a single chip solution, the signals between system components no longer have to cross chip boundaries, resulting in a significant increase in the overall system speed. Moreover, integrating systems onto a single IC chip significantly reduces overall costs, because fewer chips are required to perform a given computational task.

[0003] However, some systems cannot be integrated into a single chip due to their high complexity and large size. Note that IC chips are typically integrated onto a printed circuit board that contains multiple layers of signal lines for inter-chip communication. Furthermore, signal lines on an IC chip are about 100 times more densely packed than signal lines on a printed circuit board. Consequently, only a tiny fraction of the signal lines on a chip can be routed across the printed circuit board to other chips. Because of this reason, in such systems, inter-chip communication becomes the bottleneck for increasing the operating speed. Moreover, increases in IC integration densities are expected to exacerbate this bottleneck.

[0004] To overcome this inter-chip communication bottleneck, researchers have recently developed an alternative technique, known as "Proximity Communication", for communicating between semiconductor chips. Proximity communication involves integrating arrays of capacitive transmitters and receivers onto active surfaces of IC chips to facilitate inter-chip communication. If a first chip is situated face-to-face with a second chip so that transmitter regions on the first chip are capacitively coupled with receiver regions on the second chip, it is possible to transmit signals directly from the first chip to the second chip without having to route the signal through intervening signal lines within a printed circuit board.

[0005] Unfortunately, because proximity communication requires chips to be face-to-face it is not possible to stack more than two chips on top of each other. Hence, in order to couple a large number of chips together, it is necessary to arrange the chips so that they partially overlap in a pattern that alternates face-up and face-down chip orientations. This interconnection constraint can make it very hard to effectively combine such chips into a three-dimensional structure to save space and to reduce propagation delays between chips.

[0006] In addition to proximity communication techniques, a number of methods exist to laminate or permanently attach chips together and to create electrically conductive connections between the laminated chips. These laminated chip assemblies offer higher performance and faster communication, but suffer from the known-good-die problem.

[0007] The known-good-die problem arises from the fact that it is not possible to fully test a die at the wafer level or bare-die level. During wafer-level testing, faulty IC chips can be identified, but this technique is error prone, because chips must be assembled to be fully tested. Furthermore, since a single faulty chip can ruin an entire multi-chip assembly, the yield for a multi-chip assembly can be intolerably low for assemblies consisting of more than a few chips. For example, if a die lot has an actual yield of 80% (or 0.8), the cumulative yield for an assembly of three laminated dies is 0.8³ ≈ 0.5, while the cumulative yield for an assembly of ten laminated dies is 0.8¹⁰ ≈ 0.11. A low yield can result in a prohibitively high per-chip cost.

[0008] US-A-5, 629,838 describes a method and apparatus for constructing, repairing and operating modular electronic systems utilizes peripheral half-capacitors (i.e., conductive plates on the outside of the modules) to communicate non-conductively between abutting modules.

[0009] US-A-5,561,622 discloses an integrated memory cube structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip

[0010] US-A-2002/109236 discloses a three-dimensional, multi-chip package with chip selection pads formed at the chip-level formed by stacking a number of semiconductor integrated circuit chips. Each chip comprises an integrated circuit die, a chip selection terminal, chip selection pads, an insulation layer, metal wirings, upper connection terminals, lower connection terminals, and trench wirings. The chip selection terminal of each chip is separated from the chip selection of the other chips by the chip selection pads formed at the chip-level.

Summary of the Invention

[0011] The invention is defined in the claims.

[0012] One embodiment of the present invention provides a technique for assembling semiconductor chips. First, multiple semiconductor chips are permanently bonded together into a plurality of laminated chip assemblies, wherein the semiconductor chips within a laminated chip assembly communicate with each other through electrically conductive connections. Next, laminated chip assemblies are stacked together to form a stack of semiconductor chips without permanently bonding the laminated chip assemblies together, wherein the laminated chip assemblies communicate with each other using capacitive coupling.

[0013] Note that using this technique to stack (but not permanently bond) laminated chip assemblies together to form the stack of semiconductor chips helps to reduce the yield problem that exists for large stacks of permanently bonded semiconductor chips. Furthermore, using electrically conductive connections for inter-chip communication within the laminated chip assembly helps to reduce the interconnection constraints that are imposed due to the face-to-face chip orientation requirements of purely capacitive coupling techniques. Accordingly, such an approach can be used to provide a high-bandwidth, low-latency inter-chip communication method that does not suffer from the drawbacks described above in relation to existing systems.

[0014] In one embodiment, power is provided to the stack of semiconductor chips while avoiding the permanent attachment of a power supply to the stack of semiconductor chips.

[0015] In one embodiment, providing power to the stack of semiconductor chips involves using one or more of the following: capacitive coupling; inductive coupling; springs; fuzzbuttons; and/or anisotropic sheets.

[0016] In one embodiment, creating the electrically conductive connections between semiconductor chips in a laminated chip assembly involves using through-chip vias.

[0017] In one embodiment, the semiconductor chips in a laminated chip assembly can be different sizes and have different thicknesses.

[0018] In one embodiment, assembling the stack of semiconductor chips involves placing the laminated chip assemblies in an array, particularly a two-dimensional array. The two-dimensional array is arranged such that the capacitive communication regions are alternately oriented face-up and face-down on overlapping edges of the laminated chip assemblies.

[0019] In one embodiment, assembling the stack of semiconductor chips involves stacking laminated chip assemblies to form a three-dimensional array.

[0020] In one embodiment, the laminated chip assembly can include a carrier chip, which is laminated to one or more semiconductor chips. Note that the carrier chip maybe used to transfer signals from one laminated chip assembly to another laminated chip assembly.

[0021] In one embodiment, a laminated chip assembly is removed from the stack of semiconductor chips and replaced if one of the semiconductor chips in the laminated chip assembly is found to be malfunctioning.

Brief Description of the Drawings

[0022] Various embodiments of the invention will now be described in detail by way of example only with reference to the following drawings:

FIG. 1 illustrates semiconductor chips which use proximity communication in accordance with an embodiment of the present invention.

FIG. 2 illustrates a stack of semiconductor chips which uses proximity communication between laminated chip assemblies in accordance with an embodiment of the present invention.

FIG. 3 illustrates through-chip vias in a laminated chip assembly in accordance with an embodiment of the present invention.

FIG. 4 illustrates a tiled (two-dimensional) array of laminated chip assemblies in accordance with an embodiment of the present invention.

FIG. 5 illustrates a three-dimensional structure composed of layers of two-dimensional arrays of laminated chip assemblies in accordance with an embodiment of the present invention.

Detailed Description

Inter-Chip Communication using Proximity Communication

[0023] FIG. 1 illustrates semiconductor chips which use proximity communication in accordance with an embodiment of the present invention. As illustrated in FIG. 1, IC chip 110 contains transmitter circuitry 111, which feeds a signal into a capacitive transmitter region 112 in IC chip 110. This signal is capacitively transmitted to capacitive receiver region 122, and then passes into receiver circuitry 121 in IC chip 120. Note that when the transmitter and receiver regions are properly aligned, there is no direct physical contact between the transmitter and receiver regions, and signals are communicated between the transmitter and receiver regions through capacitive coupling.

Proximity Communication between Laminated Chip Assemblies

[0024] FIG. 2 illustrates a stack of semiconductor chips 205 which uses proximity communication between laminated chip assemblies in accordance with an embodiment of the present invention.

[0025] Laminated chip assemblies 200 and 201 are multi-chip assemblies wherein the constituent IC chips have been permanently laminated together using one of a number of known bonding techniques. Within laminated chip assemblies 200 and 201, communication occurs through direct electrically conductive connections. In other words, when chip 202 sends a signal to chip 203, the signal passes through a conductor directly from chip 202 to chip 203. Note that these conductors can possibly include through-chip vias.

[0026] In contrast, laminated chip assembly 200 and laminated chip assembly 201 communicate with each other not through direct electrical connections, but instead through proximity communication (across proximity communication regions 204).

[0027] Since there is no physical wiring between laminated chip assembly 200 and laminated chip assembly 201, no mechanical attachment is required. Hence, either laminated chip assembly 200 or laminated chip assembly 201 can be removed and replaced with an equivalent laminated chip assembly. Because either laminated chip assembly can be replaced, the failure of a single chip does not require the replacement of the entire stack of semiconductor chips 205, only the replacement of a single laminated chip assembly. Hence, the stack of semiconductor chips 205 has the connectivity advantages of laminated chip assemblies with respect to bandwidth, latency, and packing size while maintaining acceptable yields.

Through-Chip Vias

[0028] FIG. 3 illustrates through-chip vias in a laminated chip assembly 300 in accordance with an embodiment of the present invention. Laminated chip assembly 300 includes proximity communication region 302 and through-chip via 301.

[0029] Proximity communication normally takes place on the top surface of an IC chip within a laminated chip assembly, by utilizing the top layer or layers of the IC chip to facilitate capacitive coupling. However, proximity communication may utilize the bottom surface of the IC chip (through the silicon or insulator substrate material) using through-chip vias and metallization to construct proximity communication regions. Note that through-chip vias may already be used to conductively interconnect the laminated stack of chips, but through-chip vias can also be used to connect circuits within the non-interface IC chips of a laminated chip assembly (such as chip A and chip B in FIG. 3) to a proximity communication region.

[0030] Before being assembled, through-chip vias in each IC chip in laminated chip assembly 300 are etched and filled with metal. During assembly, an electrically conductive connection is made for the through-chip via 301 between chip A, chip B and chip C. Once electrically connected, the signal source in chip A can communicate with IC chips outside laminated chip assembly 300 through proximity communication region 302 located in chip C.

Two-Dimensional Tiled Arrays of Laminated Chip Assemblies

[0031] FIG. 4 illustrates a tiled (two-dimensional) array of laminated chip assemblies in accordance with an embodiment of the present invention. This two-dimensional array includes laminated chip assembly 401 and proximity communication regions 400. Laminated chip assembly 401 communicates with other laminated chip assemblies in the two-dimensional array via proximity communication regions 400.

[0032] Note that laminated chip assembly 401 is composed of IC chips of various sizes. The laminated chip assemblies can communicate with each other as long as their proximity communication regions align; there is no requirement that the constituent IC chips of the laminated assemblies have the same physical dimensions.

[0033] Note also that the IC chip that includes the proximity communication region can be a carrier, which only transfers signals and does not contain any active circuits. In this type of system, a signal may travel across several laminated chip assemblies before arriving at the laminated chip assembly where the signal is actually used.

Three-dimensional Matrices of Laminated Chip Assemblies

[0034] FIG. 5 illustrates a three-dimensional structure composed of layers of two-dimensional arrays of laminated chip assemblies in accordance with an embodiment of the present invention. As mentioned with respect to FIG. 3, laminated chip assemblies can have proximity communication regions on both the top and bottom faces. For example, proximity communication regions 501 include a proximity communication region on both the top and bottom faces of laminated chip assembly 500. When laminated chip assemblies have proximity communication regions on both top and bottom faces, layers of two-dimensional tiled arrays assembled from these laminated chip assemblies can be stacked into a three-dimensional matrix.

Power Connections to Laminated Chip Assemblies

[0035] Power can be supplied to the stack of semiconductor chips by a number of mechanisms. To avoid permanent attachment, power can be capacitively coupled, inductively coupled, or coupled by a combination of these two techniques. Also, to avoid permanent attachment, power can be conductively coupled through springs, micro-springs, fuzz buttons, or anisotropic sheets. Furthermore, semi-permanent attachment methods can bring in power conductively, thereby permitting limited re-work during assembly to replace defective laminated chip assemblies in stacks of semiconductor chips.

[0036] The foregoing descriptions of embodiments of the present invention have been presented for purposes of illustration in order to enable a person skilled in the art to appreciate and implement the invention. They are provided in the context of particular applications and their requirements, but are not intended to be exhaustive or to limit the present invention to the forms disclosed. Accordingly, many modifications and variations will be apparent to practitioners skilled in the art, and the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. Apparatus comprising:

a plurality of laminated chip assemblies (200,201; 300), wherein each laminated chip assembly comprises multiple semiconductor chips (202, 203; A, B, C), which are bonded permanently together to form the laminated chip assembly and which communicate with each other through electrically conductive connections;

wherein the plurality of laminated chip assemblies are stacked together to form a stack (205) of laminated chip assemblies without being permanently bonded to each other; and

wherein laminated chip assemblies communicate with each other through capacitive coupling (204; 302).

2. The apparatus of claim 1, further comprising a power supply mechanism that supplies power to the stack of semiconductor chips while avoiding permanent attachment to the stack of semiconductor chips.

3. The apparatus of claim 2, wherein the power supply mechanism transfers power to the stack of semiconductor chips through one or more of the following:

capacitive coupling;

inductive coupling;

springs;

fuzzbuttons; and

anisotropic sheets.

4. The apparatus of any preceding claim, wherein the electrically conductive connections between semiconductor chips in a laminated chip assembly involve through-chip vias (301).

5. The apparatus of any preceding claim, wherein the semiconductor chips in a laminated chip assembly have different sizes or different thicknesses.

6. The apparatus of claim 1, wherein the stack of semiconductor chips includes an array of laminated chip assemblies, which have capacitive communication surfaces that are alternately oriented face-up and face-down.

7. The apparatus of any preceding claim, wherein the array of laminated chip assemblies is two-dimensional.

8. The apparatus of any of claims 1 to 6, wherein laminated chip assemblies are stacked to form a three-dimensional array.

9. The apparatus of any preceding claim,
wherein a laminated chip assembly can include a carrier chip, which is laminated to one or more semiconductor chips;
wherein the carrier chip is used to transfer signals from one laminated chip assembly to another laminated chip assembly.

10. A method for assembling semiconductor chips, comprising:

forming a plurality of laminated chip assemblies (200, 201; 300), each laminated chip assembly being formed by permanently bonding multiple semiconductor chips (202, 203; A, B, C), together, wherein the semiconductor chips within each laminated chip assembly communicate with each other through electrically conductive connections ; and

stacking the laminated chip assemblies together to form a stack of semiconductor chips without permanently bonding the laminated chip assemblies together, wherein the laminated chip assemblies in the stack of semiconductor chips use capacitive coupling (204; 302) to communicate with each other.

11. The method of claim 10,
wherein the laminated chip assemblies are stacked so that capacitively coupled communication regions are aligned between faces of the laminated chip assemblies.

12. The method of claim 10 or 11, wherein the method further comprises providing power to the stack of semiconductor chips in a manner that avoids permanent attachment of a power supply to the stack of semiconductor chips.

13. The method of claim 12, wherein providing power to the stack of semiconductor chips involves using one or more of the following:

capacitive coupling;

inductive coupling;

springs;

fuzzbuttons; and

anisotropic sheets.

14. The method of any of claims 10 to 13, wherein creating the electrically conductive connections between semiconductor chips in a laminated chip assembly involves using through-chip vias (301).

15. The method of any of claims 10 to 14, wherein the semiconductor chips in a laminated chip assembly can be different sizes and can have different thicknesses.

16. The method of any of claims 10 to 15,
wherein assembling the stack of semiconductor chips involves placing the laminated chip assemblies in a two-dimensional array; and
wherein capacitive communication regions are alternately oriented face-up and face-down on the overlapping edges of the laminated chip assemblies.

17. The method of any of claims 10 to 16, wherein assembling the stack of semiconductor chips involves stacking the two-dimensional arrays of laminated chip assemblies to form a three-dimensional array.

18. The method of any of claims 10 to 17,
wherein the laminated chip assembly can include a carrier chip, which is laminated to one or more semiconductor chips; and
wherein the carrier chip is used to transfer signals from one laminated chip assembly to another laminated chip assembly.

19. The method of any of claims 10 to 18, wherein the method further comprises removing and replacing a laminated chip assembly from the stack of semiconductor chips when one of the semiconductor chips in the laminated chip assembly is malfunctioning.

20. A computer system including:

a processor;

a main memory; and

the apparatus of any of claims 1 to 9.

Ansprüche

1. Vorrichtung, umfassend:

mehrere laminierte Chip-Baugruppen (200, 201; 300), wobei jede laminierte Chip-Baugruppe mehrere Halbleiter-Chips (202, 203; A, B, C), umfasst, welche dauerhaft zusammengebondet sind, um eine laminierte Chip-Baugruppe auszubilden, und welche miteinander über elektrisch leitende Verbindungen kommunizieren;

wobei die mehreren laminierten Chip-Baugruppen zusammengestapelt sind, um einen Stapel (205) von laminierten Chip-Baugruppen auszubilden, ohne dauerhaft miteinander gebondet zu sein; und

wobei laminierte Chip-Baugruppen miteinander über kapazitive Kopplung (204; 302) kommunizieren.

2. Vorrichtung nach Anspruch 1, ferner umfassend einen Stromversorgungsmechanismus, der den Stapel von Halbleiter-Chips mit Strom versorgt, während dauerhafte Befestigung des Stapels von Halbleiter-Chips vermieden wird.

3. Vorrichtung nach Anspruch 2, wobei der Stromversorgungsmechanismus Strom zu dem Stapel von Halbleiter-Chips über ein oder mehrere der Folgenden überträgt:

kapazitive Kopplung;

induktive Kopplung;

Federn;

Fuzzbuttons; und

anisotrope Blätter.

4. Vorrichtung nach einem vorhergehenden Anspruch, wobei die elektrisch leitenden Verbindungen zwischen Halbleiter-Chips in einer laminierten Chip-Baugruppe Durch-Chip-Vias (301) involvieren.

5. Vorrichtung nach einem vorhergehenden Anspruch, wobei die Halbleiter-Chips in einer laminierten Chip-Baugruppe verschiedene Größen oder verschiedene Dicken aufweisen.

6. Vorrichtung nach Anspruch 1, wobei der Stapel von Halbleiter-Chips ein Array aus laminierten Chip-Baugruppen beinhaltet, welche kapazitive Kommunikationsoberflächen aufweisen, die abwechselnd nach oben und nach unten orientiert sind.

7. Vorrichtung nach einem vorhergehenden Anspruch, wobei das Array von laminierten Chip-Baugruppen zweidimensional ist.

8. Vorrichtung nach einem der Ansprüche 1 bis 6, wobei laminierte Chip-Baugruppen gestapelt sind, um ein dreidimensionales Array auszubilden.

9. Vorrichtung nach einem vorhergehenden Anspruch, wobei eine laminierte Chip-Baugruppe einen Träger-Chip beinhalten kann, welcher an einen oder mehrere Halbleiter-Chips laminiert ist;
wobei der Träger-Chip zum Übertragen von Signalen von einer laminierten Chip-Baugruppe zu einer anderen laminierten Chip-Baugruppe verwendet wird.

10. Verfahren zum Zusammensetzen von Halbleiter-Chips, umfassend:

Ausbilden von mehreren laminierten Chip-Baugruppen (200, 201; 300), wobei jede laminierte Chip-Baugruppe durch mehrere dauerhaft zusammengebondete Halbleiter-Chips (202, 203; A, B, C) ausgebildet wird, wobei die Halbleiter-Chips innerhalb jeder laminierten Chip-Baugruppe miteinander über elektrisch leitende Verbindungen kommunizieren; und

Zusammenstapeln der laminierten Chip-Baugruppen, um einen Stapel von laminierten Chip-Baugruppen auszubilden, ohne dauerhaft miteinander gebondet zu werden, wobei die laminierten Chip-Baugruppen in dem Stapel von Halbleiter-Chips kapazitive Kopplung (204; 302) verwenden, um miteinander zu kommunizieren.

11. Verfahren nach Anspruch 10,
wobei die laminierten Chip-Baugruppen derart gestapelt werden, dass kapazitiv gekoppelte Kommunikationsregionen zwischen Flächen der laminierten Chip-Baugruppen ausgerichtet sind.

12. Verfahren nach Anspruch 10 oder 11, wobei das Verfahren ferner Liefern von Strom an den Stapel von Halbleiter-Chips auf eine Weise, die dauerhaftes Befestigen einer Stromversorgung an dem Stapel von Halbleiter-Chips vermeidet, umfasst.

13. Verfahren nach Anspruch 12, wobei Liefern von Strom an den Stapel von Halbleiter-Chips ein oder mehrere der Folgenden involviert:

kapazitive Kopplung;

induktive Kopplung;

Federn;

Fuzzbuttons; und

anisotrope Blätter.

14. Verfahren nach einem der Ansprüche 10 bis 13, wobei Herstellen der elektrisch leitenden Verbindungen zwischen Halbleiter-Chips in einer laminierten Chip-Baugruppe Durch-Chip-Vias (301) involviert.

15. Verfahren nach einem der Ansprüche 10 bis 14, wobei die Halbleiter-Chips in einer laminierten Chip-Baugruppe verschiedene Größen oder verschiedene Dicken aufweisen können.

16. Verfahren nach einem der Ansprüche 10 bis 15, wobei Zusammensetzen des Stapels aus Halbleiter-Chips Platzieren der laminierten Chip-Baugruppen in einem zweidimensionalen Array involviert; und
wobei kapazitive Kommunikationsregionen an den überlappenden Kanten der laminierten Chip-Baugruppen abwechselnd nach oben und nach unten orientiert sind.

17. Verfahren nach einem der Ansprüche 10 bis 16, wobei Zusammensetzen des Stapels aus Halbleiter-Chips Stapeln der zweidimensionalen Arrays aus laminierten Chip-Baugruppen involviert, um ein dreidimensionales Array auszubilden.

18. Verfahren nach einem der Ansprüche 10 bis 17, wobei die laminierte Chip-Baugruppe einen Träger-Chip beinhalten kann, welcher an einen oder mehrere Halbleiter-Chips laminiert ist; und
wobei der Träger-Chip zum Übertragen von Signalen von einer laminierten Chip-Baugruppe zu einer anderen laminierten Chip-Baugruppe verwendet wird.

19. Verfahren nach einem der Ansprüche 10 bis 18, wobei das Verfahren ferner Entfernen und Ersetzen einer laminierten Chip-Baugruppe aus dem/in dem Stapel von Halbleiter-Chips, wenn einer der Halbleiter-Chips in der laminierten Chip-Baugruppe Fehlfunktion zeigt, umfasst.

20. Computersystem, aufweisend:

einen Prozessor;

einen Hauptspeicher; und

die Vorrichtung nach einem der Ansprüche 1 bis 9.

Revendications

1. Appareil comprenant :

une pluralité d'ensembles de puces stratifiées (200, 201 ; 300), chaque ensemble de puces stratifiées comprenant de multiples puces semi-conductrices (202, 203 ; A, B, C), qui sont liées entre elles de façon permanente pour former l'ensemble de puces stratifiées et qui communiquent les unes avec les autres par des connexions électriquement conductrices ;

dans lequel la pluralité d'ensembles de puces stratifiées sont empilés ensemble pour former un empilement (205) d'ensembles de puces stratifiées sans être liés entre eux de façon permanente ; et

dans lequel les ensembles de puces stratifiées communiquent les uns avec les autres par un couplage capacitif (204 ; 302).

2. Appareil de la revendication 1, comprenant en outre un mécanisme d'alimentation électrique qui alimente électriquement l'empilement de puces semi-conductrices tout en évitant une fixation permanente à l'empilement de puces semi-conductrices.

3. Appareil de la revendication 2, dans lequel le mécanisme d'alimentation électrique transfère de l'énergie à l'empilement de puces semi-conductrices par un ou plusieurs des éléments suivants :

couplage capacitif ;

couplage inductif ;

ressorts ;

boutons Fuzz Button ; et

feuilles anisotropes.

4. Appareil d'une quelconque revendication précédente, dans lequel les connexions électriquement conductrices entre puces semi-conductrices dans un ensemble de puces stratifiées impliquent des trous d'interconnexion à travers les puces (301).

5. Appareil d'une quelconque revendication précédente, dans lequel les puces semi-conductrices dans un ensemble de puces stratifiées ont différentes tailles ou différentes épaisseurs.

6. Appareil de la revendication 1, dans lequel l'empilement de puces semi-conductrices comporte un réseau d'ensembles de puces stratifiées, qui ont des surfaces de communication capacitive qui sont orientées en alternance face vers le haut et face vers le bas.

7. Appareil d'une quelconque revendication précédente, dans lequel le réseau d'ensembles de puces stratifiées est bidimensionnel.

8. Appareil de l'une quelconque des revendications 1 à 6, dans lequel les ensembles de puces stratifiées sont empilés pour former un réseau tridimensionnel.

9. Appareil d'une quelconque revendication précédente,
dans lequel un ensemble de puces stratifiées peut comporter une puce de support, qui est stratifiée avec une ou plusieurs puces semi-conductrices ;
dans lequel la puce de support est utilisée pour transférer des signaux d'un ensemble de puces stratifiées à un autre ensemble de puces stratifiées.

10. Procédé d'assemblage de puces semi-conductrices, comprenant :

la formation d'une pluralité d'ensembles de puces stratifiées (200, 201 ; 300), chaque ensemble de puces stratifiées étant formé en liant ensemble de façon permanente de multiples puces semi-conductrices (202, 203 ; A, B, C), les puces semi-conductrices à l'intérieur de chaque ensemble de puces stratifiées communiquant les unes avec les autres par des connexions électriquement conductrices ; et

l'empilement des ensembles de puces stratifiées pour former un empilement de puces semi-conductrices sans lier ensemble de façon permanente les ensembles de puces stratifiées, les ensembles de puces stratifiées dans l'empilement de puces semi-conductrices utilisant un couplage capacitif (204 ; 302) pour communiquer les uns avec les autres.

11. Procédé de la revendication 10,
dans lequel les ensembles de puces stratifiées sont empilés de telle sorte que des régions de communication couplées capacitivement sont alignées entre faces des ensembles de puces stratifiées.

12. Procédé de la revendication 10 ou 11, le procédé comprenant en outre l'alimentation électrique de l'empilement de puces semi-conductrices d'une manière qui évite une fixation permanente d'une alimentation électrique à l'empilement de puces semi-conductrices.

13. Procédé de la revendication 12, dans lequel l'alimentation électrique de l'empilement de puces semi-conductrices implique l'utilisation d'un ou plusieurs des éléments suivants :

couplage capacitif ;

couplage inductif ;

ressorts ;

boutons Fuzz Button ; et

feuilles anisotropes.

14. Procédé de l'une quelconque des revendications 10 à 13, dans lequel la création des connexions électriquement conductrices entre puces semi-conductrices dans un ensemble de puces stratifiées implique l'utilisation de trous d'interconnexion à travers les puces (301).

15. Procédé de l'une quelconque des revendications 10 à 14, dans lequel les puces semi-conductrices dans un ensemble de puces stratifiées peuvent être de différentes tailles et peuvent avoir différentes épaisseurs.

16. Procédé de l'une quelconque des revendications 10 à 15,
dans lequel l'assemblage de l'empilement de puces semi-conductrices implique le positionnement des ensembles de puces stratifiées dans un réseau bidimensionnel ; et
dans lequel des régions de communication capacitive sont orientées en alternance face vers le haut et face vers le bas sur les bords se chevauchant des ensembles de puces stratifiées.

17. Procédé de l'une quelconque des revendications 10 à 16, dans lequel l'assemblage de l'empilement de puces semi-conductrices implique l'empilement des réseaux bidimensionnels d'ensembles de puces stratifiées pour former un réseau tridimensionnel.

18. Procédé de l'une quelconque des revendications 10 à 17,
dans lequel l'ensemble de puces stratifiées peut comporter une puce de support, qui est stratifiée avec une ou plusieurs puces semi-conductrices ; et
dans lequel la puce de support est utilisée pour transférer des signaux d'un ensemble de puces stratifiées à un autre ensemble de puces stratifiées.

19. Procédé de l'une quelconque des revendications 10 à 18, le procédé comprenant en outre le retrait et le repositionnement d'un ensemble de puces stratifiées de l'empilement de puces semi-conductrices quand une des puces semi-conductrices dans l'ensemble de puces stratifiées est défectueuse.

20. Système informatique comportant :

un processeur ;

une mémoire principale ; et

l'appareil de l'une quelconque des revendications 1 à 9.

Drawing