(19)
(11) EP 1 644 855 A1

(12)

(43) Date of publication:
12.04.2006 Bulletin 2006/15

(21) Application number: 03818146.7

(22) Date of filing: 14.07.2003
(51) International Patent Classification (IPC): 
G06F 17/50(1995.01)
(86) International application number:
PCT/US2003/021997
(87) International publication number:
WO 2005/017785 (24.02.2005 Gazette 2005/08)
(84) Designated Contracting States:
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PT RO SE SI SK TR

(71) Applicant: Cadence Design Systems, Inc.
San Jose, CA 95134 (US)

(72) Inventors:
  • Sheffer, Louis K.
    Campbell, CA 95008 (US)
  • Yoshida, Kenji
    Inagi-shi Tokyo 206-0803 (JP)
  • Abe, Yoshikuni
    Yokohama-shi, Kanagawa 226-0001 (JP)
  • Fujimura, Aki
    Saratoga, CA 95070 (US)
  • Pack, Robert C.
    Foster City, CA 94404 (US)

(74) Representative: Viering, Jentschura & Partner 
Steinsdorfstrasse 6
80538 München
80538 München (DE)

   


(54) METHOD FOR CREATING PATTERNS FOR PRODUCING INTEGRATED CIRCUITS