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(11) | EP 1 657 753 A2 |
| (12) | EUROPEAN PATENT APPLICATION |
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| (54) | Nonvolatile memory device including one resistor and one diode |
| (57) A nonvolatile memory device includes one resistor and one diode. The device includes
a lower electrode; a resistor structure disposed on the lower electrode; a diode structure
disposed on the resistor structure; and an upper electrode disposed on the diode structure.
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BACKGROUND OF THE INVENTION
[0001] The present invention relates to a nonvolatile memory device including one resistor and one diode.
[0002] In recent years, a lot of studies have been made of a semiconductor memory device that increases the number of memory cells per area (i.e., integration density) and operating speed and can be driven with low power, and various kinds of memory devices have been developed.
[0003] In general, a semiconductor memory device includes many memory cells that are connected through circuits. In a dynamic random access memory (DRAM) that is a representative semiconductor memory device, a unit memory cell is typically comprised of one switch and one capacitor. Such a DRAM is advantageous for high integration density and fast operating speed. However, when power supply is cut off, the DRAM loses all stored data.
[0004] By comparison, some nonvolatile memory devices, such as a flash memory device, can retain stored data even if power supply is abruptly interrupted. The flash memory device has a nonvolatile characteristic but has lower integration density and slower operating speed than a volatile memory device.
[0005] Nowadays, such nonvolatile memory devices as a magnetic random access memory (MRAM), a ferroelectric random access memory (FRAM), and a phase-change random access memory (PRAM) are laboriously under study.
[0006] The MRAM stores data using a change of magnetization direction in a tunnel junction, and the FRAM stores data using a polarization direction of a ferroelectric material. Although the MRAM and FRAM have individual merits and demerits, they basically have high integration density and fast operating speed and can be driven with low power as described above. Also, research is being carried out in a good data retention characteristic of the MRAM and FRAM.
[0007] Further, the PRAM is a memory that stores data using a certain material's characteristic, namely, a variation in resistance with respect to a phase change, and includes one resistor and one switch (transistor). The resistor used for the PRAM is a calcogenide resistor, which becomes crystalline or amorphous according to temperature that is controlled when the resistor is formed. The PRAM is formed on the principle that a crystalline resistor is typically more resistive than an amorphous resistor. In fabricating the PRAM using a conventional DRAM process, performing an etch process becomes complicated and takes much time. Accordingly, the productivity of memory devices decreases and the cost of production increases, thus weakening the competitiveness of the devices.
SUMMARY OF THE INVENTION
[0008] According to an aspect of the present invention, there is provided a nonvolatile memory device including one resistor and one diode. The device includes a lower electrode; a resistor structure disposed on the lower electrode; a diode structure disposed on the resistor structure; and an upper electrode disposed on the diode structure.
[0009] The invention thus provides a nonvolatile memory device including one resistor and one diode, which is fabricated in a simple process, can be driven with low power, and has fast operating speed.
[0010] The resistor structure may include a buffer layer disposed on the lower electrode; and a data storage layer disposed on the buffer layer.
[0011] The resistor structure may be formed of at least one of NiO, TiO2, HfO, ZrO, ZnO, WO3, CoO, and Nb2O5.
[0012] The diode structure may include a first oxide layer disposed on the resistor structure; and a second oxide layer disposed on the first oxide layer. Also, the first oxide layer may be formed of p-type oxide, and the second oxide layer may be formed of n-type oxide.
[0013] According to another aspect of the present invention, there is provided an array of a nonvolatile memory device including one resistor and one diode. The array includes at least two bit lines arranged at regular intervals; at least two word lines arranged at regular intervals and disposed across the bit lines; a resistor structure disposed on the bit lines at each of the intersections of the bit lines and word lines; and a diode structure disposed in contact with the resistor structure and the word lines.
BRIEF DESCRIPTION OF THE DRAWINGS
[0014] The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:
FIG. 1A illustrates a nonvolatile memory device including one resistor and one diode according to an exemplary embodiment of the present invention;
FIG. 1B is a graph showing characteristics of materials used for the nonvolatile memory device including one resistor and one diode as shown in FIG. 1;
FIG. 2 illustrates an array structure of the nonvolatile memory device including one resistor and one diode as shown in FIG. 1;
FIG. 3 is an equivalent circuit diagram of the array of the nonvolatile memory device including one resistor and one diode as shown in FIG. 2;
FIG. 4 is a graph showing operating characteristics of the nonvolatile memory device including one resistor and one diode as shown in FIG. 1; and
FIG. 5 is a diagram for explaining the operating principle of the nonvolatile memory device including one resistor and one diode as shown in FIGS. 2 and 3.
DETAILED DESCRIPTION OF THE INVENTION
[0015] A nonvolatile memory device including one resistor and one diode according to the present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown.
[0016] FIG. 1A is a cross sectional view of a nonvolatile memory device including one resistor and one diode according to an exemplary embodiment of the present invention.
[0017] Referring to FIG. 1A, the memory device includes a substrate 10, a lower electrode 11, resistance layers 12 and 13, a diode structure 14 and 15, and an upper electrode 16, which are sequentially stacked. Here, the resistance layers 12 and 13 function as a data storage portion. A first resistance layer 12 acts as a buffer layer, and a second resistance layer 13 acts as a data storage layer. The first resistance layer 12, which acts as the buffer layer, may be optionally formed. The diode structure 14 and 15 is a p-n junction structure and includes a first oxide layer 14 and a second oxide layer 15.
[0018] In this case, the substrate 10 may be a semiconductor substrate, such as a Si substrate, that is used for a typical semiconductor device. The lower and upper electrodes 11 and 16 may be formed of a conductive material, such as a metal, that is typically used for an electrode of a semiconductor device. In particular, a material for the lower electrode 11 may be selectively determined according to the kind of material formed thereon. The first and second resistance layers 12 and 13 are formed on the lower electrode 11. The first and second resistance layers 12 and 13 may be formed of transition metal oxide, for example, at least one of NiO, TiO2, HfO, ZrO, ZnO, WO3, CoO, and Nb2O5. The first and second resistance layers 12 and 13 may be formed of the same material, for example, NiO.
[0019] The first oxide layer 14 may be formed of p-type oxide, and the second oxide layer 15 may be formed of n-type oxide. For example, the first and second oxide layers 14 and 15 may be formed of transparent metal oxide with a controlled fraction of oxygen. The transition metal oxide has an electrical characteristic, which varies with the amount of oxygen combined with transition metal. The first and second oxide layers 14 and 15 may be formed of the same material as the second resistance layer 13, but they may exhibit a p-type semiconductor characteristic or an n-type semiconductor characteristic by increasing a fraction of oxygen more than the second resistance layer 13. Hereinafter, the first oxide layer 14 and the second oxide layer 15 will be referred to a p-type oxide layer 14 and an n-type oxide layer 15, respectively.
[0020] FIG. 1B is a graph showing characteristics of materials used for the nonvolatile memory device including one resistor and one diode as shown in FIG. 1. Specifically, FIG. 1B shows a variation in resistance with respect to a fraction oxgen partial pressure for formation of NiOx.
[0021] Referring to FIG. 1B, when a fraction of oxygen in NiOx is extremely low (region "A"), NiOx is similar in characteristics to Ni. However, as the fraction of oxygen gradually increases (region "B"), resistance greatly increases, thus showing a switching characteristic. As the fraction of oxygen further increases (region "C"), resistance gradually decreases, thus showing a semiconductor characteristic. Any one of the resistance layers 12 and 13, the p-type oxide layer 14, and the n-type oxide layer 15 may be formed of transition metal oxide, such as NiOx, with a controlled fraction of oxygen. In a manufacturing process, the resistance layers 12 and 13, the p-type oxide layer 14, and the n-type oxide layer 15 may be sequentially formed in-situ by depositing the same transition metal on a sample using sputtering while appropriately controlling the amount of oxygen gas injected into a reaction chamber. Of course, it is obvious that the above-described transition metal oxides other than NiO and a combination thereof can exhibit similar characteristics.
[0022] FIG. 2 illustrates an array structure of the nonvolatile memory array including one resistor and one diode as shown in FIG. 1.
[0023] Referring to FIG. 2, a plurality of lower electrodes 11 are disposed at regular intervals, and a plurality of upper electrodes 16 are disposed across the lower electrodes 11. Also, resistance layers 12 and 13 and a p-n junction diode structure 14 and 15 are formed at each of the intersections of the lower electrodes 11 and the upper electrodes 16.
[0024] FIG. 3 is an equivalent circuit diagram of the array of the nonvolatile memory device including one resistor and one diode as shown in FIG. 2.
[0025] Hereinafter, the electrical characteristics of the second resistance layer 13 of the nonvolatile memory device including one resistor and one diode according to the exemplary embodiment of the present invention will be described with reference to FIG. 4. In FIG. 4, a horizontal axis refers to voltage applied through the upper and lower electrodes 16 and 11, and a vertical axis refers to current that passes through the second resistance layer 13.
[0026] FIG. 4 shows two current-voltage curves G1 and G2. The curve G1 shows a case where the resistance of the second resistance layer 13 is lowered, that is, current that passes through the second resistance layer 13 is higher for the same voltage. By comparison, the curve G2 shows a case where the resistance of the second resistance layer 13 is elevated, that is, current that passes through the second resistance layer 13 is lower for the same voltage. In the present invention, the semiconductor memory device including one resistor and one diode makes use of different current-resistance characteristics, as will now be described in detail.
[0027] At the outset, when applied voltage is gradually increased from 0V to 1V, current increases in proportion to the voltage along the curve G1. However, with the application of V1, current is suddenly reduced and varied along the curve G2. This phenomenon is continued also in the range of V1≤ V ≤ V2. Also, when voltage is applied in the range of V2 < V, current increases along the curve G1 again. Here, resistance in the curve G1 is referred to as a first resistance, and resistance in the curve G2 is referred to as a second resistance. That is, it can be seen that the resistance of the second resistance layer 13 sharply increases in the range of V1 ≤ V ≤ V2.
[0028] Also, the present inventor confirmed that the nonvolatile memory device including one resistor and one diode according to the present invention had the following characteristics. Initially, after voltage is applied in the range of V1 ≤ V ≤ V2, when voltage is applied in the range of V < V1, current is detected based on the curve G2. After voltage is applied in the range of V2 < V, when voltage is applied in the range of V < V1, current is detected based on the curve G1. Accordingly, the nonvolatile memory device can properly operate using the above-described characteristics.
[0029] That is, in the nonvolatile memory device including one resistor and one diode according to the exemplary embodiment of the present invention, when voltage is applied in the range of V2 < V through the lower and upper electrodes 11 and 16, the first resistance is stored in the second resistance layer 13. Also, when voltage is applied in the range of V1 ≤ V ≤ V2, the second resistance is stored in the second resistance layer 13. By applying a voltage less than V1 and reading a current value, a state of memory stored in the second resistance layer 13 can be read.
[0030] FIG. 5 is a diagram for explaining the operating principle of the nonvolatile memory device including one resistor and one diode as shown in FIGS. 2 and 3. FIG. 5 illustrates four memory cells 'aa', 'ab', 'ba', and 'bb', and each of bit lines B1 and B2 and word lines W1 and W2 is shared by a pair of cells.
[0031] A process of storing the first resistance (of the curve G1 of FIG. 4) in the second resistance layer 13 is referred to as a program process (set), and a process of storing the second resistance (of the curve G2 of FIG. 4) in the second resistance layer 13 is referred to as an erase process (reset).
[0032] In order to store the first resistance in the cell 'aa' of FIG. 5, a voltage of V2 or higher should be applied. For this operation, a voltage of V0 (V2< V0) is applied to the bit line B1 and the word line W2. In this case, the cells 'ab' and 'ba' do not operate because there is no difference in electric potential between upper and lower electrodes. Also, the cell 'bb' does not operate because a reverse voltage is applied thereto. Therefore, the first resistance is stored only in the cell 'aa'.
[0033] Thereafter, in order to store the second resistance in the cell 'aa', a voltage of V1≤ V ≤ V2 should be applied. For this operation, a voltage of V1≤ V ≤ V2 is applied only to the bit line B1 and the word line W2, and the bit line B2 and the word line W1 are grounded. Accordingly, the first resistance is erased from the second resistance layer 13 of the cell 'aa' and the second resistance is programmed in the second resistance layer 13. The first resistance may be designated as '0' and the second resistance may be designated as '1,' and the reverse designation is also possible.
[0034] Further, a resistance state of the second resistance layer 13 that is a data storage layer of the cell 'aa' can be read using a current value that is measured by applying a voltage Vr less than V1 to the cell 'aa'. In this case, the voltage Vr is applied only to the bit line B1 and the word line W2 as described above, it is determined whether the measured current corresponds to the curve G1 or the curve G2 of FIG. 4, and stored data is read.
[0036] First, a unit cell structure of a nonvolatile memory device includes one diode and one resistor, which are sequentially stacked. Thus, the nonvolatile memory device and an array cell structure thereof are structurally very simple.
[0037] Second, the nonvolatile memory device of the present invention can be formed using conventional DRAM manufacturing processes. Unlike a memory device including a typical switching device, a resistance layer and a diode structure formed thereon can be formed in-situ by controlling a fraction of oxygen. As a result, the manufacture of the nonvolatile memory device is very simple, so that productivity is elevated and the cost of production is lowered.
[0038] Third, considering the operating principle of the present invention, data can be stored and reproduced in a simple method using materials with unique characteristics, thus enabling high-speed operation of the device.
[0039] While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the scope of the present invention as defined by the following claims.
1. A nonvolatile memory device including one resistor and one diode comprising:
a lower electrode;
a resistor structure disposed on the lower electrode;
a diode structure disposed on the resistor structure; and
an upper electrode disposed on the diode structure.
2. The device according to claim 1, wherein the resistor structure includes:
a buffer layer disposed on the lower electrode; and
a data storage layer disposed on the buffer layer.
3. The device according to claim 1 or 2, wherein the resistor structure is formed of
at least one selected from the group consisting of NiO, TiO2, HfO, ZrO, ZnO, WO3, CoO, and Nb2O5.
4. The device according to any preceding claim, wherein the diode structure includes:
a first oxide layer disposed on the resistor structure; and
a second oxide layer disposed on the first oxide layer.
5. The device according to claim 4, wherein the first oxide layer is formed of p-type
oxide, and the second oxide layer is formed of n-type oxide.
6. The device according to claim 5, wherein any one of the p-type oxide and n-type oxide
is formed of at least one selected from the group consisting of NiO, TiO2, HfO, ZrO, ZnO, WO3, CoO, and Nb2O5.
7. An array of a nonvolatile memory device including one resistor and one diode, the
array comprising:
at least two bit lines arranged at regular intervals;
at least two word lines arranged at regular intervals and disposed across the bit lines;
a resistor structure disposed on the bit lines at each of the intersections of the bit lines and word lines; and
a diode structure disposed in contact with the resistor structure and the word lines.
8. The array according to claim 7, wherein the resistor structure includes:
a buffer layer disposed on the lower electrode; and
a data storage layer disposed on the buffer layer.
9. The array according to claim 7 or 8, wherein the resistor structure is formed of at
least one selected from the group consisting of NiO, TiO2, HfO, ZrO, ZnO, WO3, CoO, and Nb2O5.
10. The array according to claim 7, 8 or 9, wherein the diode structure includes:
a first oxide layer disposed on the resistor structure; and
a second oxide layer disposed on the first oxide layer.
11. The array according to claim 10, wherein the first oxide layer is formed of p-type
oxide, and the second oxide layer is formed of n-type oxide.
12. The array according to claim 10, wherein any one of the p-type oxide and n-type oxide
is formed of at least one selected from the group consisting of NiO, TiO2, HfO, ZrO, ZnO, WO3, CoO, and Nb2O5.