(19)
(11) EP 1 665 049 A2

(12)

(88) Date of publication A3:
26.01.2006

(43) Date of publication:
07.06.2006 Bulletin 2006/23

(21) Application number: 04784098.8

(22) Date of filing: 13.09.2004
(51) International Patent Classification (IPC): 
G06F 11/00(1968.09)
G01R 31/3185(1995.01)
H01L 21/66(1974.07)
(86) International application number:
PCT/US2004/030127
(87) International publication number:
WO 2005/029329 (31.03.2005 Gazette 2005/13)
(84) Designated Contracting States:
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PL PT RO SE SI SK TR
Designated Extension States:
AL HR LT LV MK

(30) Priority: 15.09.2003 US 503710 P
18.12.2003 US 740779
18.12.2003 US 740722
18.12.2003 US 740721
18.12.2003 US 740723
23.06.2004 US 876340

(71) Applicant: NVIDIA Corporation
Santa Clara, CA 95050 (US)

(72) Inventors:
  • DIAMOND, Michael, B.
    Los Gatos, CA 95032 (US)
  • MONTRYM, John, S.
    Cupertino, CA 95014 (US)
  • VAN DYKE, James, M.
    Austin, TX 78750 (US)
  • NAGY, Michael, B.
    Agoura Hills, CA 91301 (US)
  • TREICHLER, Sean, J.
    Mountain View, CA 94040 (US)

(74) Representative: Ebner von Eschenbach, Jennifer et al
LADAS & PARRY LLP Dachauerstrasse 37
80335 München
80335 München (DE)

   


(54) A SYSTEM AND METHOD FOR TESTING AND CONFIGURING SEMICONDUCTOR FUNCTIONAL CIRCUITS