Hybrid digital cross-connect for switching circuit and packet based data traffic

Abstract

 A network node includes bidirectional interfaces having first ports for ingress/egress of circuit and/or packet based traffic from/to the network and second ports connected to a Hybrid Switch capable of routing mixed traffic through the node. The connection between the second ports and the Hybrid Switch is carried out by an unique SDH bus on the backplane which transport said mixed circuit and packet based traffic. An interface for mixed Ethernet packet and circuit based traffic forwards the VCs relevant to circuits to a combiner at the second port. For each packet entering the node the interface generates a VLAN-ID from the MAC addresses and maps it onto a CID identifier only usable inside the Hybrid Switch. A GFP framer inserts the CID in the GFP header and encapsulates the packet, without VLAN-ID, into the GFP payload. GFP frames so arranged are embedded into VC-4 containers, which are combined with the VCs relevant to circuits into an STM-16 flow directed to the Hybrid Switch. The latter receives and synchronizes all the m received STM-16 flows and for each flow disassembles the VCs and sends each byte of VCs carrying circuit based transport signal to an m-input multiplexer belonging to a Circuit Switch. For the VC-4s carrying packets, the Hybrid Switch sends each byte of n concatenated VC-4 to a set of m x m-input multiplexers belonging to a Packet Switch. The latter performs the delineation on the GFP frames, retrieves the CID and PLI contents from the header and sends their values to a Router. The m-input multiplexers both for circuits and packets are univocally associated to the m STM-16 input channels, so that all traffic node is considered simultaneously. The outputs of the m packet multiplexers are stored into m buffers to be sent together with the output of the circuit multiplexer to the inputs of a final multiplexer, whose output signal is sent to a STM-16 former followed by a serializer. Routing tables are stored in advance for packets and circuits. According to the routing tables, the Router of the Hybrid Switch, selects for the m circuit multiplexers the one out of m inputs to be forwarded to the output, while similar selection for the m packet multiplexers is performed from the received CIDs and PLIs values. The Centralized Router also controls the final multiplexer to output either packets or circuits. Finally, the VCs are completed with headers and pointers and the resulting STM-16 flows are forwarded on the SDH output bus towards the interfaces. The interfaces perform dual operations with respect of the former direction, particularly reinsert the VLAN-IDs in the payloads of the switched GFP frames.

Description

FIELD OF THE INVENTION

[0001] The present invention relates to the field of digital communications networks, and more precisely to a hybrid digital cross-connect (DCX) for switching circuits and packets transport signals under standard interfaces.

[0002] To simplify the disclosure, used acronyms are listed in APPENDIX A and bibliographic References are given in APPENDIX B.

[0003] As known, digital communications networks are subdivided in circuit or packet ones based on the used transport. Typical circuit-fashioned networks for high capacity traffic make use of: PDH, SDH, SONET, OTN, DWDM, or the like physical layers; while examples of packet networks are: ATM, Ethernet, Token Ring, IP,MPLS etc. Circuit and packet transports show very different characteristics to each other: the first is distinguished by a fixed connection which stands up for all the call duration with constant dedicated bandwidth assignment, while the second is connectionless or even connection-oriented, but the available bandwidth is shared between more users according to a (fair) scheduling criterion. Despite the underlined differences, suboptimum uses of the two types of networks have been largely implemented in the course of the years to the aim of using a network for transmitting signals best suitable to be transmitted on the other type of transport. A first example is packet data transmitted via modem over a circuit connection. A second example is a streaming signal transmitted over a packet transport, e.g.: ATM AAL1 used for circuit emulation, or Voice over IP.

[0004] The two approaches are now considered on the light of continuously increasing service demand to the operators, either incumbent or new coming ones. Incumbent operators with a large basis of installed SDH equipments are evolving toward a so called MSPP based solution which integrates into a traditional SDH node (ADM) those new functionalities identified as NG-SDH and comprising VCat, GFP, and LCAS, which allow more effective and flexible transportation of Ethernet based services like: Ethernet Private Line, Ethernet Private LAN, etc. This approach, usually identified as EoSDH is characterized by a compromise between the exploitation of the already deployed infrastructure and a less optimized packet-oriented service implementation.

[0005] As opposite to the Incumbent approach, new coming operators, or operators with less installed legacy-SDH base are attracted by the idea of adopting a solution based on a pure packet approach. In this case, the network is optimized for the packet and whenever a circuit or a TDM service is required, solution is offered throughout CES or ToCES. Circuit emulation approach is quite a complex function and requires a certain amount of sophisticated and expensive circuitry/algorithms (see [MEFD00029]) which need to be realized for adapting a time continuous TDM (PDH or SDH) signal to be transmitted over a packet switched network. Furthermore, this solution is quite new, not yet completely standardized, very preliminary devices with very limited capacity and from small new companies have until now been offered. Very limited verification in real network application has been until now conducted and therefore cannot be considered a trustable solution yet. Another consideration we can make is that circuit emulation, requiring the conversion of the TDM signal in a packet format and vice versa, is certainly more expensive respect to the case of remaining in a circuit switched context, and if it can be acceptable when the number of TDM interfaces is very small, it becomes extremely inconvenient as soon as this number is comparable with the number of interfaces carrying packets.

[0006] In conclusion, the proposed solutions for the two types of suboptimal scenarios are not completely satisfactory because the network performances are not guaranteed and standards are only in a preliminary/draft state. Nowadays a platform able to combine the characteristics of an SDH (or similar) network element for circuit / TDM transport and the pure packet approach for the new Ethernet/IP services, would be ideal. In this case operators would adopt a single network element and could tuned its configuration, toward packet or circuit, according to their specific needs or the specific network context application.

BACKGROUND ART

[0007] A serious approach to the desired network element is disclosed in the International Patent Application WO200217580-A1, titled: "DUAL SWITCH ARCHITECTURE FOR MIXED PACKET AND CIRCUIT TRANSPORTS OVER SONET AND SDH AND DWDM". With reference to fig.1, a dual switch architecture for mixed packet and circuit transports over SONET and SDH and DWDM is provided. The dual switch architecture includes: a TDM circuit cross connect module (210), a packet switch module (220), interface modules (230) with one or more ports, a bi-directional TDM bus (215) between the TDM circuit cross connect module (210) and the packet switch module (220), a point-to-point bi-directional TDM connection (280) between each interface module (230) and the TDM circuit cross connect module (210), and a point-to-point bi-directional packet connection (290) between each interface module (230) and the packet switch module (220). Every port can be either packet or circuit interface. Every interface card has connections to both cross-connect block and the packet switch block simultaneously. The architecture is defined to add/drop mixed circuit/packet traffic from/to local ports to/from SONET ring. Virtual concatenation is provided in the node for creating a logical connection by combining multiple n STS-1 or VT, which can be contiguous or not, into a single connection NxSTS-1 or NxVT, respectively, in order to support a flexible adaptation of the SONET/SDH bandwidth to the throughput required from the packet traffic. Similar concepts are applied to concatenate the AU-n into NxAU-n in SDH. In case of circuit connections, the data is fed to the cross-connection block directly through the (280) lines. The cross-connect card performs circuit cross-connect and route the circuit to the trunk card for SONET ring. The trunk card is itself one of interface cards. In case of packet connections, the packet is buffered at the interface card and sent to the packet switch block through the (290) line. The packet switch (220) then performs all the packet switching to route each packet to its destination either to line (290) towards another interface card or to the internal TDM bus (215) towards the cross-connect (210) to be treated as a circuit connection. A logical circuit connection is setup as a label switch path LSP on the ring to carry a forward equivalent class of MPLS packets [RFC3036]. In this way, all packets from the interface ports on a node element can be aggregated into the same LSP as long as they share the same destination and CoS. In addition, the MPLS LDP protocol [RFC3031] with bandwidth reservation capability can be used to dynamically increase/decrease/setup/tear down the virtual concatenated LSP according to the actual traffic need.

OUTLINED TECHNICAL PROBLEM

[0008] A very critical problem limiting the growth of the SDH apparatuses towards higher STM-N applications is the difficulty to implement a high speed serial bus on the backplane. To overcome this difficulty some former solutions proposed to demultiplex the incoming STM-N into M signals transmitted on M serial buses with lower bitrate on the backplane, then switching the VC-N acting on the columns of the SDH matrix , and re-multiplexing the columns at the end. This is a clear sign of the difficulties inherent in the backplane. Another drawback affecting signals travelling on the backplane is the cross-talk noise induced by the adjacent lines. A good design for SDH apparatuses should make use of an unique high speed bus on the backplane avoiding as far as possible duplications. In this optic, the design of backplane interconnections is not optimized in the dual switch architecture of the nearest prior art. In fact, from the sole fig.2, the only inferable implementation is that the backplane interconnection between each interface cards unit and the two centralized devices for packet and circuit transports is duplicated, namely: one link set provides the transport of packet based traffic, another link set provides to transport circuit based traffic. The following drawbacks are highlighted for the nearest prior art:

• The overall number of interfaces to the buses of the two centralized devices is doubled in respect of a solution based on a unique high speed bus.
• A certain degree of circuit emulation is maintained and another TDM bus is used for this purpose. In a fully configurable architecture, this interface has to provide the full ring capacity in order to cover the case of packet traffic only. On the other hand, this interface is completely wasted when the traffic is only of the circuit typology.
• Because of duplication the link set that provides transport of packet based traffic constitutes a source of cross-talk noise for the TDM bus used for circuit transports, and vice versa.

[0009] Furthermore, the splitting of the incoming SONET ring into a TDM bus and a separated packet bus is a solution that might obstacle the future standardization of the interface cards.

OBJECT OF THE INVENTION

[0010] The object of the present invention is that to overcome the limitations of the prior art and to indicate an integrated approach based on a unique high speed serial bus running on the backplane between the interface cards and a dual centralized device capable of switching packets and circuits transport signals inside a network node.

SUMMARY AND ADVANTAGES OF THE INVENTION

[0011] The invention achieves said object by providing a network node, as disclosed in claim 1. According to the invention, the network node includes bidirectional interfaces having first ports for ingress/egress of circuit and/or packet based traffic and second ports connected to a dual switch capable of routing mixed packet and circuit based traffic trough the node and hence also termed Hybrid Switch. The connection between the second ports and the Hybrid Switch is carried out by a SDH bus on the backplane which transports said mixed circuit and packet based traffic. Considering the invention more in details, different topologies of bidirectional interfaces are foreseen.

[0012] In an exemplar case an input interface for incoming mixed packet and circuit based traffic is a card connected both to a packet network (e.g. Ethernet) and to a SDH network. The interface circuitry connected to the SDH network synchronizes the incoming STM-N flux with the apparatus clock, aligns the VCs to a fixed position and forwards to a combiner the VCs containing only circuit based traffic to be combined with the VCs conveying only packet traffic (a single VC-4-n). The interface circuitry connected to the packet network, for each packet entering the node generates, from the combination of the MAC source and destination address, a VLAN-ID identifier which identifies the logical link inside the node and maps it onto a biunique CID identifier which is used by the hybrid switch to forward the packet towards the egress interface card. GFP frames of variable length are built up appositely for transporting packets inside the hybrid switch. Operatively, the packet associated to the VLAN-ID is encapsulated (after having extracted the VLAN-ID) into the payload of a GFP frame, whose Extension header includes the mapped CID identifier. The VLAN-ID has been extracted from the pre-embedded packet because its permanence in the payload would reduce the throughput of the hybrid switch, and hence of the node. The GFP frames so arranged are embedded into VCs directed to the combiner to be combined with the VCs containing circuit based traffic into a common STM-N leaving the interface on the SDH bus on the backplane directed to the Hybrid Switch.

[0013] The Hybrid Switch architecture is constituted by a centralized part and m replicated parts (hereafter called channels) as the m incoming STM-N flows. The centralized part is devoted to timing generation, mixed traffic routing control, and packet scheduling. Channels and centralized parts are illustrated with the following synthetic disclosure of the Hybrid Switch, which includes:

• a front-end circuitry for recovering data incoming from each STM-N flow on the SDH bus on the backplane, separating the two typologies of traffic, and sending bytes of the VCs that carry GFP frames to a set of m m-input-one-output (packet) switches, and bytes of the VCs which have to be switched as such to a set of m m-input-one-output (circuit) switches;
• a packet framer dedicated to the portion VCs within each STM-N incoming signal carrying GFP frames, to perform a GFP frame delineation in order to establish the begin of each GFP frame, hence CID identifier and frame length values retrieval from the GFP header;
• a memory to store routing tables indicating the destination ports mapped both to all foreseen CID identifiers and the incoming circuit based VCs of the m channels;
• a centralized routing controller which accesses first routing tables using the CID identifiers provided by the m packet switches to get address of the mapped output port and generate in correspondence control signals towards the m packet switches for the selection of the addressed output port, and which accesses second routing tables to read the address of the output port of each VC conveying circuit based traffic at the inputs of the m circuit switches and generate in correspondence control signals to the selection of said output ports;
• m time-switches (multiplexer) each receiving bytes from the outputs of both packet and circuit switches of a respective channel, in order to output either the first or the second type of traffic bytes upon a control signal from the centralized control;
• m STM-N formers cascaded to the m time-switches and in their turn followed by m serializers which provide the STM-N flows of the SDH bus on the backplane directed to the output interfaces.

[0014] The output interface, dual in respect of the input one, is connected to the SDH bus on the backplane for receiving the STM-N flow from the Hybrid Switch and operate on the VC pointers in a way to align the VCs to a fixed frame position to be sent so aligned to a splitter. The latter subdivides VCs of the two type of traffic and forwards them along two different paths. The VCs concerning circuit based traffic are forwarded to an STM-N former of the flow on the SDH bus towards the external SDH network. The VCs which conveys GFP frames are instead subjected to the delineation procedure to establish the begin of said frames. Then for each GFP frame packet is de-encapsulated from the payload of the GFP frame, the CID identifier is retrieved from the header and remapped onto the VLAN-ID identifier, and the latter is reinserted into the packet. Packets so obtained leave the node towards the packet network (e.g. Ethernet).

[0015] Respect to the dual switch architecture disclosed in WO200217580-A1, the hybrid solution proposed by the invention has the following advantages:

• the simplification of the backplane structure allows a better utilization of the centralized resources and prevents cross-talk noise, otherwise introduced by the duplicated link set for different traffic typology.
• The overall number of interfaces to the buses of the centralized devices (circuit cross connect and packet switch) is halved.
• The adoption of an unique bus for both signal typologies not only reduces the number of bus interfaces but allows also some other circuitry optimization: frame aligner, memory banks, controller, etc.
• Interface cards with mixed traffic can be served with a single bus instead of two distinguished ones.
• The packet switch emulation to/from circuit cross connect interface is prevented.

[0016] A peculiarity of the present invention is that the interface cards used in the network node see both the packet switch and the circuit transport switch under an unique standard interface, namely the SDH bus. With that, a uniform design of the interfaces is made possible, paving the way for a future standardization.

[0017] Lastly, although SDH is explicitly mentioned to qualify the node which is the subject of the present invention, it shall be understood that other transport technologies having characteristics similar to SDH, such as SONET and OTN, are suitable to be used in the node of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The features of the present invention which are considered to be novel are set forth with particularity in the appended claims. The invention and its advantages may be understood with reference to the following detailed description of an embodiment thereof taken in conjunction with the accompanying drawings given for purely non-limiting explanatory purposes and wherein:

• fig.1, already described, shows the general diagram of a dual switch architecture for mixed packet and circuit transports on SONET/SDH according to the known art;
• fig.2 shows the general architecture of a network node for routing mixed packet and circuit transports according to the present invention;
• fig.3 shows a detail of an Ethernet interface card inside the node of fig.2;
• fig.4 shows the GFP framing structure used to encapsulate packets into a virtual container routed by a hybrid switch device inside the node of fig.2;
• fig.5 shows in detail a GFP frame;
• figures 6 and 7 show two functional schematisations of two types of hybrid interface cards inside the node of fig.2, each combining packet and circuit transports;
• fig.8 shows some logical connections for the GFP frames inside the node of fig.2;
• fig.9 shows the functional architecture of the hybrid switch device inside the node of fig.2.

DETAILED DESCRIPTION OF AN EMBODIMENT OF THE INVENTION

[0019] As a description rule, in the several figures of the drawings like referenced numerals identify like elements. With reference to fig.2, we see a possible network node including a central Hybrid Switch HYSW connected to various types of interface cards through bidirectional SDH buses labelled SDH-I wired on the backplane structure. In a practical embodiment an STM-16 stream is transported on the SDH-I bus whose payload structure depends on the granularity we want to provide within the node using different Virtual Containers: VC12, VC3, VC4. The number of SDH-I buses connecting the card interface to the HYSW depends on the bandwidth the card processes. The virtual containers can also be of the concatenated format, as described in Ref. [ITUG707]; according to the line card they are connected to, they can transport a continuous signal, or a packet based signal, or a combination of the two. As there are some cards which can manage packet traffic and SDH traffic at the same time, the SDH-I bus could carry both packet traffic and SDH traffic at the same time. Therefore each SDH-I bus can carry either SDH traffic or packet traffic or mixed traffic, it depends on the line card. Anyway if SDH-I carries packet traffic, there is only one group (VC-4-Xv) which carries all packet traffic.

[0020] The interface cards are further connected to other networks through external buses. Different typologies of cards are equipped:

• A first type of interface cards is constituted by Ethernet Cards ETH providing any combination of all the standardized Ethernet interface : 10Mbit, 100Mbit, 1Gbit, 10Gbit, in different flavour (electric, optical,..). The Ethernet Cards ETH are connected to an external GbE interface. The SDH-I streams originated/terminated on Ethernet cards carry VCs transporting GFP frames which shall be switched in the packet switched section of the hybrid switch HYSW. The Ethernet traffic is first encapsulated onto GFP frames and then mapped on VC-4-Xv pipes (X is the concatenation multiplier programmable by operator). Lower granularity such as VC12 or VC3 requires only larger processing capabilities. This type of cards will be described with the illustration of fig.3.
• A second type of interface cards is constituted by SDH cards SYC connected to one out of a plurality of possible networks by means of an external SDH interface, labelled SDH-E. The SDH-E bus can be variously implemented either for electrical, optical, or radio signals. These SDH cards can manage different types of traffic depending on the connected networks, for example: pure circuit transport signals, packet over SDH (Ethernet packets, ATM cells, Frame Relay,...), or mixed packets and circuit transport signals. Inasmuch the two types of traffic coexist, we intend these cards are hybrid cards. The SDH-I streams originated/terminated on the hybrid cards carry both VCs transporting GFP frames mapping packets which shall be switched in the packet switched fashion and VCs transporting continuous signals which shall be switched in the circuit switched fashion. This type of cards will be described with the illustration of fig.6.
• A third type of interface cards is constituted by Hybrid Cards HYB providing the SDH-E interface both for Ethernet packets and SDH circuit transport signals. The SDH-I streams originated/terminated on these cards carry both VCs transporting GFP frames mapping packets which shall be switched in the packet switched fashion and VCs transporting continuous signals which shall be switched in the circuit switched fashion. This type of cards will be described with the illustration of fig.7.
• A fourth type of interface cards is constituted by SDH cards SDC connected to the network through the SDH-E bus carrying only circuit transport signals. The SDH-I streams originated/terminated on these cards carry VCs transporting continuous signals which shall be switched in the circuit switched fashion. Their structure doesn't contain any element of novelty or originality in respect to standard card currently developed in any SDH equipment.
• A fifth type of interface cards is constituted by Plesiochronous PDH cards PBC providing plesiochronous interfaces towards the network and carrying only circuit transport signals, see [ITUG703]. Also for the PDH cards there could be hybrid version, of the same type described above, but for simplicity they will not be described in details, the same consideration applying as for the SDH/Eth combination. The SDH-I streams originated/terminated on these cards carry VCs transporting continuous signals which shall be switched in the circuit switched fashion. Their structure doesn't contain any element of novelty or originality in respect to standard card currently developed in any SDH equipment.

[0021] The HYSW hybrid switch can be used with different topologies of optical transport networks, e.g.: self-healing ring, star, mesh, or mixed architectures. The HYSW is protected by redundancy path and APS hitless devices (not shown) and is remotely controlled at the Q interface of a TMN network which exploits control channels built up on some dedicated bytes of the SOH.

[0022] By a rapid glance to the fig.2, it can be immediately realized that a unique serial bus SDH-I on the backplane carrying mixed packet and circuit based traffic is ideally prolonged at the two sides of the hybrid switch HYSW, differently from the cited prior art where duplication is needed.

[0023] Without limitation, the only Ethernet network is considered hereafter as example of packet networks served by the network node; it is understood that all the considerations concerning this network are valid for other packet interface typologies :i.e. MPLS. An Ethernet card ETH is detailed in fig.3. With reference to the figure and [IEEE802.3], the ETH card includes an Ethernet Switch 1 (level-2 switch) connected to the external GbE interface(s) and to a certain number of internal connections GbE-I connected to a block named HySAC, which implements all the functionalities of the cards including interfacing with the SDH-I bus. In the simplified figure the following blocks/devices are not shown: electro-optical transducers, apparatus clock recovery circuits, local ETH ports, MAC terminations, and a RAM external to the HySAC block for buffering function. The HySAC block includes two cascaded blocks 2 and 5 on the direction from the input ports (not shown) to the Hybrid Switch HYSW, and other two cascaded blocks 6 and still 2 on the opposite direction.

[0024] In operations, each GbE traffic interface carries Ethernet frames belonging to one or more ETH logical connections. The Ethernet Switch 1 for each packet entering the node generates, from the combination of the MAC source and destination address (SA, DA), a VLAN-ID identifier which identifies the logical link inside the node; the VLAN-ID will then be mapped onto a biunique identifier which will be placed in the CID field of a GFP frame. VLAN-ID is also named Tag in the description to mark the Ethernet packets as Tagged frames. As already said, the Ethernet packets can be encapsulated in the payload of GFP frames and then mapped into SDH frames. Considering that the GFP frames coming from different ingress ports can be directed towards the same output port, some scheduling/queuing must be implemented to have fairness in accessing the shared bandwidth. Block 2 is a Traffic Manager performing on the incoming Ethernet frames from the GbE-I interface all those known functions (e.g.: policing, queuing, and rate shaping) they are needed to accept, regulate, and bufferize the traffic to be switched inside the node. Block 2 also performs similar functions on the Ethernet frames sent on the GbE-I interface for leaving the node.
Block 5 implements the teaching of [ITUG7041] highlighted in the figures 4 and 5. An Ethernet frame according to [IEEE802.3] is depicted on the top of figure fig.4. This frame includes the VLAN Tags (VLAN_ID) in the payload. The VLAN tags are associated to logical connections through the node; this is obtained associating each VLAN_ID to a GFP_lDx, to say, the CID field included in the Extension Header of the GFP frame represented in fig.5. The implementation of a logical connection is based on the following associations:

• <VLAN_IDa, GFP_lDx> on one interface card,
• <VLAN_IDb, GFP_IDx> on the other interface card.

The VLAN_IDa could be different from VLAN_IDb, but the CID value must be the same and must be the unique in the Hybrid Switch configuration. The VLAN_ID is only valid between Ethernet Switch and HySAC block, it is not carried on the GFP frame. Based on VLAN_ID, block 5 of the HySAC controller identifies the GFP_IDx and writes the corresponding value in the CID field of the Extension header of the GFP frame, then it extracts the VLAN-ID from the Ethernet frame. Block 5 completes the mapping of all the GFP frames onto the portion of the STM-N frame (concatenated VCs) which is then sent on the outgoing SDH-I bus. As depicted in fig.4, the GFP frames are then mapped into the assigned VCs by means of the delineation function realized with the PLI as described in [ITUG7041]. For better clarification, the Ethernet frames are interpreted with the help of the field SFD which indicates the beginning of a new frame. Gaps between successive frames are filled up with the preamble. The GFP frames are interpreted with the help of the core header field PLI+ associated to the correction code. The PLI contains information on the frame length. Gaps between successive frames are filled up with core header of frames with null length. Accordingly the receiver checks for a frame constituted by a sole core header and once it is detected the remaining frames are also correctly detected consequently. Mapping between the output ports and CID values is configurable by software.
The GFP frame is shown in fig.5, where the various acronyms used to indicate the various fields have the following meaning: PLI (Payload Length Identifier), cHEC (Core Header Error Control), PTI (Payload Type Identifier), PFI (Payload FCS Indicator), EXI (Extension Header Identifier), UPI (User Payload Identifier), tHEC (Type Header Error Control), CID (Channel ID), eHEC (Extension Header Error Control), pFCS (Payload Frame Check Sequence). Turning back to fig.3, block 6 performs the opposite operations than block 5. More precisely, it receives the SDH frames from the incoming SDH-I bus, extracts the VC-4 containers, de-maps the GFP frames by delineation and for each GFP frame: reads the CID field from the extension header, retrieves the VLAN-ID associated to the CID value, by re-mapping, and inserts the VLAN-ID into the payload of the de-encapsulated GFP frame obtaining an Ethernet frame to be completed with frame delimiter and preamble. The incomplete Ethernet frames are forwarded again to block 2 to perform the aforementioned traffic management functions for a correct subdivision of packets received by an unique source to many GbE-I links.

[0025] With reference to fig.6, the hybrid card SYC which corresponds to the second type of interface cards is diagrammatically represented. The SYC card represents the case where the traffic interface is SDH and the traffic carried on the SDH-E bus consists either of Virtual Containers which have to be transmitted from the ingress to the egress of the card in this format, or Virtual Containers transporting GFP frames which on their turn contain packets (i.e. Ethernet frames). The hybrid card SYC includes a PP (Pointer Processing) Framer block 10, two splitters/combiners 11, 15 and other blocks similar to the ones of fig.3. To simplify the drawing block 2 is split in two parts at the two sides of the Ethernet Switch 1. The splitters/combiners 11 and 15 are bidirectional three-port devices. The PP Framer 10 is connected to the SDH-E bus and to a first port of the splitter/combiner 11. The SDH-I bus is connected to a first port of the splitter/combiner 15, while a second bidirectional port of both splitters/combiners 11 and 15 are connected together. The third port of the splitter/combiner 11 is connected to the cascade of blocks 6a, 2, 1, 2 again, 5, and the third port of the splitter/combiner 15. The third port of the splitter/combiner 15 is also connected to the cascade of blocks 6, 2, 1, 2 again, 5a, and the third port of the splitter/combiner 11. Blocks 6a and 5a differ form the corresponding blocks 6 and 5 of fig.3 by the fact that the only functions indicated with 3. and 4. are performed.

[0026] In operation, the SDH-E bus is directed to the PP Framer block 10 which intercepts the VCx pointer in the received SDH frame and repositions the VC in a new frame, with apparatus clock and the VCx pointer in a known and fixed position of the frame (VCx = 0). The splitter 11 conveys the VCs including signals which have to be switched in the circuit fashion directly towards the combiner 15, where they will be added to the VCs coming from the packet processing and inserted in the SDH-I signal with the pointers in their former positions. The others VCs containing packets, nominally transporting GFP frames on the SDH network, are diverted towards the block 6 where the original Ethernet frames are extracted from the GFP frames and addressed to the Traffic Manager 2, which regulates the access to the Ethernet Switch 1 on the internal connection GbE-I. Packets at the output of the Ethernet Switch 1 on the GbE-I connection are directed again to the Traffic Manager 2 which also regulates the access on the SDH-I bus. Block 2 forwards the received packets to block 5 to be encapsulated into GFP frames and sent to the third port of the combiner 15. In the reverse direction from bus SDH-I to SDH-E reverse operations are carried out by the splitter 15 and the combiner 11.

[0027] With reference to fig.7, the hybrid card HYB corresponding to the third type of interface cards is diagrammatically represented. The HYB cards represent the case where Ethernet interfaces and SDH interfaces coexist on the same card. In this case, the SDH-E bus carries only traffic which has to be handled in the circuit format, and the GbE interface carries packets. The hybrid card HYB includes a PP Framer block 10, a splitter/combiner 15, an ETH PHY card 18, and other blocks similar to the ones of fig.3. The splitter/combiner 15 is a bidirectional three-port device. The PP Framer 10 is connected to the SDH-E bus and to a first port of the splitter/combiner 15. The SDH-I bus is connected to a second port of the splitter/combiner 15, while the third port is connected to the cascade of blocks 6, 2, the Ethernet Switch 1, and the ETH PHY card connected at the GbE interface. In its turn, the ETH PHY card 18 is connected to the cascade of the Ethernet Switch 1, blocks 2, 5, and the third port of the splitter/combiner 15.

[0028] In operation, the circuit transport signals embedded in Virtual Containers on the SDH-E bus which have to be transmitted from the ingress to the egress of the card in this format is directed to the PP Framer 10, to be arranged as already said and forwarded to the combiner 15 where they are added to the VCs coming from the packet processing and inserted in the SDH-I signal. In the reverse direction, from bus SDH-I to SDH-E, the splitter 15 conveys the VCs relevant to signals switched in the circuit fashion directly towards the PP Framer 10, which re-establishes the exact pointer locations and inserted them in the SDH-E signal. The others VCs containing packets nominally transported in GFP frames are diverted towards the block 6, where the original Ethernet frames are extracted from the GFP frames and addressed to the Traffic Manager 2, which regulates the access to the Ethernet Switch 1 on the GbE-I connections with the internal GbE-I interface. Packets at the output of the Ethernet Switch 1 on the GbE-I connections are directed to the ETH PHY block 18 to be forwarded on the GbE interface.

[0029] Packets incoming at the GbE interface enter the ETH PHY block 18 which carries out the typical physical layer functions and forwards them on the GbE-I connection to the Ethernet Switch 1. Packets at the output of the Ethernet Switch 1 on GbE-I connection are directed to the Traffic Manager 2 which regulates the access to the SDH-I bus. Block 2 forwards the packets to block 5 which encapsulates them into GFP frames and sent the corresponding VCs to the third port of the combiner 15 to be added to the VCs coming from the SDH-E interface.

[0030] The description of the various typologies of interface cards is completed and the base for understanding the operation of the central Hybrid Switch HYSW is posed. This central switch is a special cross-connect with the twofold capability of routing SDH virtual containers parallelly to GFP frames and hence the Ethernet packets transported in the GFP payload. As show in fig.2, such a hybrid cross-connect accepts STM-N flows at the ingresses and outputs STM-N flows at the egresses. An immediate visual representation of the packet routing through the Hybrid Switch is given in fig.8, where some logical connections between ETH ports (physical or logical) placed at the two sides of the Hybrid Switch HYSW are drawn. The connections between ETH logical ports are set up on operator's command by configuration setting. From the Switch point of view, the ETH logical ports are managed as typical ETH physical ports. The logical connection setting is similar to a physical (RJ45) connection setting (with different bandwidth of course). More particularly, a logical connection LCN1 inside the node is highlighted between an ETH logical port Pa of the uppermost ETH1 left card and an ETH logical port Pb of the second ranked ETH2 right card. The ETH packets at ingress port Pe of the ETH1 card are identified by the MAC address (SA, DA) combination and switched accordingly within the Ethernet switch from where they emerge with a VLAN-ID which identifies the internal logical path (LCN1 from Pa to Pb) to be traversed in order to reach the egress port. Before crossing the hybrid switch, the tagged frame is encapsulated into a GFP frame where the CID field of the extension header contains the value which identifies the LCN1 path within the hybrid switch. Operatively, the mapping for routing Pa → Pb is performed in two steps: a first step VLAN-ID → CID is carried out by the ETH1 card using a first table; a second mapping step CID → Pb is carried out by the Hybrid Switch HYSW using a second table (a single table might include the two mapping).. The switching scenario is completed by two SDH cards SDC/SYC at the two sides of the Hybrid Switch for switching circuit transport signals embedded on the SDH-I bus. In operation, for each received GFP frame, the Hybrid Switch carries out the delineation procedure described in [ITUG7041] and identifies the output port reading the CID field, then switches the GFP frame to the configured output port rendering physical the logical connection.

[0031] The architecture of the Hybrid Switch is represented in fig.9 in a general diagrammatical form and for a direction only of the SDH-I bus (the architecture for the other direction is identical). With reference to fig.9, the Hybrid Switch HYSW accepts on the SDH-I bus a number m of STM-16 flows at the inputs called Data_IN_1, ....., Data_IN_m, each carrying mixed packet and circuit based traffic in the most general case. The HYSW outputs on the SDH-I bus a number m of STM-16 flows called Data_OUT_1, ....., Data_OUT_m, each carrying mixed packet and circuit based traffic in the most general case. The HYSW switch includes m sub-block channels dedicated to the m incoming/outgoing STM-16 flows, plus a common synchronization circuit 29 and a local processor block 30. Circuit 29 receives a reference clock CK_Ref at 2,488.32 Mbit/s and a MF frame reference pulse at the repetition rate of 125 µs and in its turn generates the timing signals needed to all internal blocks. Each sub-block channel 1,...,m is followed by two cascaded blocks 27-1 and 28-1,.......,27m and 28m corresponding to a STM-16 FORMER and a SERIALIZER connected to an output buffer of Data_OUT_1,..., Data_OUT_m signal on the serial SDH-I bus. The processing block 30 includes a processor 31 having a bidirectional bus connected to a memory 32, a Routing controller 33, and a Packet Scheduler 34 (for drawing simplification the connections of block 30 with the main blocks of HYSW are not shown). For brevity, the only Channel 1 sub-block is represented in detail, the other sub-block channels are identical. Channel 1 includes a front-end block 21 which receives an STM-16 flow Data_IN_1 from an input buffer connected to the SDH-I bus, a timing signal from block 29, and the apparatus clock CK_Ref, generating 2-bytes words sent on an internal bus 21 b directed to a packet switch PSW and a circuit switch CSW. The PSW switch includes a header analyser block 22 connected at the input to the internal bus 21 b and at its output to a first input of m multiplexers 23 in parallel. Block 22 is further connected to the Packet Scheduler 34. The outputs of the m multiplexers 23 are directed to respective buffers 24, in their turn connected to the inputs of a terminal multiplexer 25, whose output is connected to the STM-16 Former 27. The remaining m-1 channels are structured as channel 1, the last m^th channel includes the following blocks: 21 m, 22m, 23m, 24m, 25m, and 26m in correspondence of the equivalent ones of channel 1. Each m-input multiplexer 23 has the remaining m-1 inputs respectively connected (in parallel to the same inputs of the other nm multiplexers with the same label) to the m-1 blocks equivalent to block 22 inside the other m-1 channels. Similarly, the CSW switch includes an m-input multiplexer whose other m-1 inputs are respectively connected to the m-1 blocks equivalent to block 22 inside the other m-1 channels, and an output connected to an input of the terminal multiplexer 25. The set of multiplexer 23,....,23m see packets entering the m STM-16 channels of the whole node. Similarly, the set of multiplexer 26,....,26m see circuit transport signals entering the m STM-16 channels of the whole node.

[0032] In operation, block 21 synchronizes the incoming STM-16 flow and recovers the incoming serial Data_IN_1, disassembles the VCs, aligns them to a fixed position (begin of the frame) to make the switching easier. The aligned VCx is S/P converted in octets (bytes) and the octets of circuit based and packet based VCx are sent on the internal bus 21 b (16 wires) towards the respective switch PSW or CSW. At word time the multiplexer 26 is controlled to output one out of m words simultaneously present at the m inputs according to the VCs routing plane (the other inputs are not lost because selected by other multiplexers).

[0033] As the packet switching is concerned, the description concentrates on the only VC-4 format (140 Mbit/s), but other VC format can be used is used; a prefixed number n of VC-4 containers are concatenated to increase the switched bandwidth in respect of the single VC-4 so as to match the bandwidth of the GbE interface. Block 22 receives the packet bytes of the GFP frames from the internal bus 21b and executes the Delineation procedure, as already said. From delineation, the starting point of each GFP frame is determined. Block 22 retrieves the contents of PLI and CID header fields from each GFP frame and sends the read values to the processing block 30. The bytes of delimited frames are sent to a same input of the m multiplexers 23 according to the concatenation procedure. At word time the multiplexer 23 is controlled to output one out of m words simultaneously present at the m x m inputs according to the GFP frame routing plane

[0034] At word time the multiplexer 25 is controlled to output either packet or circuit based bytes according to the mixed structure of the STM-16 output flow. With that, multiplexer 25 behaves as a time switch between circuits and packets transport signals. The STM-16 FORMER block 27 receives the sequential bytes at the output of multiplexer 25 and reconstructs in an internal buffer the sequential order assigned to the VCs into the STM-16 output frame. Each VC is completed with the overhead and the pointer which indicates its position on the frame. The reconstructed frame is transferred to the serializer block 28 which reads it at bit rate, obtaining the STM-16 flow of Channel 1 on the SDH-I bus at the output of the hybrid switch HYSW. The processing block 30 performs the routing function both for packets and circuit based signals. The two set of multiplexers 23,...,23m and 26,...,26m, and the set of terminal multiplexers 25,....,25m constitute a T-S-T hybrid switching matrix completely non-blocking controlled to switch packets and circuit transport data mixed together. In case of congestion at the output interfaces, the congestion status is communicated to the processing block 30 which performs the scheduling of the GFP frames stored in the m buffers internal to PSW according to known scheduling algorithms. The memory 32 stores the needed routing tables that can be updated by remote control. As the circuit based transport is concerned, the incoming VCs are switched as such. Without limitation, three types of Containers are considered by the switch HYSW, namely: VC-4 (140 Mbit/s), VC-3 (34/45 Mbit/s), and VC-12 (2 Mbit/s). In the case of packet switching, instead, the processing block 30 receives the PLI and CID values of each GFP frame and uses the CID value to address the output port in the stored map, and the PLI value to set the duration of the relevant switch. The memory 32 also stores tables including the sequential structure of each STM-16 frame at the output of HYSW. Basing on the stored tables, the routing controller 33 controls each set of multiplexers 23, 26, and 25 at byte time. From the knowledge of the GFP frame length for packet switch and the type of VC for circuit based switch, the routing controller 33 holds the respective control signals unchanged for all relevant duration.

VARIANTS

[0035] A precise obligation doesn't exist at all to the use of STM-16 flows at the inputs and the outputs of the Hybrid Switch, for example, STM-4 or STM-64 are valid choices. Also the architecture of the Hybrid Switch is not unique and some changes may be introduced by those skilled in the art without departing from the scope of the invention. Besides, a certain degree of simplification is possible in the interface cards. For example, a solution more integrated than the intermediate passage from the VLAN-ID, could be obtained mapping the internal connection associated to the couple of MAC addresses (SA, SD) onto the CID field of the GFP extension header directly. The embodiment with the intermediate VLAN-ID is only tied to the use of commercial Ethernet Switch inside the interface cards.

Claims

1. Network node including bidirectional interfaces (ETH, HYB, SDC, SYC, PBC) having first ports (GbE, SDH-E) for ingress/egress of circuit and/or packet based traffic and second ports (Pa, Pb) connected to a dual switch (HYSW) arranged for routing said mixed circuit and packet based traffic trough the node, characterized in that said second ports (Pa, Pb) are connected to said dual switch (HYSW) by an internal SDH bus (SDH-I) on the backplane, or by other TDM buses SDH compliant, transporting said mixed circuit and packet based traffic.

2. The network node of the claim 1, characterized in that said interfaces (ETH, HYB, SYC) include:

- means (1) for generating for each packet entering first ports (GbE, SDH-E) an identifier, called hereafter VLAN-ID, of logical connections valid inside the node except inside said dual switch (HYSW) from the combination of the MAC source and destination address of said packets;

- means (5) for univocally associating each VLAN-ID identifier to an identifier, called hereafter CID, which is used by the dual switch (HYSW) to forward packets towards output ports (Pa, Pb) mapped to the CID values;

- means (5) to extract said VLAN-ID identifiers from said packets;

- means (5) for encapsulating said packets into the payload of as many GFP frames and introducing said CID identifier in the header;

- means (5) for embedding said GFP frames into virtual containers of an SDH flow (SDH-I) going out of second ports (Pa, Pb).

3. The network node of the claim from 2, characterized in that said interfaces (ETH, HYB, SYC) include:

- means (6) for delineating the begin of the GFP frames embedded in virtual containers transported by a SDH flow (SDH-I) entering said second ports (Pa, Pb);

- means (6) for de-encapsulating said packets from the payload of the GFP frames;

- means (6) for retrieving said CID identifiers from the header of the GFP frames;

- means (6) for remapping said CID identifiers onto said VLAN-ID identifiers;

- means (6) for re-inserting said VLAN-ID identifiers into said packets and forwarding the de-capsulated packets towards said first port (GbE, SDH-E).

4. The network node of the claim 3, characterized in that said interfaces (HYB) include:

- an additional first port connected to an SDH network through a SDH bus (SDH-E) conveying STM-N flows including virtual containers for only circuit based traffic;

- bidirectional means (15) for:

- combining virtual containers conveying only circuit based traffic with said virtual containers having embedded GFP frames into a STM-N flow for mixed traffic (SDH-I) going out from said second port (Pa, Pb); and

- splitting virtual containers conveyed by a STM-N flow for mixed traffic (SDH-I) entering said second port (Pa, Pb) into virtual containers of the two types of traffic separately processed and forwarded towards the compliant type of first port.

5. The network node of the claim 3, characterized in that said first port of the interfaces (SYC) is connected to a SDH bus conveying STM-N flows for mixed circuit and packet based traffic, and the interfaces (SYC) including first bidirectional splitting/combining means (11) connected at the first port and second bidirectional splitting/combining means (15) connected at the second port for splitting/combining virtual containers conveying the two types of traffic so as to forward circuit based virtual containers between the two ports in a transparent way.

6. The network node of any preceding claims, characterized in that said dual switch (HYSW) includes:

- means (21) for recovering data incoming from a number m of STM-N flows (Data_IN_1,.....,Data_IN_m), also termed channels, on the SDH bus on the backplane (SDH-I);

- means (21) operating upon each received channel for separating virtual containers transporting packets from virtual containers transporting circuit based traffic to be switched as such;

- a set of m m-input-one-output packet switches (PSW) receiving packet bytes from said separating means (21);

- a set of m m-input-one-output circuit switches (CSW) receiving bytes of virtual containers which transport circuit based traffic from said separating means (21);

- memory means (MEM) to store routing tables indicating the destination ports mapped both to all foreseen CID identifiers and said virtual containers to be switched as such;

- control means (30) for accessing first routing tables using said CID identifiers to get addresses of respective mapped output ports and generate in correspondence control signals towards the m packet switches (PSW) for the selection of the addressed output ports; and for accessing second routing tables to read the address of the output port of the m circuit switches (CSW) and generate in correspondence control signals to the selection of the addressed output ports.

7. The network node of the claim 6, characterized in that said dual switch (HYSW) includes: means (22) inside each packet switch (PSW) to perform GFP frame delineation in order to establish the begin of each GFP frame including a packet, and means (22) for retrieving the CID identifier and the frame length values from the GFP header in order to instruct said control means (33).

8. The network node of the claim 6 or 7, characterized in that said dual switch (HYSW) includes time-switching means (25) cascaded to said m packet and circuit switches (PSW, CSW), in order to output either the first or the second type of traffic bytes upon a control signal from the control means (33).

9. The network node of the claim 8, characterized in that said dual switch (HYSW) includes m STM-N formers (27-1,...27-m) cascaded to the m time-switching (25) and m serializers (28-1,...28-m) cascaded to the m STM-N formers for building up m STM-N flows (Data_OUT_1, .......,Data_OUT_m) of the SDH bus on the backplane (SDH-I) directed to the output interfaces.

Drawing