PROGRAMMABLE LOGIC DEVICE AND ITS DESIGNING METHOD

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EP 1 727 196 A8

(12)	CORRECTED EUROPEAN PATENT APPLICATION
	published in accordance with Art. 158(3) EPC

(15)	Correction information:
	Corrected version no 1 (W1 A1)

(48)	Corrigendum issued on:
	03.01.2007 Bulletin 2007/01

(43)	Date of publication:
	29.11.2006 Bulletin 2006/48

(21)	Application number: 05720492.7

(22)	Date of filing: 10.03.2005

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International Patent Classification (IPC):

H01L 21/82^(2006.01)
H01L 27/088^(2006.01)

H01L 21/8234^(2006.01)

(86)	International application number:
	PCT/JP2005/004221

(87)	International publication number:
	WO 2005/091357 (29.09.2005 Gazette 2005/39)

(84)	Designated Contracting States:
	DE FR GB NL

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Priority:

18.03.2004 JP 2004078826

(71)	Applicant: Matsushita Electric Industrial Co., Ltd.
	Kadoma-shi Osaka 571-8501 (JP)

(72)	Inventors:
	MORI, Atsuhiro Mat.Elec.Ind. Co., Ltd. I.P.R.O. Chuo-ku, Osaka-shi, Osaka 540-6319 (JP) MARUI, Shinichi Mat.Elec.Ind.Co.,Ltd.I.P.R.O. Chuo-ku, Osaka-shi, Osaka 540-6319 (JP) OKAMOTO, Minoru Mat.Elec.Ind.Co.,Ltd. I.P.R.O Chuo-ku, Osaka-shi, Osaka 540-6319 (JP)

(74)	Representative: Grünecker, Kinkeldey, Stockmair & Schwanhäusser Anwaltssozietät
	Maximilianstraße 58 D-80538 München D-80538 München (DE)

(54)	PROGRAMMABLE LOGIC DEVICE AND ITS DESIGNING METHOD

(57) The power consumption and area of a programmable logic device formed from programmable logical elements can be reduced.
In a programmable logic device 101 formed from programmable logical elements, there are provided first logical elements 102 and second logical elements 104 having the same logic as the first logical elements 102 but having an upper limit of operating speed designed to be lower than that of the first logical elements 102.