METHOD AND APPARATUS FOR DESIGNING INTEGRATED CIRCUIT LAYOUTS - Patent 1759321

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EP 1 759 321 A2

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(88)	Date of publication A3:
	15.12.2005

(43)	Date of publication:
	07.03.2007 Bulletin 2007/10

(21)	Application number: 05740549.0

(22)	Date of filing: 29.04.2005

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International Patent Classification (IPC):

G06F 17/50^(2006.01)

(86)	International application number:
	PCT/US2005/015024

(87)	International publication number:
	WO 2005/109257 (17.11.2005 Gazette 2005/46)

(84)	Designated Contracting States:
	AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU MC NL PL PT RO SE SI SK TR

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Priority:

01.05.2004 US 836581
01.05.2004 US 836582

(71)	Applicant: Cadence Design Systems, Inc.
	San Jose, CA 95134 (US)

(72)	Inventors:
	SCHEFFER, Louis, K. Campbell, CA 95008 (US) TEIG, Steven Menlo Park, CA 94025 (US)

(74)	Representative: Hess, Peter K. G.
	Patent- und Rechtsanwälte Bardehle . Pagenberg . Dost . Altenburg . Geissler Galileiplatz 1 81679 München 81679 München (DE)

(54)	METHOD AND APPARATUS FOR DESIGNING INTEGRATED CIRCUIT LAYOUTS