(19)
(11) EP 1 806 652 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
05.11.2008 Bulletin 2008/45

(43) Date of publication A2:
11.07.2007 Bulletin 2007/28

(21) Application number: 06251769.3

(22) Date of filing: 30.03.2006
(51) International Patent Classification (IPC): 
G06F 7/499(2006.01)
G06F 7/483(2006.01)
G06F 7/74(2006.01)
 G06F 5/01(2006.01)
G06F 7/544(2006.01)
(84) Designated Contracting States:
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC NL PL PT RO SE SI SK TR
Designated Extension States:
AL BA HR MK YU

(30) Priority: 02.12.2005 JP 2005349804

(71) Applicant: Fujitsu Ltd.
Kawasaki-shi, Kanagawa 211-8588 (JP)

(72) Inventor:
  • Tajiri, Kunihiko, c/o Fujitsu Limited
    Kawasaki-shi Kanagawa 211-8588 (JP)

(74) Representative: Stebbing, Timothy Charles et al
Haseltine Lake Lincoln House 300 High Holborn
London WC1V 7JH
London WC1V 7JH (GB)

   


(54) Normalization and rounding of an arithmetic operation result


(57) An arithmetic operation unit, which generates shift information representing whether or not an arithmetic operation result has been shifted when the arithmetic operation result is normalized, has an arithmetic logical unit for outputting the arithmetic operation result, a normalizer (30) having a plurality of shifters for normalizing the arithmetic operation result, a shift amount calculator for calculating a plurality of shift amounts for the plural shifters, and a predictor (51) for generating interim information that is a result of prediction of whether or not the arithmetic operation result is to be shifted when the arithmetic operation result is normalized, by using the plural shift amounts, and a generator (52) for generating the shift information by using the interim information. The cycle time required to generate the interim information (a sticky bit) is shortened to efficiently generate the sticky bit, and the hardware resources for generating the sticky bit are reduced.







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