(19)
(11) EP 1 818 974 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
20.05.2009 Bulletin 2009/21

(43) Date of publication A2:
15.08.2007 Bulletin 2007/33

(21) Application number: 07101968.1

(22) Date of filing: 08.02.2007
(51) International Patent Classification (IPC): 
H01L 27/115(2006.01)
H01L 21/336(2006.01)
 H01L 21/8247(2006.01)
H01L 29/788(2006.01)
(84) Designated Contracting States:
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC NL PL PT RO SE SI SK TR
Designated Extension States:
AL BA HR MK RS

(30) Priority: 10.02.2006 US 351520

(71) Applicant: Micrel, Inc.
San Jose, CA 95131 (US)

(72) Inventor:
  • MOORE, Paul M
    Foster City, CA 94404 (US)

(74) Representative: Brookes Batchellor LLP 
102-108 Clerkenwell Road
London EC1M 5SA
London EC1M 5SA (GB)

   


(54) Non-volatile memory cells and methods for fabricating the same


(57) A non-volatile memory cell (200) and method of fabrication are provided. The non-volatile memory cell (200) includes a substrate (202) of a first conductivity type, a first dopant region (204) of a second conductivity type in the substrate (202), a second dopant region (206) of the first conductivity type in the first dopant region (204), a first isolation region (214B) overlaying a portion of the substrate (202), the first dopant region (204), and the second dopant region (206), a second isolation region (214A) overlaying another portion of the substrate (202), the first dopant region (204), and the second dopant region (206), a contact region (208) of the first conductivity type in the second dopant region (206), the contact region (208) extending between the first isolation region (214B) and the second isolation region (214A) and being more heavily doped than the second dopant region (206), a gate dielectric (212A) atop the first isolation region (214B) and a portion of the contact region (208), and a gate conductor (210A) atop the gate dielectric (212A).







Search report