METHOD OF MAKING A PLANAR DOUBLE-GATED TRANSISTOR - Patent 1846945

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EP 1 846 945 A2

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(88)	Date of publication A3:
	14.06.2007

(43)	Date of publication:
	24.10.2007 Bulletin 2007/43

(21)	Application number: 05854001.4

(22)	Date of filing: 14.12.2005

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International Patent Classification (IPC):

H01L 21/00^(2006.01)

(86)	International application number:
	PCT/US2005/045202

(87)	International publication number:
	WO 2006/083401 (10.08.2006 Gazette 2006/32)

(84)	Designated Contracting States:
	AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC NL PL PT RO SE SI SK TR
	Designated Extension States:
	AL BA HR MK YU

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Priority:

31.01.2005 US 47448

(71)	Applicant: Freescale Semiconductor, Inc.
	Austin, Texas 78735 (US)

(72)	Inventor:
	ORLOWSKI, Marius K. Austin, Texas 78739 (US)

(74)	Representative: Wharmby, Martin Angus et al
	Freescale Semiconductor Inc. c/o Impetus IP Limited Grove House Chineham Basingstoke, Hampshire RG24 8AG Basingstoke, Hampshire RG24 8AG (GB)

(54)	METHOD OF MAKING A PLANAR DOUBLE-GATED TRANSISTOR