The present invention relates to transceivers, and more particularly to controlling a transceiver to improve performance of a radio.

Transceivers are used in many communication systems including wireless devices, for example. A transceiver can be used for both transmit and receive operations in a device. Often, a transceiver is coupled between a baseband processor and an antenna and related circuitry of the system. In the receive direction, incoming radio frequency (RF) signals are received by the transceiver, which downconverts them to a lower frequency for processing by the baseband processor. In the transmit direction, incoming baseband data is provided to the transceiver, which processes the data and upconverts it to a higher frequency, e.g., a RF frequency. The upconverted RF signals are then passed to a power amplifier (PA) for amplification and transmission via an antenna.

Thus, the transceiver acts as an interface between digital and RF domains. Among the various tasks performed by a transceiver are downconversion and upconversion, modulation and demodulation, and other related tasks. Oftentimes, a transceiver is controlled by a baseband processor to which it is coupled.

In turn, the transceiver is coupled to a power amplifier, which generates appropriately conditioned, RF signals for transmission via an antenna. In the transmit direction, the transceiver provides RF signals to the power amplifier, which amplifiers the signals based on gain and ramp information for a given modulation type. Different wireless communication protocols implement different modulation schemes. For example, a Global System for Mobile communication (GSM) system can implement various modulation schemes, including a gaussian minimum shift keying (GMSK) modulation scheme for voice data. Furthermore, extensions to GSM, such as Enhanced Data rates for GSM Evolution (EDGE) use other modulation schemes, such as an 8 phase shift keying (8-PSK) modulation scheme.
US Patent 2005/0054308 describes a variable gain power amplifier that implements both GMSK and 8PSK modulation schemes.

While many different power amplifiers exist, most PAs receive various control signals, e.g., from the baseband processor, along with the data signal, e.g. from the transceiver. These control signals include an enable signal and the like. Also, a PA receives a supply voltage and/or one or more bias voltages. Some PAs in certain wireless protocols implement a linear architecture. These PAs can operate in dual modes of operation, namely a saturated mode and a linear mode. GMSK schemes typically transmit in a saturated mode in which transmitted data is output from the PA with a constant amplitude as measured by power versus time during the useful part of the burst. In contrast, 8-PSK modulation implements a linear mode in which a time-varying amplitude is output from the PA as measured by power versus time during the useful part of the burst.

In the 3GPP specification, a mixed mode of operation is set forth. This mixed mode of operation, otherwise known as a dual transfer mode, switches modulation schemes during inter-slot periods. Specifically, one implementation calls for transmission in alternating GMSK-8-PSK schemes in different slots. Control between the modulation schemes switches in the inter-slot period. Accordingly, the 3GPP specification requires that a switching spectrum be met in which power transients at the output of the power amplifier are reduced or eliminated in the inter-slot period to provide for proper operation.
WO 2004/021659 describes a transmitter which introduces dips in the guard time interval between adjacent time slots or bursts to avoid interference.
WO 2003/036896 discloses a transmitter that fully ramps a communication signal down and then back inside a guard period so that signal glitches only occur when the signal is ramped down and so can be made negligible.

As more service providers enable mixed mode operations, wireless systems need to improve their switching spectrum during the inter-slot period, particularly for mixed mode operations.

A first aspect of the present invention provides a method comprising transmitting radio frequency (RF) data of a first slot via an RF signal path from a transceiver to a power amplifier, squelching the RF signal path during a predetermined portion of an inter-slot period, and transmitting RF data of a second slot via the RF signal path from the transceiver to the power amplifier, wherein the squelching the RF signal path comprises squelching an RF output to a zero value by opening a switch on the RF signal path from the transceiver to the power amplifier. In addition to squelching the RF signal path, a ramp output of the transceiver may further be disabled during the predetermined portion.

Another aspect of the present invention provides an apparatus comprising a transceiver to receive baseband data and to provide radio frequency (RF) data to a power amplifier, wherein the transceiver is controllable to squelch an RF output during an inter-slot period between a first slot and a second slot of a multi-slot communication; wherein the transceiver comprises a switch coupled to a RF output line from the transceiver, and the apparatus comprises a controller to control the transceiver to squelch the RF output to a zero value by opening the switch. The apparatus may further include a baseband processor coupled to the transceiver that sends control information to the transceiver to disable a ramp output of the transceiver, and the baseband processor may further include a controller that controls squelching of the RF output.

Yet another aspect of the present invention provides a system comprising a transceiver to receive baseband data and control information and to provide radio frequency (RF) data to a power amplifier, wherein the transceiver is to squelch an RF output during an inter-slot period between a first slot and a second slot of a mixed mode multi-slot communication; a baseband processor to provide the baseband data and the control information; and a power amplifier coupled to the transceiver to receive the RF output; wherein the transceiver comprises a switch coupled to a RF output line from the transceiver, and the baseband processor is operable to squelch the RF output to a zero value by opening the switch.

FIG. 1 is a block diagram of a portion of a wireless system in accordance with one embodiment of the present invention.

FIG. 2 is a timing diagram of a multi-slot transition in accordance with one embodiment of the present invention.

FIG. 3 is a timing diagram of a multi-slot transition in accordance with another embodiment of the present invention.

FIG. 4 is block diagram of a transceiver in accordance with one embodiment of the present invention.

FIG. 5 is a block diagram of a system in accordance with one embodiment of the present invention.

In various embodiments, a transceiver may be controlled to remove or squelch its RF output during certain portions of a communication cycle to avoid power transients at an output of a power amplifier to which the transceiver is coupled. Furthermore, in some implementations ramp control for the power amplifier may also be squelched during these portions of the communication cycle. Further, the ramp control may switch between baseband control for certain modulation schemes and transceiver control for other modulation schemes. While the following discussion refers to a mixed mode of operation, and more particularly a mixed mode of operation using GMSK and 8-PSK modulation schemes, it is to be understood that the scope of the present invention is not so limited.

Referring now to FIG. 1, shown is a block diagram of a portion of a wireless system in accordance with one embodiment of the present invention. As shown in FIG. 1, system 10 includes a baseband processor 20. In various embodiments, baseband processor 20 may be responsible for processing data of a wireless communication, e.g., a voice and/or data communication. Furthermore, baseband processor 20 may provide control signals to other system components, such as a transceiver 30 to which it is coupled.

Baseband processor 20 provides wireless data to transceiver 30, e.g., in the form of I and Q signals. Furthermore, baseband processor 20 provides control signals to transceiver 30. In one embodiment, such control information may be sent via a serial control interface (SCI), although the scope of the present invention is not so limited. As further shown in FIG. 1, baseband processor 20 further provides a ramp signal to transceiver 30. In different implementations, a ramp digital-to-analog converter (DAC) within baseband processor 20 may generate the ramp signal and provide it to transceiver 30. The ramp signal may be used to ramp the transceiver up before a transmit burst and ramp it down after a transmit burst to improve signal performance, e.g., to prevent out of band spurious noise. Use of the ramp signal will be discussed further below.

Upon receipt of wireless data, transceiver 30 may perform various processing including, for example, frequency conversion and modulation according to a desired modulation scheme. Data may be transmitted out of transceiver 30 as RF output data (RFO), and in turn may be input to PA 40 as a power input signal (P_in). Transceiver 30 is further coupled to provide a ramp output signal (RAMPOUT) which is input to PA 40 as V_RAMP. The amplified RF signals are then transmitted from PA 40 as a power output signal (PA_out) and are output from an antenna 50.

To reduce transients at an output of PA 40, transceiver 30 may be controlled to squelch its RF output at a predetermined time within the inter-slot period. In such manner, performance of system 10 may be improved and the spectral requirements for switching transients in a mixed mode of operation may be met. Still further, at this predetermined time of the inter-slot period, the ramp output from transceiver 30 may also be controlled to a zero value.

In different implementations, various manners of controlling the transceiver to enable this inter-slot silent period can be effected. In one implementation, control information from a baseband processor may be received in the inter-slot period and be used to trigger an RF squelch of the RF output signal and furthermore to clamp the ramp output signal to a ground or other reference level.

Referring now to FIG. 2, shown is a timing diagram of a multi-slot transition in accordance with one embodiment of the present invention. As shown in FIG. 2, a first slot (Slot X) is to be transmitted using 8-PSK modulation, while a second slot (Slot X+1) is to be transmitted using GMSK modulation. As shown in FIG. 2, control information corresponding to the contents of various registers is transmitted from a baseband processor and is received at a serial port of a transceiver. As shown in FIG. 2, the contents of various control registers may be transmitted to the transceiver via the serial port prior to the transmission time for the first slot. In the embodiment of FIG. 2, these control registers are enumerated as registers 21-24h. The contents of these registers may include various control information for data transmission. Such control information may include, e.g., a band indicator, channel numbers, automatic frequency control (AFC) fine tuning data, transmitter set up information, mode select data, among other such information. Of course, in other embodiments additional or different control information may be transmitted.

Still referring to FIG. 2, note that a power mask (PDN) is active for the entire multi-slot period. Note also that an incoming ramp signal (RAMPIN) from the baseband processor ramps up prior to the first slot, ramps down during the inter-slot period and further ramps up again prior to the second slot. However, in various embodiments the ramp output signal that is provided from the transceiver to the power amplifier (RAMPOUT) may be controlled to be squelched during a predetermined portion of the inter-slot period, additional details of which are discussed below.

FIG. 2 also shows a detailed inset of the inter-slot period. As shown, the inter-slot period is formed of a number of guard bits which are surrounded on both sides by a number of tail bits. The inset further shows that control information is received at the transceiver from the baseband processor (i.e., on serial data input/output lines (SDIO/SCLK)). Furthermore, an enable signal is received via another serial control line (SEN). When this enable signal transitions from a low state to a high state (i.e., at a quarter bit (qB) count of 17), the control information sent in the inter-slot period, namely data written into a selected register (i.e., register 23h in the embodiment of FIG. 2) from the baseband processor is applied. Specifically, this data may include control information to squelch the RF signal and clamp the ramp output.

Thus as shown in the inset of FIG. 2, the RF output (RFO) signal is squelched to a zero value. Accordingly, a corresponding output of the PA is also squelched, as shown in FIG. 2 (PA_OUT). While various manners of squelching the RF output signal from the transceiver are possible, in one embodiment an output buffer of the transceiver that conditions RF data for transmission may be disabled. In this embodiment, the control information sent from the baseband processor in the inter-slot period may include a disable bit to disable the output buffer. Accordingly, when this disable bit is activated via the SEN signal, the output buffer is disabled, thereby squelching the RF output. Disabling the output buffer may prevent output signals from a transceiver, while maintaining other circuitry of the transceiver in continued operation, such as a phase locked loop (PLL). Accordingly, no additionally settling time is needed to begin transmitting RF output data when the output buffer disable signal is deasserted.

Additional control information may be sent in the register during the inter-slot period. For example, the register may include ramp output values for use in an 8-PSK mode. Such values may include both digital and analog values, either of which may be used depending on a desired mode of operation. Furthermore, a gain value may be sent which may be used to control a variable gain amplifier (VGA) within the transceiver during 8-PSK operation. Still further, a mode bit may be transmitted to indicate the mode of operation for the next slot, e.g., 8-PSK or GMSK mode.

Of course, other manners of disabling the RF output signal may be accommodated. For example, the RF output line may be coupled to a switch, which is controlled based on control information, e.g., received from the transceiver. In yet other embodiments, the transceiver may include control logic to independently disable its RF output at the appropriate time. While such control logic may take many forms, in some implementations the logic may either receive a control signal from the baseband processor or, at the appropriate point in the inter-slot period, be programmed to effect disabling of the RF output, e.g., via disabling the output buffer, opening a switch or another such way.

Still referring to the inset of FIG. 2, when enabled by the control information during the inter-slot period, the ramp output signal is also controlled. Specifically, the ramp output signal (RAMPOUT) is also clamped to a zero value. In one embodiment, the mode select bit within the control information may be used to cause the ramp output signal to be clamped. However, different manners of squelching the ramp output signal may be effected in other embodiments.

In such manner, power transients may be reduced or removed from the output of the power amplifier. In the embodiment shown in FIG. 2, these squelch activities are active for four quarter bits, however, the scope of the present invention is not so limited. Accordingly, by providing an inter-slot silent period, improved power amplifier performance may be achieved, allowing a handset or other wireless device including the PA to pass qualification tests, such as spectral requirements for switching transients during a mixed mode multi-slot transmission.

In different modes of operation, the ramp output signal sent from the transceiver may be obtained and used differently. Specifically, in a GMSK mode, the voltage received by the transceiver at its ramp input pin (i.e., RAMPIN in FIG. 1) may be passed to its output (i.e., RAMPOUT in FIG. 1) to provide a ramp voltage to the power amplifier. In other words, the ramp output tracks the ramp input. In contrast, during an 8-PSK mode, the voltage received on the ramp input pin of the transceiver may be used to modulate the gain of the transceiver to achieve its ramping. Thus, the output ramp signal may be an independently controllable output, which is used to provide a bias voltage (i.e., at a fixed voltage) to the power amplifier for the 8-PSK mode of operation. In some implementations, transceiver 30 may include a switch, such as a single pole double throw (SPDT) switch to either provide the ramp signal received from the baseband processor 20 as the ramp output signal to PA 40 or to provide an independently-generated ramp output signal from transceiver 30 to PA 40.

Still referring to the inset of FIG. 2 after the inter-slot silent period, note that the ramp out signal begins tracking the input ramp signal (RAMPIN) from the baseband processor. Furthermore, note that the RF output signal switches from a squelched value to an active signal value, and the corresponding output of the PA also begins ramping up in preparation for the next communication slot.

Referring now to FIG. 3, shown is a timing diagram of a multi-slot transition in accordance with another embodiment of the present invention. As shown in FIG. 3, a first slot (Slot X) is to be transmitted using GMSK modulation, while a second slot (Slot X+1) is to be transmitted using 8-PSK modulation. As shown in FIG. 3, transmission control information from a baseband processor to the transceiver may be the same as that described above with regard to FIG. 2. Note that in the embodiment of FIG. 3, before this inter-slot silent period, the ramp output signal tracks the ramp input signal received from the transceiver. However, after the inter-slot silent period, the ramp output signal during the 8-PSK mode does not track the ramp input signal. Instead, the ramp output signal may be dependent upon a ramp control value received, e.g., from the baseband processor. The RF output is squelched at a predetermined portion of the inter-slot period, as is the ramp output signal. After the inter-slot silent period, the RF output signal is again enabled, allowing the power amplifier to ramp up for transmission in the second slot.

Referring now to FIG. 4, shown is block diagram of a transceiver in accordance with one embodiment of the present invention. Such a transceiver may be a CMOS transceiver for quad-band GSM/GPRS/EDGE wireless communications such as for use in cellular handsets and wireless data modems, although the scope of the present invention is not so limited.

As shown in FIG. 4, a transceiver 232 may be incorporated into a wireless system, such as the exemplary wireless system 230. Transceiver 232 may include a receiver 234 and a transmitter 236. Receiver 234 may be a heterodyne or a homodyne receiver may include a low intermediate frequency (IF) architecture. In some embodiments of the invention, transmitter 236 may be a direct up or heterodyne transmitter. For embodiments of the invention in which transmitter 236 is a heterodyne transmitter, the heterodyne transmitter may incorporate an offset phase locked loop (PLL) architecture.

Still referring to FIG. 4, a ramp generator 233 may generate ramp signals to be provided as the ramp output, e.g. for an 8-PSK mode of operation. Accordingly, a switch S 1 is coupled to select either the output of ramp generator 233 or the ramp input signal from baseband processor 258 to pass along as the ramp output signal to power amplifier 256. Furthermore, during 8-PSK operation, the incoming ramp signal from baseband processor 258 may be provided to transmitter 236 to modulate the gain.

As depicted in FIG. 4, in some embodiments of the invention, a synthesizer 237 of transceiver 232 may provide a radio frequency (RF) local oscillator signal to receiver 234; and furthermore, synthesizer 237 may provide both an RF local oscillator signal and an IF local oscillator signal to transmitter 236. Depending on the particular embodiment of the invention, synthesizer 237 may incorporate an RF PLL or an IF PLL or a combination of both of these components. The main function of synthesizer 237 is to provide local oscillator signals to receiver 234 and transmitter 236.

As further shown in FIG. 4, a baseband interface 240 forms an interface to a baseband processor 258, in some embodiments of the invention. Baseband interface 240 may be a digital interface, an analog interface or a combination of a digital and an analog interface, depending on the particular embodiment of the invention.

Also shown in FIG. 4 is a control storage 250 within transceiver 232. Control storage 250 may be coupled to receive and store various configuration and control information. As shown in FIG. 4, control storage 250 is further coupled to provide information therefrom to ramp generator 233, receiver 234, synthesizer 237 and transmitter 236. Furthermore, while not shown for ease of illustration in FIG. 4, configuration information from control storage 250 may further be coupled to power amplifier 256 and RF filters 254, an antenna switch 257 and an antenna 258, to control these components as desired.

While shown in FIG. 4 as including the particular components shown therein, it is to be understood that in other embodiments, transceiver 232 may include additional and/or different components, and the embodiment shown in FIG. 4 is for illustrative purposes.

Referring now to FIG. 5, shown is a block diagram of a system in accordance with one embodiment of the present invention. As shown in FIG. 5, system 305 may be a cellular telephone handset, although the scope of the present invention is not so limited. For example, in other embodiments, the system may be a pager, personal digital assistant (PDA) or other such device. As shown, an antenna 302 may be coupled to a transceiver 102, such as the transceiver shown in FIG. 4. In turn, transceiver 102 may be coupled to a digital signal processor (DSP) 310, which may handle processing of baseband communication signals. In turn, DSP 310 may be coupled to a microprocessor 320, such as a central processing unit (CPU) that may be used to control operation of system 305 and further handle processing of application programs, such as personal information management (PIM) programs, email programs, downloaded games, and the like. Microprocessor 320 and DSP 310 may also be coupled to a memory 330. Memory 330 may include different memory components, such as a flash memory and a read only memory (ROM), although the scope of the present invention is not so limited. Furthermore, as shown in FIG. 5, a display 340 may be present to provide display of information associated with telephone calls and application programs. Although the description makes reference to specific components of system 305, it is contemplated that numerous modifications and variations of the described and illustrated embodiments may be possible. Furthermore, transceiver 102 may include an article in the form of a machine-readable storage medium (or may be coupled to such an article, e.g., memory 330) onto which there are stored instructions and data that form a software program. The software program may be implemented by transceiver 102 to perform activities according to control information received from DSP 310.

While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications.