Serial-to-parallel conversion circuit and method of designing the same

(19)

(11)

EP 2 015 457 A3

(12)	EUROPEAN PATENT APPLICATION

(88)	Date of publication A3:
	12.08.2009 Bulletin 2009/33

(43)	Date of publication A2:
	14.01.2009 Bulletin 2009/03

(21)	Application number: 08160241.9

(22)	Date of filing: 11.07.2008

(51)

International Patent Classification (IPC):

H03M 9/00^(2006.01)
H04L 12/40^(2006.01)

G06F 13/42^(2006.01)

(84)	Designated Contracting States:
	AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MT NL NO PL PT RO SE SI SK TR
	Designated Extension States:
	AL BA MK RS

(30)

Priority:

12.07.2007 JP 2007183444

(71)	Applicant: MITSUBISHI HEAVY INDUSTRIES, LTD.
	Tokyo 108-8215 (JP)

(72)	Inventors:
	Ishii, Shigeru c/o MITSUBISHI HEAVY INDUSTRIES, LTD. KOMAKI Aichi 485-8561 (JP) Nomachi, Masaharu c/o Osaka University TOYONAKA-SHI Osaka 560-0043 (JP)

(74)	Representative: Bongiovanni, Simone et al
	STUDIO TORTA Via Viotti 9 10121 Torino 10121 Torino (IT)

(54)	Serial-to-parallel conversion circuit and method of designing the same

(57) The invention eliminates a race condition without restricting reception speed. The invention provides a method of designing a serial-to-parallel conversion circuit, the method including determining a rule for data (D) and a strobe (S) when a first-stage memory device (10a,20a) in a shift register (SF1,SF2) latches data and when the memory device holds the data; providing a logical circuit (30,40) for generating an output conforming to the rule at a data input side of the shift register; and shifting a data latch timing of the memory device by a half-period.

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