(19)
(11) EP 2 070 088 A2

(12)

(88) Date of publication A3:
19.06.2008

(43) Date of publication:
17.06.2009 Bulletin 2009/25

(21) Application number: 07840800.2

(22) Date of filing: 08.08.2007
(51) International Patent Classification (IPC): 
G11C 11/00(2006.01)
(86) International application number:
PCT/US2007/075521
(87) International publication number:
WO 2008/021912 (21.02.2008 Gazette 2008/08)
(84) Designated Contracting States:
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC MT NL PL PT RO SE SI SK TR
Designated Extension States:
AL BA HR MK RS

(30) Priority: 08.08.2006 US 836343 P
08.08.2006 US 836437 P
28.08.2006 US 840586 P
27.10.2006 US 855109 P
16.03.2007 US 918388 P

(60) Divisional application:
09159271.7
09159276.6

(71) Applicant: Nantero, Inc.
Woburn, MA 01801 (US)

(72) Inventors:
  • BERTIN, Claude, L.
    South Burlington, VT 05403 (US)
  • RUECKES, Thomas
    Rockport, MA 01966 (US)
  • WARD, Jonathan, W.
    Fairfax, VA 22033 (US)
  • GUO, Frank
    Danville, CA 94506 (US)
  • KONSEK, Steven, L.
    Malmö (SE)
  • MEINHOLD, Mitchell
    Arlington, MA 02474 (US)

(74) Representative: Benson, Christopher 
Harrison Goddard Foote Fountain Precinct Balm Green
Sheffield S1 2JA
Sheffield S1 2JA (GB)

   


(54) NONVOLATILE RESISTIVE MEMORIES, LATCH CIRCUITS, AND OPERATION CIRCUITS HAVING SCALABLE TWO-TERMINAL NANOTUBE SWITCHES