(19)
(11) EP 2 081 036 A8

(12) CORRECTED EUROPEAN PATENT APPLICATION
Note: Bibliography reflects the latest situation

(15) Correction information:
Corrected version no 1 (W1 A2)

(48) Corrigendum issued on:
23.06.2010 Bulletin 2010/25

(88) Date of publication A3:
09.06.2010 Bulletin 2010/23

(43) Date of publication:
22.07.2009 Bulletin 2009/30

(21) Application number: 09004194.8

(22) Date of filing: 08.09.2004
(51) International Patent Classification (IPC): 
G01R 31/3185(2006.01)
(84) Designated Contracting States:
DE GB IT

(30) Priority: 09.09.2003 JP 2003316484

(62) Application number of the earlier application in accordance with Art. 76 EPC:
04787748.5 / 1669768

(71) Applicant: Advantest Corporation
Tokyo 179-0071 (JP)

(72) Inventors:
  • Umemura, Yoshiharu
    Tokyo 179-0071 (JP)
  • Okayasu, Toshiyuki
    Tokyo 179-0071 (JP)
  • Awaji, Toshiaki
    Tokyo 179-0071 (JP)
  • Yamakawa, Masahiro
    Tokyo 179-0071 (JP)

(74) Representative: MERH-IP Matias Erny Reichl Hoffmann 
Paul-Heyse-Strasse 29
80336 München
80336 München (DE)

 
Remarks:
This application was filed on 24-03-2009 as a divisional application to the application mentioned under INID code 62.
 


(54) Testing apparatus


(57) Apparatus for testing a semiconductor device under test (DUT) is provided, which comprises a driver applying a test signal to DUT; a sampler sampling an output signal outputted from DUT at a timing indicated by a strobe signal applied thereto and outputting a sample voltage; a comparator comparing the sample voltage with a reference voltage and outputting a comparison result indicating whether the sample voltage is higher than the reference voltage; a logical comparator detecting the comparison result at the timing indicated by the strobe signal and determining the quality of DUT by comparing the thus detected comparison result with an expected value.