Plasma display and method of driving the same

Abstract

 A plasma display and a method of driving a plasma display are disclosed. The method includes dividing the cells into multiple groups, separately address driving each of the groups, and sustain-discharge driving all of the previously addressed groups together.

Description

[0001] The field relates to a plasma display and a method of driving the same.

[0002] A plasma display is a display device that uses a plasma display panel (PDP) that displays characters or images using plasma that is generated by a gas discharge. In the PDP, a plurality of cells are arranged substantially in a matrix form. The plasma display divides one frame into a plurality of subfields each having a corresponding weight, and drives the plurality of subfields to display an image.

[0003] Generally, each subfield includes a reset period, an address period, and a sustain period. In the reset period, the cells are initialized. In the address period, a scan pulse is sequentially applied to a plurality of scan electrodes to select cells that will emit light (hereinafter referred to as "on-cells") and cells that will not emit light (hereinafter referred to as "off-cells"). In the sustain period, a sustain pulse that alternately has a high level voltage and a low level voltage is applied to display electrodes to perform sustain-discharges in cells selected to emit light, in order to display an image.

[0004] An address display period separation (ADS) method may be used to address- and sustain-discharge the cells. In the ADS method, after an address operation is performed for all the cells in the address period, a sustain-discharge operation is performed for all the cells in the sustain period. That is, the address period is separated from the sustain period. In the ADS method, after an address operation is performed by sequentially applying a scan pulse to a plurality of scan electrodes for forming the cells, the sustain-discharge operation is performed. Accordingly, some scan electrodes to which the address operation is initially performed are sustain-discharged after the scan pulse is applied to all the scan electrodes is performed. This may result in unstable sustain-discharge of these initially-addressed cells because priming particles and/or wall charges generated by the address operation may be diminished before the sustain-discharge is generated.
In addition, in order to simplify a driving circuit of the plasma display, a sustain pulse alternately having a high level voltage and a low level voltage may be applied to one display electrode while a ground voltage is applied to another display electrode in a sustain period. In this case, the ground voltage is applied to the one display electrode to perform a next operation. However, since a switch for transmitting the ground voltage is fabricated as back-to-back transistors, cost of the driving circuit is increased.

[0005] The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.

[0006] One aspect is a method of driving a plasma display including a plurality of first electrodes, a plurality of second electrodes, and a plurality of cells formed by the first electrodes and the second electrodes. The method includes dividing the plurality of first electrodes into a plurality of groups including a first group and a second group, addressing on-cells and off-cells with the first group of electrodes in a first address period, sustain-discharging the on-cells of the first group in a first sustain period, where the sustain period is subsequent to the first address period, and addressing on-cells and off-cells with the second group of electrodes in a second address period, where the second address period is subsequent to the first sustain period. Sustain-discharging the on-cells of the first group includes applying a first voltage to the plurality of first electrodes while applying a reference voltage to the plurality of second electrodes during a first period, the first voltage being higher than the reference voltage, applying a second voltage to the plurality of first electrodes while applying the reference voltage to the plurality of second electrodes during a second period subsequent to the first period, the second voltage being lower than the reference voltage, increasing the voltage at the plurality of first electrodes from the second voltage to a third voltage during a third period subsequent to the second period, the third voltage being higher than the second voltage, floating the plurality of first electrodes during a fourth period subsequent to the third period, applying a fourth voltage to the plurality of second electrodes while floating the plurality of first electrodes, the fourth voltage being higher than the reference voltage, and gradually decreasing the voltage at the plurality of first electrodes to a fifth voltage during a fifth period subsequent to the fourth period, the fifth voltage being lower than the reference voltage.

[0007] Another aspect is a plasma display including a plurality of first electrodes, a plurality of second electrodes, a plurality of cells formed near the plurality of first electrodes and the plurality of second electrodes, a first driver configured to increase a voltage at the plurality of first electrodes from a first voltage to a second voltage during a first period, float the plurality of first electrodes during a second period subsequent to the first period, and gradually decrease the voltage at the plurality of first electrodes to a third voltage during a third period subsequent to the second period, and a second driver configured to apply a fourth voltage to the plurality of second electrodes during the first period, apply a fifth voltage to the plurality of second electrodes during the second period, and apply a sixth voltage to the plurality of second electrodes during the third period, the fourth voltage being higher than the first voltage and the fifth voltage being higher than the fourth voltage.

[0008] Another aspect is a method of driving a plasma display including a plurality of first electrodes, a plurality of second electrodes, and a plurality of cells formed near the plurality of first electrodes and the plurality of second electrodes. The method includes increasing a voltage at the plurality of first electrodes from a first voltage to a second voltage while applying a third voltage to the plurality of second electrodes during a first period, floating the plurality of first electrodes during a second period subsequent to the first period, applying a fourth voltage to the plurality of second electrodes while floating the plurality of first electrodes, the fourth voltage being higher than the third voltage, and gradually decreasing the voltage at the plurality of first electrodes to a fifth voltage during a third period subsequent to the second period.

[0009] FIG. 1 is a schematic block diagram of a plasma display according to an embodiment.

[0010] FIG. 2 is a schematic drawing showing a plasma display according to an embodiment.

[0011] FIG. 3 is a schematic drawing showing driving waveforms of a plasma display according to an embodiment.

[0012] FIG. 4 is a schematic diagram of driving circuits of a plasma display according to an embodiment.

[0013] FIG. 5 is a timing diagram of a driving waveform shown in FIG. 3.

[0014] FIG. 6 to FIG. 8 are diagrams showing operations of driving circuits shown in FIG. 4 according to timing shown in FIG. 5.

[0015] In the following detailed description, only certain embodiments of the present invention have been shown and described, simply by way of illustration. As those skilled in the art would realize, the described embodiments may be modified in various ways, without departing from the scope of the present invention as defined in the appended claims.

[0016] Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive. Like reference numerals generally designate like elements throughout the specification.

[0017] Throughout this specification and the claims that follow, when it is described that an element is "coupled" to another element, the element may be "directly coupled" to the other element or "indirectly coupled" to the other element through a third element.

[0018] Furthermore, "wall charges" described in this specification indicate charges that are formed adjacent to each electrode on a wall (e.g., a dielectric layer) of a cell. Wall charges may not actually contact an electrode, however in this specification, it is described that wall charges are "formed," "accumulated," or "stacked" in or on the electrode, and a wall voltage indicates a potential difference that is formed in a wall of a cell by the wall charges.

[0019] FIG. 1 is a schematic block diagram of a plasma display according to an embodiment.

[0020] Referring to FIG. 1, a plasma display includes a PDP 100, a controller 200, an address electrode driver 300, a scan electrode driver 400, and a sustain electrode driver 500.

[0021] The PDP 100 includes a plurality of display electrodes Y1 to Yn and X1 to Xn, a plurality of address electrodes (hereinafter referred to as "A electrodes") A1 to Am, and a plurality of cells 110. Among the plurality of display electrodes Y1 to Yn and X1 to Xn, Y1 to Yn are scan electrodes (hereinafter referred to as "Y electrodes"), and X1 to Xn are sustain electrodes (hereinafter referred to as "X electrodes"). The Y electrodes Y1 to Yn and the X electrodes X1 to Xn extend substantially in a row direction and substantially form parallel pairs of Y and X electrodes. The A electrodes A1 to Am extend substantially in a column direction crossing the row direction and are substantially parallel to each other. Each of the Y electrodes Y1 to Yn may correspond to one of the X electrodes X1 to Xn. In some embodiments, each of the Y electrodes Y1 to Yn corresponds to two or more of the X electrodes X1 to Xn. Cells 110 are formed in spaces near the crossings of the A electrodes A1 to Am, the Y electrodes Y1 to Yn, and the X electrodes X1 to Xn. The above-described PDP 100 is only one example, and the PDP 100 may have another structure.

[0022] The controller 200 receives a video signal and an input control signal for controlling the display of the video signal. The video signal includes luminance information of each of the cells 110, and the luminance of each of the cells 110 may be represented as one of a number of gray levels. The input control signal may include a vertical synchronization signal and a horizontal synchronization signal. The controller 200 divides one frame into a plurality of subfields, each of which has a weight. The controller 200 processes the video signal and the input control signal based on the plurality of subfields, and generates an A electrode driving control signal, a Y electrode driving control signal, and an X electrode driving control signal. The controller 200 outputs the A electrode driving control signal to the address electrode driver 300, the Y electrode driving control signal to the scan electrode driver 400, and the X electrode driving control signal to the sustain electrode driver 500.

[0023] The address electrode driver 300 applies driving voltages to the A electrodes A1 to Am in accordance with the A electrode driving control signal.

[0024] The scan electrode driver 400 applies driving voltages to the Y electrodes Y1 to Yn in accordance with the Y electrode driving control signal.

[0025] The sustain electrode driver 500 applies driving voltages to the X electrodes X1 to Xn in accordance with the X electrode driving control signal.

[0026] FIG. 2 is a schematic drawing showing a driving method of a plasma display according to an embodiment.

[0027] Referring to FIG. 2, one frame is divided into a plurality of subfields, and each subfield SF includes a reset period, a mixed address/sustain period T1, a brightness compensation period T2, and a common sustain period T3. The Y electrodes Y1 to Yn are divided into a number of groups G1 to Gk according to their physical locations. For example, the Y electrodes Y1 to Yn/k form the first group G1, and the Y electrodes Yn/k+1 to Y2n/k form the second group G2. Similarly, the Y electrodes Y(k-1)n/k+1 to Yn form the k-th group Gk. Alternatively, the Y electrodes separated by a certain spacing therebetween may be grouped into one group, or the Y electrodes Y1 to Yn may be grouped in a random manner.
In the reset period, a reset waveform is applied to the Y electrodes Y1 to Yn of all groups G1 to Gk to initialize the wall charge state of the cells. The mixed address/sustain period T1 includes a plurality of address periods corresponding to the groups G1 to Gk and a plurality of sustain periods corresponding to the groups G1 to Gk. That is, in the mixed address/sustain period T1, the address periods and the sustain periods are mixed. Accordingly, each address/sustain period T1 has an address portion and a sustain portion. In each address portion, on-cells and off-cells are selected among the cells of the group being addressed. In each sustain portion, on-cells of the groups G1 to Gk are sustain-discharged. In the brightness compensation period T2, variation in brightness is compensated in the on-cells of the groups G1 to Gk. The common sustain period T3 is a period that sustain-discharges the on-cells of the groups G1 to Gk in common for a predetermined time.

[0028] In some embodiments, the cells of the groups G1 to Gk are initialized to off-cells in the reset period R1. Alternatively, the cells of the groups G1 to Gk may not simultaneously be initialized in the reset period R1, and a plurality of reset periods corresponding to the groups G1 to Gk may be used. In this case, each reset period may be executed just prior to the address period of a corresponding group.

[0029] In the mixed address/sustain period T1, an address operation is performed on the cells of the first group G1 during address period AG1 to select the on-cells, and subsequently a sustain-discharge operation is performed to sustain-discharge the on-cells of the first group G1 during sustain period S11. Next, an address operation is performed on cells of the second group G2 during address period AG2 to select the on-cells, which is followed by a sustain-discharge operation that is performed to sustain-discharge the on-cells of the first and second groups G1 and G2 during the sustain period S12/S21. Subsequently, an address operation is performed to select the on-cells in the third group G3 during the address period AG3, and again a sustain-discharge operation is performed to sustain-discharge the on-cells of the groups G1, G2, and G3 during the sustain period Sl3/S22/S31. In a similar manner, an address operation is performed to select the on-cells in the k-th group Gk in the address period AGk, and a sustain-discharge operation is performed during the sustain period S1k/S2(k-1)/S3(k-2)/.../Sk1 to sustain-discharge the on-cells in the groups G1 to Gk. Accordingly, in the address/sustain mixed period T1, the on-cells of the group having just been addressed, and the on-cells of the groups having previously been addressed are sustain discharged together.

[0030] When the operation of the mixed address/sustain period T1 is performed as described above, the number of sustain-discharge operations for the cells of each group may vary, which leads to corresponding variance in brightness of the groups G1 to Gk. To compensate for this brightness variance, the brightness compensation period T2 is performed so as to correct the brightness differences of the respective groups. In the brightness compensation period T2, the sustain-discharge operations are performed so that the same number of sustain-discharges are generated in the on-cells for each of the groups G1 to Gk.

[0031] During the brightness compensation period T2, a sustain-discharge operation is performed during a sustain period S2k/S3(k-1)/.../Sk2 to sustain-discharge the on-cells of the groups G2 to G4 while the on-cells of the group G1 are not sustain-discharged. Subsequently, a sustain-discharge operation is performed to sustain-discharge the on-cells of the groups G3 to Gk during a sustain period S3k/.../Sk3 while the on-cells of the groups G1 and G2 are not sustain-discharged. In a similar manner, a sustain-discharge operation is performed to sustain-discharge the on-cells of the k-th group Gk during a sustain period Skk while the on-cells of the groups G1-Gk-1 are not sustain-discharged. Accordingly, the same number of sustain-discharges are generated for each of the groups over one subfield so that the on-cells of the groups G1 to Gk can have the same brightness in the same subfield.
In the common sustain period T3, a sustain-discharge operation is performed for a time to sustain-discharge the on-cells of all of the groups G1 to Gk. Weights of corresponding subfields are set by controlling the length of the common sustain period T3. After the common sustain period T3 ends, the reset period of the next subfield starts.

[0032] Referring to FIG. 2, the common sustain period T3 is performed after the brightness compensation period T2. In some embodiments, the common sustain period T3 may be performed between the mixed address/sustain period T1 and the brightness compensation period T2. In addition, in some embodiments, the common sustain period T3 is not performed when the weight of the corresponding subfield is satisfied by the sustain-discharge operation provided in the mixed address/sustain period T1 and the brightness compensation period T2.

[0033] FIG. 3 is a timing diagram showing driving waveforms of a plasma display according to an embodiment. It is shown for ease of description in FIG. 3 that the Y electrodes Y1 to Yn are grouped into two groups G1 and G2, and the Y electrodes of the first group G1 are denoted as Yg1 and the Y electrodes of the second group G2 are denoted as Yg2. In addition, a driving waveform applied to the A electrodes is not shown in FIG. 3.

[0034] Referring to FIG. 3, during the reset period R1, a voltage at the Y electrodes Yg1 and Yg2 of the first and second groups G1 and G2 is gradually increased from a voltage of (VscH-VscL), which is the difference between a voltage of VscH and a voltage of VscL, to a voltage of [Vs+(VscH-VscL)], which is a sum of a voltage of Vs and the voltage of (VscH-VscL), while a reference voltage (0V of FIG. 3) is applied to the X electrodes. Alternatively, the voltage at the Y electrodes may be gradually increased from a voltage that is different from the voltage of (VscH-VscL), and may be gradually increased to a voltage that is different from the voltage of [Vs+(VscH-VscL)]. While the voltage at the Y electrode Yg1 and Yg2 is gradually increased, weak reset discharges are generated in the cells of the first and second groups G1 and G2 such that wall charges are formed on the cells of the first and second groups G1 and G2. Subsequently, the voltage at the Y electrodes Yg1 and Yg2 is gradually decreased from the voltage of (VscH-VscL) to a voltage of Vnf while a voltage of Ve is applied to the X electrodes. Alternatively, the voltage at the Y electrodes may be gradually decreased from a voltage that is different from the voltage of (VscH-VscL). While the voltage at the Y electrode is gradually decreased, weak reset discharges are generated in the cells of the first and second groups G1 and G2 such that the wall charges formed on the cells of the first and second groups G1 and G2 are erased. As a result, the cells of the first and second groups G1 and G2 are initialized to be off-cells. In this case, the voltage of (Vnf-Ve) may be similar to a discharge firing voltage between the Y electrode and the X electrode. A wall voltage between the Y electrode and the X electrode is approximately 0V such that the off-cells can be prevented from being discharged in the sustain period.
In the address period AG1 of the mixed address/sustain period T1, a scan pulse having a voltage of VscL is sequentially applied to the Y electrodes Yg1 of the first group G1 while the voltage of Ve is applied the X electrodes and a voltage of VscH that is higher than the voltage of VscL is applied to the Y electrodes Yg2 of the second group G2. The voltage of VscL may be equal to or lower than the voltage of Vnf. An address pulse having a positive voltage (not shown) is applied to the A electrode of a cell that will be set to the on-cell among the cells of the first group G1 formed by the Y electrode receiving the scan pulse. Then, an address discharge is generated in the cell of the first group G1 receiving the scan pulse and the address pulse. As a result, positive wall charges are formed on the Y electrode, and negative wall charges are formed on the X and A electrodes such the on-cell is set. In contrast, the voltage of VscH is applied to the Y electrodes not receiving the scan pulse, and the reference voltage is applied to the A electrodes not receiving the address pulse.

[0035] In the sustain period S11, a sustain pulse alternately having the voltage of Vs and a voltage of -Vs is applied to the Y electrodes Yg1 and Yg2 of the first and second groups G1 and G2, and the reference voltage is applied to the X electrodes. The voltage of -Vs may be equal to the voltage of VscL. As shown in FIG. 3, a sustain pulse is applied once to the Y electrodes Yg1 and Yg2, i.e., each of the voltage of Vs and the voltage of -Vs is applied once to the Y electrodes. The sustain-discharge is generated twice in the on-cells of the first group G1. As a result, negative wall charges are formed on the Y electrodes of the on-cells of the first group G1 and positive wall charges are formed on the X electrodes of the on-cells of the first group G1 by the sustain-discharge according the voltage of Vs. Subsequently, positive wall charges are formed on the Y electrodes of the on-cells of the first group G1 and negative wall charges are formed on the X electrodes of the on-cells of the first group G1 by the sustain-discharge according the voltage of -Vs. The sustain-discharge is not generated in the cells of the second group G2.

[0036] In this case, the wall charge state of the cells in the second group G2 may be different from the wall charge state set in the reset period R1 by the sustain-discharge generated in the on-cells of the first group G1. To compensate the wall charge state of the second group G2, the voltage at the Y electrodes is gradually decreased to the voltage of Vnf after the sustain-discharges in the sustain period S11. A weak discharge is generated in the cells of the second group G2 such that the cells of the second group G2 are initialized again.

[0037] Subsequently, in the address period AG2, the scan pulse having the voltage of VscL is sequentially applied to the Y electrodes Yg2 of the second group G2 while the voltage of Ve is applied to the X electrodes and the voltage of VscH is applied to the Y electrodes Yg1 of the first group G1. The address pulse having the positive voltage is applied to the A electrode of a cell that will be set to the on-cell among the cells of the second group G2 formed by the Y electrode receiving the scan pulse. Then, an address discharge is generated in the cell of the second group G2 receiving the scan pulse and the address pulse. As a result, positive wall charges are formed on the Y electrode, and negative wall charges are formed on the X and A electrodes such that the on-cell is set in the second group G2.

[0038] In the sustain period S12/S21, the sustain pulse alternately having the voltage of Vs and the voltage of -Vs is applied to the Y electrodes Yg1 and Yg2 of the first and second groups G1 and G2 while the reference voltage is applied to the X electrodes. Since the positive wall charges are formed on the Y electrodes and the negative wall charges are formed on the X electrodes in the on-cells of the first groups G1 as well as on-the cells of the second group G2 when the voltage of Vs is applied to the Y electrodes Yg1 and Yg2, the sustain-discharge is generated in the on-cells of the first and second groups G1 and G2. As a result, the negative wall charges are formed on the Y electrodes and positive wall charges are formed on the X electrodes, in the on-cells of the first and second groups G1 and G2. Subsequently, positive wall charges are formed on the Y electrodes and negative wall charges are formed on the X electrodes, by the sustain-discharge according the voltage of -Vs. Accordingly, the number of sustain-discharges is "2" in the on-cells of the second group G2, but the number of sustain-discharges is "4" in the on-cells of the first group G1.

[0039] Subsequently, the brightness compensation period T2 is performed to set the number of sustain-discharges in the first group G1 to be equal to the number of sustain-discharges in the second group G2. In the brightness compensation period T2, the voltage of -Vs is applied to the Y electrodes Yg1 of the first group G1 and the voltage of Vs is applied to the Y electrodes Yg2 of the second group G2 while the reference voltage is applied to the X electrodes. Then, the sustain-discharge is generated in the on-cells of the second group G2 such that the negative wall charges and the positive wall charges are respectively formed on the Y electrodes and the X electrodes in the second group G2. In contrast, the sustain-discharge is not generated in the on-cells of the first group G1 since the voltage -Vs applied to the Y electrodes is lower than the reference voltage applied to the X electrodes. As a result, the positive wall charges on the Y electrodes and the negative wall charges on the X electrode are maintained in the first group G1. Subsequently, the voltage of - Vs is applied to the Y electrodes Yg2 of the second group G2 while the reference voltage and the voltage of -Vs are respectively applied to the X electrodes and the Y electrodes of the first group G1. Then, the sustain-discharge is generated in the on-cells of the second group G2 such that the positive wall charges and the negative wall charges are respectively formed on the Y electrodes and the X electrodes in the second group G2. However, the sustain-discharge is not generated in the on-cells of the first group G1 since the voltage of -Vs applied to the Y electrodes is lower than the reference voltage applied to the X electrodes. As a result, the positive wall charges on the Y electrodes and the negative wall charges on the X electrode are maintained in the first group G1. Therefore, the sustain-discharges are generated twice in the on-cells of the second group G2 in the brightness compensation period T2 such that the number of sustain-discharges in the first group G1 becomes equal to the number of sustain-discharges in the second group G2.

[0040] Alternatively, the brightness compensation period T2 may be performed by applying the voltage of Vs to the Y electrodes Yg1 of the first group G1 when the voltage of -Vs is applied to the Y electrodes Yg2 of the second group G2.

[0041] In the common sustain period T3, the voltage of Vs and the voltage of -Vs are further applied to the Y electrodes Yg1 and Yg2 while the reference voltage is applied to the X electrodes. The on-cells of the first and second groups G1 and G2 are additionally sustain-discharged. As described above, the common sustain period T3 may be omitted.

[0042] According to an embodiment, a plurality of Y electrodes Y1 to Yn are divided into groups G1 to Gk, and the operation of the sustain period is performed between the two adjacent address periods. As a result, a time provided between the address discharge and the sustain-discharge is reduced to generate a stable sustain-discharge. In addition, the voltage at the Y electrodes is gradually decreased to the voltage of Vnf after the sustain-discharge is performed in the sustain period S11 such that the wall charge state of the second group G2 can be compensated. As a result, the address discharge can be stably generated in the address period AG2 for the second group G2.

[0043] A driving circuit for generating the driving waveforms shown in FIG. 3 will be described with reference to FIG. 4. FIG. 4 is a schematic diagram of a driving circuit of a plasma display according to an embodiment. In FIG. 4, switches are n-channel field effect transistors, and each n-channel field effect transistors may have a body diode having an anode coupled to a source and a cathode coupled to a source. Alternatively, other types of transistors may be used as the switches. In addition, each transistor is shown as one transistor in FIG. 3, but each transistor may be formed by a plurality of transistors coupled in parallel. Furthermore, one of the X electrodes X1 to Xn and one of the Y electrodes Y1 to Yn are shown in FIG. 3, and a capacitive component formed by the X electrode and the Y electrode is shown as a panel capacitor.

[0044] Referring to FIG. 4, a driving circuit of a scan electrode driver 400 includes an inductor L, transistors Yr, Yf, Ys1, Ys2, Yfr, and YscL, a Zener diode ZD, a capacitor CscH, a diode DscH, and a scan circuit 410.

[0045] The scan circuit 410 has two input terminals and an output terminal, and includes transistors Sch and Scl. A plurality of scan circuits 410 that correspond to the plurality of Y electrodes Y1 to Yn are formed, but one scan circuit 410 corresponding to one Y electrode is shown in FIG. 3. In addition, a number of scan circuits 410 may be formed as one integrated circuit.

[0046] A source of the transistor Sch and a drain of the transistor Scl are coupled to the output terminal of the scan circuit 410, and the output terminal is coupled to the Y electrode. A source of the transistor Scl is coupled to one input terminal of the scan circuit 410, which is coupled to one terminal of the capacitor CscH. A drain of the transistor Sch is coupled to another input terminal of the scan circuit 410, which is coupled to a terminal of the capacitor CscH. A source of the transistor YscL is coupled to a power source for supplying the voltage of VscL, and a drain of the transistor YscL is coupled to the Y electrode via one input terminal of the scan circuit 410. A power source for supplying the voltage of VscH is coupled to another terminal of the capacitor CscH via a diode DscH. When the transistor YscL is turned on, the voltage of (VscH-VscL) may be charged to the capacitor CscH. In the address period, the transistor YscL is turned on, and one of the transistors Sch and Scl of the scan circuit 410 is turned on. When the transistor Sch is turned on, the voltage of VscH is applied to the Y electrode by the capacitor CscH and the power source VscL. Alternatively, the voltage of VscH may be applied to the Y electrode by the power source VscH. That is, either the power source VscH or the combination of the capacitor CscH and the power source VscL act as a power source for supplying the voltage of VscH to the Y electrodes. In addition, when the transistor Scl is turned on, the voltage of VscL is applied to the Y electrode.

[0047] One terminal of the inductor L is coupled to a power source for supplying the reference voltage, for example a ground terminal, and the other terminal of the inductor L is coupled to the Y electrode via the transistors Yr and Yf and one input terminal of the scan circuit 410. The drain of the transistor Yr is coupled to a terminal of the inductor L, and the source of the transistor Yr is coupled to a source of the transistor Yf. The drain of the transistor Yf is coupled to the Y electrode via one input terminal of the scan circuit 410.

[0048] The drain of the transistor Ys1 is coupled to a power source for supplying the voltage of Vs, and the source of the transistor Ys1 is coupled to the Y electrode via an input terminal of the scan circuit 410. The source of the transistor Ys2 is coupled to a power source for supplying the voltage of -Vs, and the drain of the transistor Ys2 is coupled to the Y electrode via one input terminal of the scan circuit 410. The transistor Ys1 is turned on to apply the voltage of Vs to the Y electrode, and the transistor Ys2 is turned on to apply the voltage of -Vs to the Y electrode.

[0049] The source of the transistor Yfr is coupled to a power source for supplying the voltage of VscL, the drain of the transistor Yfr is coupled to an anode of the Zener diode Zd, and the cathode of the Zener diode ZD is coupled to the Y electrode via one input terminal of the scan circuit 410. Alternatively, the Zener diode ZD may be coupled between the source of the transistor Yfr and the power source. The transistor Yfr is operated to gradually decrease the voltage at the Y electrode. The breakdown voltage of the Zener diode is the difference between the voltage of Vnf and the voltage of VscL. Alternatively, the transistor Yfr may be coupled between a power source for supplying the voltage of Vnf and the Y electrode without the Zener diode ZD. In the case that the voltage of -Vs is lower than the voltage of VscL/Vnf, a current path including the power source VscL, the body diode of the transistor Yfr/YscL, the transistor Ys2, and the power source -Vs may be formed when the transistor Ys2 is turned on. To prevent this current path, a diode or a transistor may be formed in the current path.

[0050] In some embodiments, when the voltage of VscL is equal to the voltage of -Vs, the transistor YscL may be omitted. A driving circuit of the sustain electrode driver 500 includes transistors Xe and Xg.

[0051] The drain of the transistor Xe is coupled to a power source for the voltage of Ve, and the source of the transistor Xe is coupled to the X electrode. The source of the transistor Xg is coupled to a power source for supplying the reference voltage, for example the ground terminal, and the drain of the transistor Xg is coupled to the X electrode. The transistor Xe is turned on to apply the voltage of Ve to the X electrode, and the transistor Xg is turned on to apply the reference voltage to the X electrode.

[0052] In some embodiments, in order to apply the voltage of -Vs to the Y electrodes Yg1 of the first group G1 while applying the voltage of Vs to the Y electrodes Yg2 of the second group G2 in the brightness compensation period T1, the transistors Ys1 and Ys2 may be coupled to one input terminal of the scan circuits 410 for the Y electrodes Yg2 of the second group G2. In this case, additional transistors for applying the voltages of Vs and -Vs may be coupled to one input terminal of the scan circuits 410 for the Y electrodes Yg1 of the first group G1.

[0053] A method of generating the driving waveforms shown in FIG. 3 using the driving circuits of FIG. 4 will be described with reference to FIG. 5 to FIG. 8. Particularly, driving waveforms applied in the sustain period S11 will be described. Since the same driving waveforms are applied to the Y electrodes Yg1 and Yg2 of the first and second groups G1 and G2 in the sustain period S11, the driving waveform applied to one of the Y electrodes will be described.

[0054] FIG. 5 is a timing diagram of a driving waveform shown in FIG. 3, and FIG. 6 to FIG. 8 are diagrams showing operations of driving circuits shown in FIG. 4 according to timing shown in FIG. 5.

[0055] First, just before the sustain period S11, the transistor Sch is turned on such that the Y electrode is maintained at the voltage of VscH.

[0056] In a period TA1, the transistors Xe and Sch are turned off, and the transistors Yr, Scl, and Xg are turned on. Accordingly, the reference voltage is applied to the X electrode. In addition, as shown in FIG. 6, a resonance is generated between the inductor L and the panel capacitor in a current path P1 including the inductor L, the transistor Yr, the body diode of the transistor Yfr, the body diode of the transistor Scl, and the Y electrode of the panel capacitor. The voltage at the Y electrode is increased from the voltage of VscH to almost the voltage of Vs due to the resonance.

[0057] In a period TA2, the transistor Ys1 is turned on, and the transistor Yr is turned off. Accordingly, as shown in FIG. 6, a current path P2 including the power source Vs, the transistor Ys1, the transistor Scl, and the Y electrode of the panel capacitor is formed. The voltage of Vs is applied to the Y electrode through the current path P2.

[0058] In a period TA3, the transistor Ys1 is turned off, and the transistor Yf is turned on. Accordingly, as shown in FIG. 7, a resonance is generated between the inductor L and the panel capacitor in a current path P3 including the Y electrode of the panel capacitor, the transistor Scl, the transistor Yf, the transistor Yr, the inductor L, and the ground terminal. The voltage at the Y electrode is decreased from the voltage of Vs to almost the voltage of -Vs due to the resonance.

[0059] In a period TA4, the transistor Ys2 is turned on, and the transistor Yf is turned off. Accordingly, as shown in FIG. 7, a current path P4 including the Y electrode of the panel capacitor, the transistor Scl, the transistor Ys2, and the power source -Vs is formed. The voltage of -Vs is applied to the Y electrode through the current path P4.

[0060] In a period TA5, the voltage at the Y electrode is increased from the voltage of -Vs to a voltage of V1 while the reference voltage is applied to the X electrode. The voltage of V1 may be equal to the voltage of VscH to not use an additional power source for supplying the voltage of V1 and an additional transistor for transmitting the voltage of V1. In detail, during the period TA5, the transistors YscL and Sch are turned on, and the transistors Scl and Ys2 are turned off. Then, as shown in FIG. 8, a current path P5 including the power source VscL, the transistor YscL, the capacitor CscH, the transistor Sch, and the Y electrode is formed. The voltage at the Y electrode is increased to the voltage of VscH through the current path P5.
In a period TA6, the Y electrode is floated, and a voltage of V2 that is higher than the reference voltage is applied to the X electrode. The voltage of V2 may be lower than the voltage of Vs to prevent the on-cells from being discharged. Particularly, the voltage of V2 voltage may be equal to the voltage of Ve to not use an additional power source for supplying the voltage of V2 and an additional transistor for transmitting the voltage of V2.

[0061] In detail, during the period TA6, the transistor YscL is turned off, and the scan circuit 410 floats the Y electrode. The transistors Sch and Scl of the scan circuit 410 are both turned off. The transistor Xe is turned on while the Y electrode is floated. Then, the voltage at the X electrode is increased to the voltage of Ve from the reference voltage through a current path P6 including the power source Ve, the transistor Xe, and the X electrode. In addition, the voltage at the floated Y electrode is also increased by the increase of the voltage at the X electrode. That is, the voltage at the Y electrode is increased to a voltage near the reference voltage while the Y electrode is floated.

[0062] As a result, the voltage at the Y electrode is near the reference voltage without using a transistor for transmitting the reference voltage.

[0063] In a period TA7, the transistors Scl and Yfr are turned on. Accordingly, as shown in FIG. 8, a current path P7 including the Y electrode of the panel capacitor, the transistor Scl, the Zener diode ZD, the transistor Yfr, and the power source VscL is formed. The voltage at the Y electrode is gradually decreased to the voltage of Vnf through the current path P7.

[0064] As described above, according to an embodiment, after the sustain pulse is applied to the Y electrodes of the first and second groups G1 and G2 in the sustain period S11, the voltage at the Y electrode is gradually decreased to the voltage of Vnf from the voltage near the reference voltage. Therefore, although the wall charge state of the on-cells of the second group G2 becomes unstable by the sustain-discharge of the first group, it can be compensated. As a result, the address discharge can be stably generated in the address period AG2 for the second group G2. In addition, in some embodiments, the transistor for transmitting the reference voltage to the Y electrode can be omitted.

[0065] While certain inventive aspects have been described in connection with what is presently considered to be practical embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements.

Claims

1. A method of driving a plasma display including a plurality of first electrodes (Y1....Yn), a plurality of second electrodes (X1.....Xn), and a plurality of cells (110) formed by the first electrodes and the second electrodes, the method comprising:

dividing the plurality of first electrodes into a plurality of groups (G1....Gk) including a first group (G1) and a second group (G2);

addressing on-cells and off-cells with the first group of electrodes (G1) in a first address period (AG1);

sustain-discharging the on-cells of the first group (G1) in a first sustain (S11) period, wherein the sustain period (S11) is subsequent to the first address period (AG1); and

addressing on-cells and off-cells with the second group of electrodes (G2) in a second address period (AG2), wherein the second address period (AG2) is subsequent to the first sustain period (S11);

wherein sustain-discharging the on-cells of the first group (G1) comprises:

applying a first voltage (Vs) to the plurality of first electrodes (Y1....Yn) while applying a reference voltage to the plurality of second electrodes (X1....Xn) during a first period (TA2), the first voltage (Vs) being higher than the reference voltage;

applying a second voltage (-Vs) to the plurality of first electrodes (Y1....Yn) while applying the reference voltage to the plurality of second electrodes (X1....Xn) during a second period (TA4) subsequent to the first period (TA2), the second voltage (-Vs) being lower than the reference voltage;

increasing the voltage at the plurality of first electrodes (Y1....Yn) from the second voltage (-Vs) to a third voltage (V1) during a third period (TA5) subsequent to the second period (TA4), the third voltage (V1) being higher than the second voltage (-Vs);

floating the plurality of first electrodes (Y1....Yn) during a fourth period (TA6) subsequent to the third period (TA5);

applying a fourth voltage (V2) to the plurality of second electrodes (X1....Xn) while floating the plurality of first electrodes, the fourth voltage (V2) being higher than the reference voltage; and

gradually decreasing the voltage at the plurality of first electrodes (Y1....Yn) to a fifth voltage (Vnf) during a fifth period (TA7) subsequent to the fourth period (TA6), the fifth voltage (Vnf) being lower than the reference voltage.

2. The method of claim 1, wherein the voltage at the plurality of first electrodes (Y1....Yn) is increased when the fourth voltage (V2) is applied to the plurality of second electrodes (X1....Xn).

3. The method of claim 1 or 2, wherein addressing on-cells and off-cells of the first group comprises:

applying a voltage (Ve) equal to the fourth voltage to the plurality of second electrodes (X1....Xn); whilst sequentially applying a sixth voltage (VscL) to the first electrodes (Yg1) of the first group (G1) .

4. The method of any one of the preceding claims, wherein addressing on-cells and off-cells of the first group comprises:

sequentially applying a sixth voltage (VscL) to the first electrodes (Yg1) of the first group (G1); and

applying a seventh voltage (VscH) to first electrodes to which the sixth voltage is not applied, the seventh voltage (VscH) being higher than the sixth voltage (VscL),

wherein the third voltage (V1) is equal to the seventh voltage (VscH).

5. The method of any one of the preceding claims, further comprising decreasing the voltage at the plurality of first electrodes from a higher voltage to a voltage equal to the fifth voltage (Vnf) in a reset period (R1) prior to the first address period (AG1).

6. The method of any one of the preceding claims, wherein the cells of the second group (G2) are not sustain-discharged while the first voltage (Vs) and the second voltage (-Vs) are applied to the plurality of first electrodes in the first sustain period (S11).

7. The method of any one of the preceding claims, further comprising sustain-discharging the on-cells of the second group (G2) in a second sustain period (S12/S21) subsequent to the second address period (AG2).

8. The method of claim 7, further comprising sustain-discharging the on-cells of the first group (G1) while sustain-discharging the on-cells of the second group (G2) in the second sustain period (S12/S21).

9. The method of claim 8, further comprising sustain-discharging the on-cells of the second group (G2) without sustain-discharging the on-cells of the first group (G1) in a third sustain period (T2) subsequent to the second sustain period (S12/S21).

10. The method of claim 9, further comprising sustain-discharging the on-cells of the first and second groups in a fourth sustain period (T3),
wherein the fourth sustain period is subsequent to the third sustain period or is between the second sustain period and the third sustain period.

11. The method of claim 9 or 10, wherein sustain-discharging the on-cells of the second group in the third sustain period (T2) comprises:

applying the first voltage (Vs) to the first electrodes (Yg2) of the second group (G2) while applying the reference voltage to the plurality of second electrodes (X1....Xn);

applying the second voltage (-Vs) to the plurality of first electrodes (Yg2) of the second group (G2) while applying the reference voltage to the plurality of second electrodes (X1...Xn); and

applying one of the first voltage (Vs) and the second voltage (-Vs) to the first electrodes (Yg1) of the first group (G1) while applying the first voltage (Vs) and the second voltage (-Vs) to the first electrodes (Yg2) of the second group (G2) in the third sustain period (T2).

12. A plasma display comprising:

a plurality of first electrodes (Y1....Yn);

a plurality of second electrodes (X1....Xn);

a plurality of cells (110) formed near the plurality of first electrodes (Y1....Yn) and the plurality of second electrodes (X1....Xn);

a first driver (400) configured to:

increase a voltage at the plurality of first electrodes (Y1....Y2) from a first voltage (-Vs) to a second voltage (V1) during a first period (TA5),

float the plurality of first electrodes during a second period (TA6) subsequent to the first period; and

gradually decrease the voltage at the plurality of first electrodes to a third voltage (Vnf) during a third period (TA7) subsequent to the second period (TA6); and

a second driver (500) configured to:

apply a fourth voltage (0V) to the plurality of second electrodes (X1....Xn) during the first period (TA5);

apply a fifth voltage (V2) to the plurality of second electrodes (X1....Xn) during the second period (TA6); and

apply a sixth voltage (Ve) to the plurality of second electrodes (X1....Xn) during the third period (TA7), the fourth voltage (0V) being higher than the first voltage (-Vs) and the fifth voltage (V2) being higher than the fourth voltage (0V).

13. The plasma display of claim 12, wherein the fifth voltage (V2) is equal to the sixth voltage (Ve).

14. The plasma display of claim 13, wherein the first driver (400) comprises:

a plurality of scan circuits (410) respectively coupled to the plurality of first electrodes (Y1....Yn), each scan circuit (410) having a first input terminal, a second input terminal, and an output terminal coupled to a corresponding one of the plurality of first electrodes (Y1....Yn);
a first switch (Ys2) coupled between a first power source for supplying the first voltage (-Vs) and the second input terminal of the scan circuits (410);
a capacitor (CscH) and a second switch (YscL) coupled in series between a second power source (YscL) and the first input terminal of the scan circuits (410), the second voltage corresponds to a sum of a voltage (VscH-VscL) charged to the capacitor (CscH) and a voltage (VscL) supplied from the second power source; and
a third switch (Yfr) coupled between a third power source for supplying the third voltage and the second input terminals of the scan circuits, and operated to gradually decrease the voltage at the plurality of first electrodes,

and wherein the second driver (500) comprises:

a fourth switch (Xg) coupled between a fourth power source for supplying the fourth voltage and the plurality of second electrodes; and

a fifth switch (Xe) coupled between a fifth power source for supplying the fifth voltage and the plurality of second electrodes.

15. The plasma display of claim 14, wherein:

during the first period, the first switch (Ys2) is turned off, and the second switch (YscL) and the fourth switch (Xg) are turned on,

during the second period, the scan circuits (410) are operated to float the plurality of first electrodes and the fifth switch (X2) is turned on, and

during the third period, the third switch (Yfr) is turned on and the fifth switch (Xe) is turned on.

16. The plasma display of claim 12, wherein the first driver (400) is configured to alternately apply a seventh voltage and the first voltage to the plurality of first electrodes to sustain-discharge at least one cell while the second driver applies the fourth voltage to the plurality of second electrodes, the seventh voltage being higher than the fourth voltage.

17. The plasma display of claim 12, wherein the first driver (400) is configured to apply a scan pulse having a seventh voltage to at least one first electrode to select at least one on-cell among the plurality of cells, and applies the second voltage to first electrodes to which the scan pulse is not applied, the seventh voltage being lower than the second voltage.

18. The plasma display of claim 12, wherein the plurality of first electrodes are divided into a plurality of groups including a first group and a second group,
wherein the first driver (400) is configured to:

address on-cells and off-cells with the first group of electrodes in a first address period;

sustain-discharge the on-cells of the first group in a first sustain period,

wherein the sustain period is subsequent to the first address period;
address on-cells and off-cells with the second group of electrodes in a second address period, wherein the second address period is subsequent to the first sustain period; and
sustain-discharge the on-cells of the first and second groups in a second sustain period subsequent to the second address period.

19. The plasma display of claim 12, wherein the first period is subsequent to sustain-discharging the on-cells of the first group in a first sustain period.

Drawing