(19)
(11) EP 2 148 319 A8

(12) CORRECTED EUROPEAN PATENT APPLICATION
published in accordance with Art. 153(4) EPC

(15) Correction information:
Corrected version no 1 (W1 A1)

(48) Corrigendum issued on:
15.06.2011 Bulletin 2011/24

(43) Date of publication:
27.01.2010 Bulletin 2010/04

(21) Application number: 08738625.6

(22) Date of filing: 22.04.2008
(51) International Patent Classification (IPC): 
G09G 3/36(2006.01)
G02F 1/1337(2006.01)
G02F 1/133(2006.01)
G09G 3/20(2006.01)
(86) International application number:
PCT/JP2008/001055
(87) International publication number:
WO 2008/139695 (20.11.2008 Gazette 2008/47)
(84) Designated Contracting States:
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MT NL NO PL PT RO SE SI SK TR

(30) Priority: 27.04.2007 JP 2007119169

(71) Applicant: Sharp Kabushiki Kaisha
Osaka-shi, Osaka 545-8522 (JP)

(72) Inventors:
  • IRIE, Kentaro
    Osaka-shi, Osaka 545-8522 (JP)
  • KITAYAMA, Masae
    Osaka-shi, Osaka 545-8522 (JP)
  • SHIMOSHIKIRYOH, Fumikazu
    Osaka-shi, Osaka 545-8522 (JP)
  • TSUBATA, Toshihide
    Osaka-shi, Osaka 545-8522 (JP)
  • YAMADA, Naoshi
    Osaka-shi, Osaka 545-8522 (JP)

(74) Representative: Zinke, Thomas 
Müller Hoffmann & Partner Patentanwälte Innere Wiener Straße 17
81667 München
81667 München (DE)


(56) References cited: : 
   
       


    (54) LIQUID CRYSTAL DISPLAY DEVICE


    (57) In a liquid crystal display device according to the present invention, when the polarities of the source signal voltages do not change over a plurality of horizontal scanning periods, the image write pulse of the gate signal supplied to a gate bus line that corresponds to pixels along the jth row rises before the source signal voltages change to values that correspond to pixels along the jth row. Next, the image write pulse of the gate signal supplied to a gate bus line that corresponds to pixels along the jth row falls, and then the image write pulse of the gate signal supplied to a gate bus line that corresponds to pixels along the kth row (j≠k) rises. The polarities of the storage capacitor signal voltages applied to storage capacitor bus lines that correspond to sub-pixels of pixels along the jth row are inverted after the image write pulse of the gate signal supplied to a gate bus line that corresponds to pixels along the kth row rises.