(19)
(11) EP 2 171 847 B8

(12) CORRECTED EUROPEAN PATENT SPECIFICATION
Note: Bibliography reflects the latest situation

(15) Correction information:
Corrected version no 1 (W1 B1)

(48) Corrigendum issued on:
08.02.2012 Bulletin 2012/06

(45) Mention of the grant of the patent:
10.08.2011 Bulletin 2011/32

(21) Application number: 08738033.3

(22) Date of filing: 30.04.2008
(51) International Patent Classification (IPC): 
H03K 19/00(2006.01)
(86) International application number:
PCT/IB2008/051671
(87) International publication number:
WO 2008/135914 (13.11.2008 Gazette 2008/46)

(54)

MULTIVALUED LOGIC CIRCUIT

MEHRWERTIGE LOGIKSCHALTUNG

CIRCUIT LOGIQUE MULTIVALUÉ

(84) Designated Contracting States:
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MT NL NO PL PT RO SE SI SK TR

(30) Priority: 10.05.2007 RU 2007117392

(43) Date of publication of application:
07.04.2010 Bulletin 2010/14

(73) Proprietor: Fuzzy Chip Pte. Ltd
Singapore 609916 (SG)

(72) Inventor:
  • OLEXENKO, Viktor, Viktorovich
    690080 Vladivostok (RU)

(74) Representative: Äkräs, Tapio Juhani 
Kolster Oy Ab Iso Roobertinkatu 23 P.O. Box 148
00121 Helsinki
00121 Helsinki (FI)


(56) References cited: : 
RU-C1- 2 176 850
US-A- 4 814 644
 US-A- 4 229 803
US-A1- 2005 093 629
   
  • CURRENT K W: "CURRENT-MODE CMOS QUATERNARY THRESHOLD LOGIC FULL ADDER CIRCUIT" INTERNATIONAL JOURNAL OF ELECTRONICS, TAYLOR AND FRANCIS.LTD. LONDON, GB, vol. 74, no. 4, 1 April 1993 (1993-04-01), pages 587-591, XP000365264 ISSN: 0020-7217
   
Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).