(19)
(11) EP 2 175 487 B8

(12) CORRECTED EUROPEAN PATENT SPECIFICATION
Note: Bibliography reflects the latest situation

(15) Correction information:
Corrected version no 1 (W1 B1)

(48) Corrigendum issued on:
06.05.2015 Bulletin 2015/19

(45) Mention of the grant of the patent:
11.03.2015 Bulletin 2015/11

(21) Application number: 10000804.4

(22) Date of filing: 24.07.2003
(51) International Patent Classification (IPC): 
H01L 23/522(2006.01)
H01L 23/528(2006.01)
 H01L 23/532(2006.01)

(54)

Semiconductor device

Halbleitervorrichtung

Dispositif à semi-conducteur

(84) Designated Contracting States:
DE FR IT

(30) Priority: 31.07.2002 JP 2002223343

(43) Date of publication of application:
14.04.2010 Bulletin 2010/15

(60) Divisional application:
15150440.4 / 2863430
15150443.8 / 2863431

(62) Application number of the earlier application in accordance with Art. 76 EPC:
03016553.4 / 1387404

(73) Proprietor: Fujitsu Semiconductor Limited
Kohoku-ku, Yokohama-shi Kanagawa 222-0033 (JP)

(72) Inventor:
  • Watanabe, Kenichi
    Kanagawa 211-8588 (JP)

(74) Representative: Hoffmann Eitle 
Patent- und Rechtsanwälte PartmbB Arabellastraße 30
81925 München
81925 München (DE)


(56) References cited: : 
JP-A- 3 089 548
JP-A- 11 054 705
 JP-A- 5 175 198
JP-A- 2000 124 403
   
  • WADA J ET AL: "Low resistance dual damascene process by new Al reflow using Nb liner", VLSI TECHNOLOGY, 1998. DIGEST OF TECHNICAL PAPERS. 1998 SYMPOSIUM ON HONOLULU, HI, USA 9-11 JUNE 1998, NEW YORK, NY, USA,IEEE, US, 9 June 1998 (1998-06-09), pages 48-49, XP010291151, DOI: DOI:10.1109/VLSIT.1998.689194 ISBN: 978-0-7803-4770-0
   
Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).