LEVEL SHIFTER HAVING LOW DUTY CYCLE DISTORTION

Description

BACKGROUND INFORMATION

Technical Field

[0001] The disclosed embodiments relate to level shifting circuits, and more particularly relate to high speed level shifting circuits that exhibit both low duty cycle distortion and high supply voltage margin.

Background Information

[0002] Digital logic circuits can be powered from different supply voltages. In one example, an integrated circuit includes a first digital logic block that operates with a first supply voltage as well as a second digital logic block that operates with a second supply voltage. If a digital signal is to pass form one logic block to the other, the digital levels of the signal must be shifted. A circuit referred to as a level shifter is sometimes used to perform this level shifting function.

[0003] Figure 1 (Prior Art) is a circuit diagram of a conventional level shifter 1. The label VDDL designates a first supply voltage (for example, 1.2 volts) whereas the label VDDH designates a second supply voltage (for example, 1.8 volts). If a digital input signal IN on input node 2 transitions from a digital low logic level (for example, ground potential or approximately ground potential) to a digital high logic level (for example, VDDL or approximately VDDL), then inverter 3 causes the signal on node 4 to transition low, and inverter 5 causes the signal on node 6 to transition high (to VDDL), and inverter 7 causes the signal on node 8 to transition low (to ground potential). The signal on node 6 transitioning to VDDL causes thick-gate insulator N-channel transistor 9 to turn on. The signal on node 8 transitioning to ground potential causes thick-gate insulator N-channel transistor 10 to turn off. Transistor 9 being turned on pulls the voltage on node 11 down to ground potential, and therefore causes thick-gate insulator P-channel transistor 12 to turn on. Transistor 10 being turned off allows conductive transistor 12 to pull the voltage on node 13 up toward the second supply voltage VDDH. The high voltage on node 13 causes thick-gate insulator P-channel transistor 14 to be turned off. It is therefore seen that the low-to-high transition from ground potential to VDDL on input node 2 is shifted into a low-to-high transition from ground potential to VDDH on node 13. The digital signal on node 13 passes through two inverters 15 and 16 in this example and is then buffered by yet another buffer 17 before the signal on node 18 is used by the second digital logic block that operates with the second supply voltage VDDH.

[0004] The level shifting circuit of Figure 1 works well in many applications, but as signal speeds increase, the level shifting circuit is seen to introduce an undesirable amount of duty cycle distortion skew into the signal. A low-to-high signal transition has a first propagation delay (TPD_LH) through the circuit whereas a high-to-low signal transition has a second propagation delay (TDP_HL) through the circuit. The high-to-low propagation delay time is significantly affected by how fast N-channel transistor 10 can pull the voltage on node 13 down and switch the signal on node 13. The low-to-high propagation delay time is significantly affected by how fast P-channel transistor 12 can pull the voltage on node 13 up and switch the signal on node 13. The sizes of transistors 10 and 12 can be adjusted so that there is little or no skew at a certain set of operating voltage, process and temperature conditions. Unfortunately, as the operating voltages, process and temperature of the circuit vary, the low-to-high and high-to-low propagation delay times differ from one another.

[0005] In one example, a level shifter circuit is desired that will conduct 400 MHz digital signals. If, for example, the signal being level shifted is a data signal being communicated from a transmitter circuit to a receiver circuit synchronously with a clock signal, and if the time that the signal arrives at the receiver varies, then the rate at which the clock signal can be clocked is reduced. The clock signal cannot transition to clock data into the receiver until the data has been received at the receiver. In the 400 MHz signal application, a circuit specification requires that if a square wave is supplied as an input to the level shifting circuit, then the level shifted signal that is output from the circuit must have a duty cycle of no less than thirty percent and must have a duty cycle of no more than seventy percent over all permutations of voltage, process and temperature corners. Unfortunately, the circuit of Figure 1 can have a duty cycle distortion greater than this.

[0006] Figure 2 is a waveform diagram that illustrates how a 50/50 duty cycle 400 MHz input signal IN that is input to the circuit of Figure 1 is level shifted into an output signal OUT that has an 80/20 duty cycle. This is more duty cycle distortion than is allowed by the circuit specification. An improved circuit is desired.

[0007] The document US 2006/0066 349 shows an example of level shift circuit having adjustment circuit for maintaining duty ratio.

SUMMARY

[0008] A novel level shifter circuit receives a digital input signal IN that transitions within a first signal voltage range (for example, from ground potential to a first supply voltage VDDL of approximately 1.2 volts) and translates the signal IN into a digital output signal OUT that transitions within a second voltage range (for example, from the ground potential to a second supply voltage VDDH of approximately 1.8 volts). The level shifter circuit includes an inverting circuit, a cross-coupled level shifting latch, and a SR logic gate latch.

[0009] According to the invention a level shifter circuit is provided as claimed in claim 1.

[0010] In operation, a low-to-high transition of the digital input signal IN causes the cross-coupled level shifting latch to be set into a first state which in turn causes the cross-coupled level shifting latch to output a high signal onto one of its differential output nodes. The high signal resets the SR latch such that the digital signal OUT transitions from a digital logic low to a digital logic high. A high-to-low transition of the digital input signal IN causes the cross-coupled level shifting latch to be set into a second state which in turn causes the cross-coupled level shifting latch to output a high signal onto the other of its differential output nodes. The high signal sets the SR latch such that the digital signal OUT transitions from a digital logic low to a digital logic high.

[0011] The propagation delay through the level shifter circuit for a low-to-high transition of the input signal IN is matched to the propagation delay through the level shifter circuit for a high-to-low transition of the input signal IN.

[0012] In the invention, the duty cycle distortion skew is less than 50 picoseconds over operating voltage, process and operating temperature corners, when the level shifter circuit has a supply voltage margin of more than one quarter of a nominal 1.2 volt value of the first supply voltage VDDL. Due to the architecture of the level shifter circuit, the low duty cycle distortion skew is achieved without having to balance operating characteristics of the P-channel and an N-channel transistors within the cross-coupled level shifting latch. Because P-channel and N-channel transistors within the cross-coupled level shifting latch do not have to be balanced, the size of the N-channel transistors can be increased relative to the P-channel transistors, thereby increasing the supply voltage margin of the level shifter circuit.

[0013] The foregoing is a summary and thus contains, by necessity, simplifications, generalizations and omissions of detail; consequently, those skilled in the art will appreciate that the summary is illustrative only and does not purport to be limiting in any way. Other aspects, inventive features, and advantages of the devices and/or processes described herein, as defined solely by the claims, will become apparent in the non-limiting detailed description set forth herein.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] 

Figure 1 (Prior Art) is a diagram of a prior art level shifter circuit.

Figure 2 (Prior Art) is a waveform diagram that illustrates duty cycle distortion introduced by the prior art level shifter circuit of Figure 1.

Figure 3 is a circuit diagram of a novel level shifter circuit 100 in accordance with one novel aspect.

Figure 4 is a circuit diagram that illustrates operation of the novel level shifter circuit 100 of Figure 3 when a low-to-high transition of an input signal propagates through the level shifter circuit.

Figure 5 is a circuit diagram that illustrates operation of the novel level shifter circuit 100 of Figure 3 when a high-to-low transition of an input signal propagates through the level shifter circuit.

Figure 6 is a diagram that compares the skew of the novel level shifter circuit 100 of Figure 3 to the prior art level shifter circuit 1 of Figure 1 over sixteen different voltage, process and temperature operating corners.

Figure 7 is a diagram that illustrates the supply voltage margin of the novel level shifter circuit 100 of Figure 3 and the prior art level shifter circuit 1 of Figure 1.

Figure 8 is a flowchart diagram of a method in accordance with one novel aspect.

DETAILED DESCRIPTION

[0015] Figure 3 is a simplified diagram of a level shifting circuit 100 in accordance with one novel aspect. Level shifting circuit 100 includes an input node 101, a cross-coupled level shifting latch 102, a set-reset (SR) logic gate latch 103, an inverting circuit 104, an inverter 105, a buffer 106, and an output node 107. A digital input signal IN is received onto input node 101 and is level shifted and output as a digital output signal OUT onto output node 107. Digital input signal IN transitions within a first signal voltage range (for example, from ground potential to a VDDL voltage of approximately 1.2 volts). Digital output signal OUT transitions within a second signal voltage range (for example, from the ground potential to a VDDH voltage of approximately 1.8 volts). Level shifting circuit 100 is realized in complementary logic involving P-channel and N-channel field effect transistors.

[0016] Inverting circuit 104 includes a non-inverting digital logic circuit 108 and an inverting digital logic circuit 109. Non-inverting digital logic circuit 108 includes two inverters 125 and 126. Inverting digital logic circuit 109 is a single inverter 127. Inverting circuit 104 is powered by a first power supply voltage VDDL (for example, 1.2 volts). Inverting circuit 104 supplies an inverted version of input signal IN onto node 110 as signal INB. The "B" in the signal name INB indicates "bar". Inverting circuit 104 also supplies a non-inverted version of input signal IN onto node 111 as signal IND. The "D" in the signal name IND indicates "delayed".

[0017] Cross coupled level shifting latch 102 includes a first input node 112, a second input node 113, a first differential output node 114, a second differential output node 115, two thick-gate insulator N-channel transistors 116 and 117, and two thick-gate insulator P-channel transistors 118 and 119. The cross-coupled level shifting latch 102 is powered by a second power supply voltage VDDH (for example, 1.8 volts).

[0018] SR logic gate latch 103 is also powered by the second power supply voltage VDDH. SR logic gate latch 103 includes a set (S) input node 121, a reset (R) input node 120, an output node 122, a first NOR gate 123 and a second NOR gate 124. The term "differential" here does not mean that information is necessarily communicated as a voltage difference between two signals, but rather includes a situation in which two signals are used to control a receiver circuit such as the SR logic gate latch 103: one to cause the SR logic gate latch to be set, and another to cause the SR logic gate latch to be reset.

[0019] Figure 4 illustrates an operation of level shifting circuit 100 when the input signal IN on input node 101 transitions from a digital low logic level (for example, ground potential or close to ground potential) to a digital high logic level (for example, supply voltage VDDL or close to VDDL). Initially, a digital logic low is present on input node 101. The signal on node 111 is therefore a digital logic low and the signal on node 110 is a digital logic high. The digital logic low on node 111 causes N-channel transistor 116 to be nonconductive and the digital logic high on node 110 causes N-channel transistor 117 to be conductive. P-channel transistor 119 is therefore nonconductive and P-channel transistor 118 is conductive. N-channel transistor 116 being nonconductive and P-channel transistor 118 being conductive causes a digital logic high to be present on node 128. N-channel transistor 117 being conductive and P-channel transistor 119 being nonconductive causes a digital logic low to be present on node 129. Because a digital logic high is present on node 128, a digital logic high is present on the lower input lead of NOR gate 124. NOR gate 124 therefore outputs a digital logic low signal onto the lower input lead of NOR gate 123. Because digital logic low signals are present on both input leads of NOR gate 123, NOR gate 123 outputs a digital logic high signal. The signal OUT on output node 107 is therefore a digital logic low. Because the input signal IN being a digital logic low causes the output signal OUT to be a digital logic low, the level shifter 100 is a noninverting level shifter circuit.

[0020] The transition of the input signal IN to a digital logic high causes the signal on node 111 to transition high and causes the signal on node 110 to transition low. N-channel transistor 116 is made conductive as indicated by the notation "ON" in Figure 4. N-channel transistor 116 couples node 128 to ground node 130. N-channel transistor 117 is made nonconductive. The cross-coupled shifting latch 102 therefore switches, and P-channel transistor 119 is made conductive. P-channel transistor 119 couples node 129 to supply voltage node 131. The signal on node 129 therefore transitions to a digital logic high. The digital logic high on the upper input lead of NOR gate 123 causes NOR gate 123 to output a digital logic low signal. Because a digital logic low signal is now present on the lower input lead of NOR gate 124, digital logic low signals are present on both input leads of NOR gate 124. The state of SR logic gate latch therefore switches. The SR latch 103, that is now outputting a digital logic low onto output node 122, is said to have been "RESET". Because the signal on output node 122 transitions to a digital logic low, the signal OUT on output node 107 transitions to a digital logic high. The signal path through the circuit is illustrated by the heavy arrow in Figure 4. In this operation, the SR latch 103 is "RESET" due to the digital logic high signal that is output onto second differential output lead 115 (see Figure 3) of the cross-coupled level shifting latch 102.

[0021] Figure 5 illustrates operation of level shifting circuit 100 when the input signal IN on input node 101 transitions back from a digital logic high to a digital logic low. The transition on input node 101 causes the signal on node 110 to transition to a digital logic high, which in turn causes N-channel transistor 117 to be made conductive. N-channel transistor 117 being conductive is indicated by the "ON" notation in Figure 5. N-channel transistor 117 couples node 129 to ground node 130 such that the voltage on node 129 transitions to a digital logic low. The signal on node 111 also transitions to a digital logic low, which in turn causes N-channel transistor 116 to be made nonconductive. The digital logic low signal on node 129 causes P-channel transistor 118 to be made conductive. P-channel transistor 118 being conductive couples node 128 to supply voltage node 131. The signal on node 128 therefore transitions to a digital logic high. Accordingly, cross-coupled level shifting latch 102 has switched states. A digital logic high is now present on the first differential output node 114 of the latch 102. The digital logic high signal on the set "S" input lead 121 of SR logic gate latch 103 causes NOR gate 124 to output a digital logic low signal. Because digital logic low signals are present on both input leads of NOR gate 123, the signal on the output lead of NOR gate 123 transitions to a digital logic high. SR logic gate latch 103 is therefore seen to have switched states. Because the signal on the output lead of NOR gate 123 transitions to a digital logic high, the SR logic gate latch 103 is set to have been 'SET". The setting of SR logic gate latch 103 causes the signal OUT on output node 107 to transition to a digital logic low. The signal path through the circuit is illustrated by the heavy arrow in Figure 5.

[0022] The transistors of cross-coupled level shifting latch 100 are sized such that the low-to-high transition of the signal on each of the nodes 128 and 129 (the first and second differential output nodes of the cross-coupled level shifting latch 102) is slower than its high-to-low transition. Because SR latch 103 is either set or reset by a digital logic high signal, the high-to-low propagation through the SR latch is made to be faster than the low-to-high propagation through the SR latch so that both the set and reset input nodes of the SR latch will not experience simultaneous digital logic high signals. The signal begins to propagate through the SR latch 103 when a low-to-high transition on one of the differential output nodes of the cross-coupled level shifting latch 102 occurs.

[0023] It is desired that the propagation delays of the paths illustrated in Figures 4 and 5 be as close to one another as possible under all permutations of voltage, process and temperature corners. Note that in the arrow of Figure 4, the signal passes through two inverters 125 and 126, an N-channel pulldown transistor 116 of latch 102, a P-channel pullup transistor 119 of latch 102, a NOR gate 123, and then the inverter 105 and buffer 106. In the arrow of Figure 5, the signal passes through one inverter 127, an N-channel pulldown transistor 117 of latch 102, a P-channel pullup transistor 118 of latch 102, two NOR gates 124 and 123 of latch 103, and then the inverter 105 and buffer 106. It is therefore seen that the arrow of Figure 5 passes through one more NOR gate than the arrow of Figure 4, but passes through one less inverter. Accordingly, to match the low-to-high and high-to-low propagation delays of the circuit, the propagation delay of NOR gate 124 is made to be substantially equal to the propagation delay through inverter 125.

[0024] In the prior art level shifter 1 of Figure 1, a low-to-high transition of the input signal IN results in N-channel transistor 10 being made nonconductive and P-channel transistor 12 being made conductive. The rate at which the voltage on node 13 transitions high therefore depends upon the ability of P-channel transistor 12 to pull the voltage on node 13 up to supply voltage VDDH. In contrast, a high-to-low transition of the input signal IN results in N-channel transistor 10 being made conductive and P-channel transistor 12 being made nonconductive. The rate at which the voltage on node 13 transitions low therefore depends upon the ability of N-channel transistor 12 to pull the voltage on node 13 down to ground potential. Making the low-to-high propagation delay through the overall circuit 1 equal to the high-to-low propagation delay through the overall circuit 1 therefore typically involves balancing the abilities of two different types of transistors (P-channel and N-channel) to switch the voltage on node 13. This is due to the cross-coupled level shifting latch driving the signal to the following output circuitry in a single-ended fashion. Due to the differences in electron and hole mobilities, the P-channel transistor is typically made to be approximately twice as large as its associated N-channel transistor so that the drive strength of the N-channel and P-channel transistors will be balanced where low duty cycle distortion is desired.

[0025] In the novel circuit of Figure 3, on the other hand, cross-coupled level shifting latch 102 drives the following output circuitry in a double-ended fashion. In the circuit of Figure 3, a low-to-high transition of the input signal IN results in N-channel transistor 116 being made conductive and P-channel transistor 119 being conductive. P-channel transistor 119 being conductive is what pulls the voltage on node 129 to a digital logic high and causes the reset signal to be output onto the reset "R" input lead 120 of the SR latch 103. The rate at which the voltage on node 129 transitions to a digital logic high is therefore dependent upon the ability of a P-channel transistor 119 to turn on and the ability of an N-channel transistor 117 to be turned off. A high-to-low transition of the input signal IN results in N-channel transistor 117 being made conductive and P-channel transistor 118 being made conductive and N-channel transistor 116 being made nonconductive. P-channel transistor 118 being conductive is what pulls the voltage on node 128 to a digital logic high and causes the set signal to be output onto the set "S" input lead 121 of the SR latch 103. The rate at which the voltage on node 128 transitions to a digital logic high is therefore dependent upon the ability of a P-channel transistor 118 to turn on and the ability of an N-channel transistor 116 to be turned off. Accordingly, for both a low-to-high transition and for a high-to-low transition of the input signal IN, the rate at which cross-coupled level shifting latch 102 outputs an active high set or reset signal depends on the rate at which an N-channel transistor can turn off and the rate at which an associated P-channel transistor can turn on. Making the low-to-high propagation delay through the overall circuit 100 equal to the high-to-low propagation delay through the overall circuit 100 therefore does not involve balancing the abilities of two different types of transistors (thick-gate P-channel versus thick-gate N-channel) to switch the voltage on a node. The different effects that voltage, process and temperature have on P-channel versus N-channel transistors that led to duty cycle distortion in the prior art circuit of Figure 1 therefore do not affect the novel level shifter circuit 100 of Figure 3.

[0026] The prior art circuit of Figure 1 also suffers from another problem. It is often desired that the level shifter circuit 1 continue to operate at low values of a supply voltage such as VDDL. This is referred to as "supply voltage margin". As the value of supply voltage VDDL is reduced, the maximum voltage that inverter 7 can drive the gate of N-channel transistor 10 decreases. Driving the gate of N-channel transistor 10 with lower and lower voltages under the condition when transistor 10 is to be made conductive results in this transistor only being partially on or weakly conductive. Further decreases in the supply voltage VDDL fail to allow N-channel transistor 10 to turn on adequately for the cross-coupled latch to switch. The level shifter circuit therefore stops working. Increasing the size of N-channel transistor 10 increases the amount of current the N-channel transistor 10 will conduct at a given gate drive voltage. Consequently, increasing the size of N-channel transistor 10 serves to improve the supply voltage margin. If, however, the turn on and turn off and conduction characteristics of the N-channel and P-channel transistors of the cross-coupled level shifting latch of Figure 1 are to be balanced to minimize duty cycle distortion as set forth above, then the size of the N-channel transistor 10 cannot be increased without adversely affecting duty cycle distortion. Improving supply voltage margin increases duty cycle distortion, and improving duty cycle distortion decreased supply voltage margin.

[0027] In the novel circuit of Figure 3, on the other hand, the turn on and turn off and conduction characteristics of the N-channel and P-channel transistors 117 and 119 do not need to be balanced. Similarly, the turn on and turn off and conduction characteristics of the N-channel and P-channel transistors 116 and 118 do not need to be balanced. The channel widths of the N-channel transistors 116 and 117 are therefore increased and supply voltage margin is improved as compared to the supply voltage margin of the prior art circuit of Figure 1. In one example, the channel width of N-channel transistor 117 is larger than the channel width of P-channel transistor 119, and the channel width of N-channel transistor 116 is larger than the channel width of P-channel transistor 118.

[0028] Figure 6 is a diagram that illustrates the skew of the novel level shifter circuit 100 of Figure 3 in comparison to the skew of the prior art level shifter circuit 1 of Figure 1. Skew is the difference in time (picoseconds) between the propagation delay through the circuit for a low-to-high input signal IN and the propagation delay through the circuit for a high-to-low input signal IN. For each of the variables of operating supply voltage(s), process, and operating temperature, there is a minimum permissible value and a maximum permissible value. These are commonly referred to as "corners". Accordingly, there are sixteen different permutations of the high and low values of the three variables. In the example of Figure 6, the temperature has a minimum of minus 40 degrees Celsius and a maximum of 125 degrees Celsius. VDDL has a minimum of 1.08 volts and a maximum of 1.45 volts (at least plus or minus ten percent). VDDH has a minimum of 1.6 volts and a maximum of 2.0 volts (at least plus or minus ten percent). The process is characterized as being "slow" to "fast". The skew at each of the sixteen permutations is indicated in Figure 6. For the permutation 1, for example, the prior art level shifter of Figure 1 has a skew of approximately 130 picoseconds, whereas the novel level shifter circuit 100 of Figure 3 has a skew of less than 50 picoseconds over all sixteen operating corners.

[0029] Figure 7 is a diagram that illustrates the supply voltage margin of the novel level shifter circuit 100 of Figure 3 in comparison to the skew of the prior art level shifter circuit 1 of Figure 1. Consider the line 200. Line 200 represents operation of the prior art level shifter of Figure 1. As the magnitude of the supply voltage VDDL is reduced, the duty cycle is fairly constant as indicated by the horizontal orientation of line 200 from 1.2 volts VDDL down to approximately 0.95 volts VDDL. Then for VDDL voltages below approximately 0.95 volts the duty cycle starts to change (duty cycle distortion increases). At point 201, duty cycle distortion is very high, but the level shifter circuit 1 is still transferring the input signal IN to the output node. For supply voltages below approximately 0.95 volts, however, the duty cycle is seen to fall to zero. The prior art level shifter has ceased operating. The supply voltage margin is therefore the nominal supply voltage VDDL value of 1.2 volts minus 0.95 volts, or approximately 0.25 volts. Next, consider the line 202 that represents operation of the novel level shifter of Figure 3. The supply voltage VDDL can be reduced down to approximately 0.83 volts before duty cycle distortion is seen to increase quickly. The novel level shifter circuit 100 of Figure 3 continues to operate down to supply voltages VDDL of approximately 0.81 volts. The novel level shifter 100 of Figure 3 is therefore said to have a supply voltage margin of 1.2 volts minus 0.81 volts or 0.39 volts. A supply voltage margin of 0.39 volts is a substantial improvement over the prior art circuit of Figure 1 which exhibits a supply voltage margin of approximately 0.25 volts. The supply voltage margin of 0.39 volts is approximately one third (more than one quarter) of the nominal 1.2 volt supply voltage.

[0030] As illustrated in Figure 6, the specific embodiment of the novel level shifter circuit 100 of Figure 6 has a skew of less than 50 picoseconds over all sixteen process, operating voltage and operating temperature corners, and it accomplishes this while being able to operate down to a supply voltage of approximately 0.81 volts. The channel width of the N-channel transistor of the P-channel and N-channel transistor pair that drives each of the differential output nodes of the cross-coupled latch 102 is at least as large as the channel width of the associated P-channel transistor of the pair.

[0031] Figure 8 is a flowchart diagram of a method 300 in accordance with one novel aspect. In step 301, a digital input signal is received and inverted and noninverted versions of the digital input signal are output. In one example, inverting circuit 104 of Figure 3 performs this step. In step 302, the non-inverted version is received onto a first input node of a cross-coupled level shifting latch and the inverted version is received onto a second input node of the cross-coupled level shifting latch. In one example, the cross-coupled level shifting latch is cross-coupled level shifting latch 102 of Figure 3. In step 303, a first differential output signal of the cross-coupled level shifting latch is received onto a first input node of an SR logic gate latch, and a second differential output signal of the cross-coupled level shifting latch is received onto a second input node of the SR logic gate latch. In one example, the SR logic gate latch is SR logic gate latch 103 of Figure 3. The SR logic gate latch outputs a level shifted digital output signal (a level shifted version of the digital input signal).

[0032] Although certain specific embodiments are described above for instructional purposes, the teachings of this patent document have general applicability and are not limited to the specific embodiments described above. In the description above, two nodes are said to be "coupled" together when they are directly connected by conductors such that the two nodes are actually a single substantially unipotential node. Although a 400 MHz digital input signal is described as being successfully level shifted by the novel level shifting circuit of Figure 3 with low duty cycle distortion skew, it is to be understood that this frequency of input signal is only used as an example. The circuit of Figure 3 operates at frequencies higher than 400 MHz. Accordingly, various modifications, adaptations, and combinations of the various features of the described specific embodiments can be practiced without departing from the scope of the claims that are set forth below.

Claims

1. A level shifter circuit comprising:

a cross-coupled level shifting latch (102) having a first input node (112), a second input node (113), a first differential output node (114) and a second differential output node (115);

a set-reset (SR) logic gate latch (103) comprising a first NOR gate (123) and second NOR gate (124) and having a reset input node (120), a set input node (121), and a single output node (122), wherein the reset input node (120) is coupled to the second differential output node (129) of the cross-coupled level shifting latch, and wherein the set input node (121) is coupled to the first differential output node (128) of the cross-coupled level shifting latch; and

an inverting circuit (104) having an input node (101) that receives a digital signal and supplies a delayed version of the digital signal onto the first input node (1 12) of the cross-coupled level shifting latch, and that supplies an inverted version of the digital signal onto the second input node (113) of the cross-coupled level shifting latch, wherein the inverting circuit comprises:

a non-inverting digital logic circuit (108) comprising a first inverter (125) and second inverter (126) having the input node (101) and an output node (111), wherein the output node (111) is coupled to the first input node of the cross-coupled level shifting latch the non-inverting digital logic circuit arranged to provide the delayed version of the digital signal; and

an inverting digital logic circuit (109) having the input node (101) and an output node (110), wherein the input node (101) of the inverting digital logic circuit is the input node (101) of the non-inverting digital logic circuit, wherein the output node (110) is the second input node of the cross-coupled level shifting latch;

wherein the propagation delay of the second NOR gate (124) being connected to the set input node (121) of the set-reset logic gate latch is substantially equal to the propagation delay of the first inverter (125) of the non-inverting digital logic circuit, whereby a propagation delay of a signal passing through the non-inverting digital logic (108) circuit to the output node of the set-reset (SR) logic gate latch is matched to a propagation delay of a signal passing through the inverting digital logic circuit (109) to the output node of the SR logic gate latch.

2. The level shifter circuit of Claim 1, wherein the cross-coupled level shifting latch comprises:

a supply voltage node,

a first P-channel field effect transistor (PFET) having a source, a drain and a gate, wherein the source is coupled to the supply voltage node, and wherein the drain is coupled to the set input node (121) of the set-reset (SR) logic gate latch (103), and wherein the gate is coupled to the second differential output node;

a second P-channel field effect transistor having a source, a drain and a gate, wherein the source is coupled to the supply voltage node, and wherein the drain is coupled to the reset input node of the SR logic gate latch, and wherein the gate is coupled to the first differential output node;

a ground node;

a first N-channel field effect transistor having a source, a drain and a gate, wherein the source is coupled to the ground node, wherein the drain is coupled to the drain of the first PFET, and wherein the gate is the first input node of the cross-coupled level shifting latch; and

a second N-channel field effect transistor having a source, a drain and a gate, wherein the source is coupled to the ground node, wherein the drain is coupled to the drain of the second P-channel field effect transistor, and wherein the gate is the second input node of the cross-coupled level shifting latch.

3. The level shifter circuit of Claim 1, wherein the SR logic gate latch comprises:

a first NOR gate having a first input node, a second input node, and an output node, wherein the first input node is the reset input node of the SR logic gate latch, and wherein the output node is the output node of the SR logic gate latch; and

a second NOR gate having a first input node, a second input node, and an output node, wherein the first input node is the set input node of the SR logic gate latch, wherein the second input node is the output node of the first NOR gate, and wherein the output node is the second input node of the first NOR gate.

4. The level shifter circuit of Claim 3, wherein a first signal passing through the non-inverting digital logic circuit from the input node of the non-inverting digital logic circuit to the output node of the non-inverting digital logic circuit has a first propagation delay, wherein a second signal passing through the inverting digital logic circuit from the input node of the inverting digital logic circuit to the output node of the inverting digital logic circuit has a second propagation delay, and wherein the second propagation delay is shorter than the first propagation delay.

5. The level shifter circuit of Claim 2, wherein the first N-channel field effect transistor (116) has a channel width, wherein the first P-channel field effect transistor (118) has a channel width, and wherein the channel width of the first N-channel field effect transistor (116) is larger than the channel width of the first P-channel field effect transistor (118).

6. The level shifter circuit of Claim 1, wherein the inverting circuit is powered from a supply voltage, and wherein the level shifter circuit has a duty cycle distortion skew of less than fifty picoseconds over a semiconductor processing variation range, over a 165 degree Celsius operating temperature range, and over a plus or minus ten percent range of the supply voltage.

7. The level shifter circuit of Claim 5, wherein the level shifter circuit has a duty cycle distortion skew of less than fifty picoseconds when the level shifter circuit is receiving an input signal of four hundred megahertz and outputting an output signal of four hundred megahertz, wherein the inverting circuit is powered by a first supply voltage, wherein the cross-coupled level shifting latch and the SR logic gate latch are powered by a second supply voltage, and wherein the level shifter circuit has the duty cycle distortion skew of less than fifty picoseconds over conditions of the first supply voltage varying plus or minus ten percent, and over conditions of the second supply voltage varying plus or minus ten percent, and wherein the level shifter circuit has the duty cycle distortion skew of less than fifty picoseconds over a 165 degree Celsius temperature range.

Ansprüche

1. Pegelumsetzerschaltung, die Folgendes umfasst:

einen kreuzgekoppelten Pegelumsetz-Latch (102) mit einem ersten Eingangsknoten (112), einem zweiten Eingangsknoten (113), einem ersten Differentialausgangsknoten (114) und einem zweiten Differentialausgangsknoten (115);

einen SR-(Set-Reset)-Logikgatter-Latch (103), der ein erstes NOR-Gatter (123) und ein zweites NOR-Gatter (124) umfasst und einen Reset-Eingangsknoten (120), einen Set-Eingangsknoten (121) sowie einen einzelnen Ausgangsknoten (122) aufweist, wobei der Reset-Eingangsknoten (120) mit dem zweiten Differentialausgangsknoten (129) des kreuzgekoppelten Pegelumsetz-Latch gekoppelt ist und wobei der Set-Eingangsknoten (121) mit dem ersten Differentialausgangsknoten (128) des kreuzgekoppelten Pegelumsetz-Latch gekoppelt ist; und

eine Invertierschaltung (104) mit einem Eingangsknoten (101), der ein digitales Signal empfängt und eine verzögerte Version des digitalen Signals dem ersten Eingangsknoten (112) des kreuzgekoppelten Pegelumsetz-Latch zuführt und eine invertierte Version des digitalen Signals dem zweiten Eingangsknoten (113) des kreuzgekoppelten Pegelumsetz-Latch zuführt, wobei die Invertierschaltung Folgendes umfasst:

eine nichtinvertierende digitale Logikschaltung (108), die einen ersten Inverter (125) und einen zweiten Inverter (126) mit dem Eingangsknoten (101) und einem Ausgangsknoten (111) umfasst, wobei der Ausgangsknoten (111) mit dem ersten Eingangsknoten des kreuzgekoppelten Pegelumsetz-Latch gekoppelt ist, wobei die nichtinvertierende digitale Logikschaltung so ausgelegt ist, dass sie die verzögerte Version des digitalen Signals bereitstellt; und

eine invertierende digitale Logikschaltung (109) mit dem Eingangsknoten (101) und einem Ausgangsknoten (110), wobei der Eingangsknoten (101) der invertierenden digitalen Logikschaltung der Eingangsknoten (101) der nichtinvertierenden digitalen Logikschaltung ist, wobei der Ausgangsknoten (110) der zweite Eingangsknoten des kreuzgekoppelten Pegelumsetz-Latch ist;

wobei die Ausbreitungsverzögerung des zweiten NOR-Gatters (124), das mit dem Set-Eingangsknoten (121) des Set-Reset-Logikgatter-Latch verbunden ist, im Wesentlichen gleich der Ausbreitungsverzögerung des ersten Inverters (125) der nichtinvertierenden digitalen Logikschaltung ist, so dass eine Ausbreitungsverzögerung eines durch die nichtinvertierende digitale Logikschaltung (108) passierenden Signals zum Ausgangsknoten des SR-(Set-Reset)-Logikgatter-Latch auf eine Ausbreitungsverzögerung eines durch die invertierende digitale Logikschaltung (109) passierenden Signals zum Ausgangsknoten des SR-Logikgatter-Latch abgestimmt ist.

2. Pegelumsetzerschaltung nach Anspruch 1, wobei der kreuzgekoppelte Pegelumsetz-Latch Folgendes umfasst:

einen Speisespannungsknoten,

einen ersten P-Kanal-Feldeffekttransistor (PFET) mit einer Quelle, einer Senke und einem Gatter, wobei die Quelle mit dem Speisespannungsknoten gekoppelt ist, wobei die Senke mit dem Set-Eingangsknoten (121) des SR-(Set-Reset)-Logikgatter-Latch (103) gekoppelt ist und wobei das Gatter mit dem zweiten Differentialausgangsknoten gekoppelt ist;

einen zweiten P-Kanal-Feldeffekttransistor mit einer Quelle, einer Senke und einem Gatter, wobei die Quelle mit dem Speisespannungsknoten gekoppelt ist, wobei die Senke mit dem Reset-Eingangsknoten des SR-Logikgatter-Latch gekoppelt ist und wobei das Gatter mit dem ersten Differentialausgangsknoten gekoppelt ist;

einen Masseknoten;

einen ersten N-Kanal-Feldeffekttransistor mit einer Quelle, einer Senke und einem Gatter, wobei die Quelle mit dem Masseknoten gekoppelt ist, wobei die Senke mit der Senke des ersten PFET gekoppelt ist und wobei das Gatter der erste Eingangsknoten des kreuzgekoppelten Pegelumsetz-Latch ist; und

einen zweiten N-Kanal-Feldeffekttransistor mit einer Quelle, einer Senke und einem Gatter, wobei die Quelle mit dem Masseknoten gekoppelt ist, wobei die Senke mit der Senke des zweiten P-Kanal-Feldeffekttransistors gekoppelt ist und wobei das Gatter der zweite Eingangsknoten des kreuzgekoppelten Pegelumsetz-Latch ist.

3. Pegelumsetzerschaltung nach Anspruch 1, wobei der SR-Logikgatter-Latch Folgendes umfasst:

ein erstes NOR-Gatter mit einem ersten Eingangsknoten, einem zweiten Eingangsknoten und einem Ausgangsknoten, wobei der erste Eingangsknoten der Reset-Eingangsknoten des SR-Logikgatter-Latch ist und wobei der Ausgangsknoten der Ausgangsknoten des SR-Logikgatter-Latch ist; und

ein zweites NOR-Gatter mit einem ersten Eingangsknoten, einem zweiten Eingangsknoten und einem Ausgangsknoten, wobei der erste Eingangsknoten der Set-Eingangsknoten des SR-Logikgatter-Latch ist, wobei der zweite Eingangsknoten der Ausgangsknoten des ersten NOR-Gatters ist und wobei der Ausgangsknoten der zweite Eingangsknoten des ersten NOR-Gatters ist.

4. Pegelumsetzerschaltung nach Anspruch 3, wobei ein erstes Signal, das vom Eingangsknoten der nichtinvertierenden digitalen Logikschaltung durch die nichtinvertierende digitale Logikschaltung zum Ausgangsknoten der nichtinvertierenden digitalen Logikschaltung passiert, eine erste Ausbreitungsverzögerung hat, wobei ein zweites Signal, das vom Eingangsknoten der invertierenden digitalen Logikschaltung durch die invertierende digitale Logikschaltung zum Ausgangsknoten der invertierenden digitalen Logikschaltung passiert, eine zweite Ausbreitungsverzögerung hat, und wobei die zweite Ausbreitungsverzogerung kürzer ist als die erste Ausbreitungsverzögerung.

5. Pegelumsetzerschaltung nach Anspruch 2, wobei der erste N-Kanal-Feldeffekttransistor (116) eine Kanalbreite hat, wobei der erste P-Kanal-Feldeffekttransistor (118) eine Kanalbreite hat und wobei die Kanalbreite des ersten N-Kanal-Feldeffekttransistors (116) größer ist als die Kanalbreite des ersten P-Kanal-Feldeffekttransistors (118).

6. Pegelumsetzerschaltung nach Anspruch 1, wobei die invertierende Schaltung von einer Speisespannung gespeist wird und wobei die Pegelumsetzerschaltung einen Tastverhältnisverzerrungsgrad von weniger als fünfzig Pikosekunden über einen Halbleiterverarbeitung-Variationsbereich über einen Betriebstemperaturbereich von 165 Grad Celsius und über einen Bereich der Speisespannung von plus oder minus zehn Prozent hat.

7. Pegelumsetzerschaltung nach Anspruch 5, wobei die Pegelumsetzerschaltung einen Tastverhältnisverzerrungsgrad von weniger als fünfzig Pikosekunden hat, wenn die Pegelumsetzerschaltung ein Eingangssignal von vierhundert Megahertz empfängt und ein Ausgangssignal von vierhundert Megahertz ausgibt, wobei die invertierende Schaltung von einer ersten Speisespannung gespeist wird, wobei der kreuzgekoppelte Pegelumsetz-Latch und der SR-Logikgatter-Latch von einer zweiten Speisespannung gespeist werden, und wobei die Pegelumsetzerschaltung den Tastverhältnisverzerrungsgrad von weniger als fünfzig Pikosekunden unter Bedingungen hat, dass die erste Speisespannung um plus oder minus zehn Prozent variiert, und unter Bedingungen, dass die zweite Speisespannung um plus oder minus zehn Prozent variiert, und wobei die Pegelumsetzerschaltung einen Tastverhältnisverzerrungsgrad von weniger als fünfzig Pikosekunden über einen Temperaturbereich von 165 Grad Celsius hat.

Revendications

1. Circuit décaleur de niveau comprenant :

un verrou de décalage de niveau interconnecté (102) ayant un premier noeud d'entrée (112), un deuxième noeud d'entrée (113), un premier noeud de sortie différentielle (114) et un deuxième noeud de sortie différentielle (115);

un verrou de porte logique de mise à un/mise à zéro (SR) (103) comprenant une première porte NON-OU (123) et une deuxième porte NON-OU (124) et ayant un noeud d'entrée de mise à zéro (120), un noeud d'entrée de mise à un (121) et un seul noeud de sortie (122), dans lequel le noeud d'entrée de mise à zéro (120) est couplé au deuxième noeud de sortie différentielle (129) du verrou de décalage de niveau interconnecté et où le noeud d'entrée de mise à un (121) est couplé au premier noeud de sortie différentielle (128) du verrou de décalage de niveau interconnecté; et

un circuit inverseur (104) ayant un noeud d'entrée (101) qui reçoit un signal numérique et fournit une version différée du signal numérique au premier noeud d'entrée (112) du verrou de décalage de niveau interconnecté et qui fournit une version inversée du signal numérique au deuxième noeud d'entrée (113) du verrou de décalage de niveau interconnecté, dans lequel le circuit inverseur comprend :

un circuit logique numérique non inverseur (108) comprenant un premier inverseur (125) et un deuxième inverseur (126) ayant le noeud d'entrée (101) et un noeud de sortie (111), dans lequel le noeud de sortie (111) est couplé au premier noeud d'entrée du verrou de décalage de niveau interconnecté, le circuit logique numérique non inverseur arrangé pour fournir la version différée du signal numérique; et

un circuit logique numérique inverseur (109) ayant le noeud d'entrée (101) et un noeud de sortie (110), dans lequel le noeud d'entrée (101) du circuit logique numérique inverseur est le noeud d'entrée (101) du circuit logique numérique non inverseur, dans lequel le noeud de sortie (110) est le deuxième noeud d'entrée du verrou de décalage de niveau interconnecté;

dans lequel le temps de propagation de la deuxième porte NON-OU (124) étant connectée au noeud d'entrée de mise à un (121) du verrou de porte logique de mise à un/mise à zéro, est sensiblement égal au temps de propagation du premier inverseur (125) du circuit logique numérique non inverseur, en vertu de quoi un temps de propagation d'un signal passant à travers le circuit logique numérique non inverseur (108) jusqu'au noeud de sortie du verrou de porte logique de mise à un/mise à zéro (SR), est assorti à un temps de propagation d'un signal passant à travers le circuit logique numérique inverseur (109) jusqu'au noeud de sortie du verrou de porte logique SR.

2. Circuit décaleur de niveau selon la revendication 1, dans lequel le verrou de décalage de niveau interconnecté comprend :

un noeud de tension d'alimentation,

un premier transistor à effet de champ à canal P (PFET) ayant une source, un drain et une porte, dans lequel la source est couplée au noeud de tension d'alimentation et dans lequel le drain est couplé au noeud d'entrée de mise à un (121) du verrou de porte logique (103) de mise à un/mise à zéro (SR) et dans lequel la porte est couplée au deuxième noeud de sortie différentielle;

un deuxième transistor à effet de champ à canal P ayant une source, un drain et une porte, dans lequel la source est couplée au noeud de tension d'alimentation et dans lequel le drain est couplé au noeud d'entrée de mise à zéro du verrou de porte logique SR et dans lequel la porte est couplée au premier noeud de sortie différentielle;

un noeud de terre;

un premier transistor à effet de champ à canal N ayant une source, un drain et une porte, dans lequel la source est couplée au noeud de terre, dans lequel le drain est couplé au drain du premier PFET et dans lequel la porte est couplée au premier noeud d'entrée du verrou de décalage de niveau interconnecté; et

un deuxième transistor à effet de champ à canal N ayant une source, un drain et une porte, dans lequel la source est couplée au noeud de terre, dans lequel le drain est couplé au drain du deuxième transistor à effet de champ à canal P et dans lequel la porte est le deuxième noeud d'entrée du verrou de décalage de niveau interconnecté.

3. Circuit décaleur de niveau selon la revendication 1, dans lequel le verrou de porte logique SR comprend :

une première porte NON-OU ayant un premier noeud d'entrée, un deuxième noeud d'entrée et un noeud de sortie, dans laquelle le premier noeud d'entrée est le noeud d'entrée de mise à zéro du verrou de porte logique SR et dans laquelle le noeud de sortie est le noeud de sortie du verrou de porte logique SR; et

une deuxième porte NON-OU ayant un premier noeud d'entrée et un noeud de sortie, dans laquelle le premier noeud d'entrée est le noeud d'entrée de mise à un du verrou de porte logique SR, dans laquelle le deuxième noeud d'entrée est le noeud de sortie de la première porte NON-OU et dans laquelle le noeud de sortie est le deuxième noeud d'entrée de la première porte NON-OU.

4. Circuit décaleur de niveau selon la revendication 3, dans lequel un premier signal passant à travers le circuit logique numérique non inverseur du noeud d'entrée du circuit logique numérique non inverseur jusqu'au noeud de sortie du circuit logique numérique non inverseur a un premier temps de propagation, dans lequel un deuxième signal passant à travers le circuit logique numérique inverseur du noeud d'entrée du circuit logique numérique inverseur jusqu'au noeud de sortie du circuit logique numérique inverseur a un deuxième temps de propagation et dans lequel le deuxième temps de propagation est plus court que le premier temps de propagation.

5. Circuit décaleur de niveau selon la revendication 2, dans lequel le premier transistor à effet de champ à canal N (116) a une largeur de canal, dans lequel le premier transistor à effet de champ à canal P (118) a une largeur de canal et dans lequel la largeur de canal du premier transistor à effet de champ à canal N (116) est plus grande que la largeur de canal du premier transistor à effet de champ à canal P (118).

6. Circuit décaleur de niveau selon la revendication 1, dans lequel le circuit inverseur est alimenté par une tension d'alimentation et dans lequel le circuit décaleur de niveau a une obliquité de distorsion de cycle de service de moins de cinquante picosecondes sur une plage de variation de traitement d'un semi-conducteur, sur une plage de température de fonctionnement de 165 degrés Celsius et sur une plage de tension d'alimentation de plus ou moins dix pour cent.

7. Circuit décaleur de niveau selon la revendication 5, où le circuit décaleur de niveau a une obliquité de distorsion de cycle de service de moins de cinquante picosecondes lorsque le circuit décaleur de niveau reçoit un signal d'entrée de quatre cents mégahertz et sort un signal de sortie de quatre cents mégahertz, dans lequel le circuit inverseur est alimenté par une première tension d'alimentation, dans lequel le verrou de décalage de niveau interconnecté et le verrou de porte logique SR sont alimentés par une deuxième tension d'alimentation et où le circuit décaleur de niveau a l'obliquité de distorsion de cycle de service de moins de cinquante picosecondes dans des conditions de la première tension d'alimentation variant de plus ou moins dix pour cent et dans des conditions de la deuxième tension d'alimentation variant de plus ou moins dix pour cent et où le circuit décaleur de niveau a l'obliquité de distorsion de cycle de service de moins de cinquante picosecondes sur une plage de température de 165 degrés Celsius.

Drawing