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(11) | EP 2 187 453 B1 |
| (12) | EUROPEAN PATENT SPECIFICATION |
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Light Emitting Device and Method of Manufacturing the Same Lichtemittierende Vorrichtung und Verfahren zu ihrer Herstellung Dispositif électroluminescent et son procédé de fabrication |
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| Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention). |
BACKGROUND
1. Field
[0001] Example embodiments relate to a light emitting device (LED) manufactured by using a wafer bonding method, and to a method of manufacturing a LED using a wafer bonding method.
2. Description of the Related Art
[0002] Light emitting diodes (LEDs) including a semiconductor material, e.g., a Group III nitride semiconductor, or a Zn-Mg-O-based semiconductor material, may be made relatively small and light and have a relatively long lifetime. Various technologies have been developed to increase the efficiency of LEDs. Recently, in order to use a LED as a conventional lighting device, research on high-output and high-brightness LEDs has been conducted. However, because of the structure of a LED, when high-power is supplied to a LED, the efficiency of the LED decreases as compared to a case where low-power is supplied to a LED.
[0003] Thus, a vertical type LED having an efficient current application structure has been proposed. Unlike a horizontal type LED in which a part of a semiconductor layer is etched and an electrode is formed in the etched part, the vertical type LED may be directly located in an upper surface and a lower surface of the semiconductor layer. Accordingly, the vertical type LED has improved efficiency and higher output as compared to the horizontal LED. The vertical type LED is also more easily cooled as compared to the horizontal type LED, because heat generated during operation thereof is more easily radiated to the outside.
[0004] On the other hand, in the case of the vertical type LED, because an electrode should be located in upper and lower surfaces of a semiconductor layer, the vertical type LED requires a different manufacturing process from the horizontal type LED. For example, after a semiconductor layer is grown on a growth substrate, e.g., sapphire, the growth substrate is removed in order to perform subsequent processes. Before removing the growth substrate, plating (via a plating method) or wafer bonding (via a wafer bonding method) is performed with respect to the semiconductor layer so as to stably fix the semiconductor layer from which the growth substrate is to be removed. When plating is used, difficulties may arise in performing the entire process due to a decrease in flatness and solidity of the plated metal thin film. When wafer bonding is used, a crack may occur in the semiconductor layer during a cooling process performed after wafer bonding, due to a difference of expansion coefficients of the growth substrate, e.g., sapphire, and a new bonding substrate. Also, the entire structure of the semiconductor layer may bend or warp.
[0005] US 2006/0226434 describes a nitride type vertical LED structure which is manufactured by bonding a vertical LED structure onto a substrate. A metal ohmic electrode forms the interface.
[0006] US2008-0135859 describes a method of manufacturing a vertical LED structure including using microwaves to carry out bonding whereby a nickel contact layer is provided below the bonding layer of the substrate. US2008/021969 describes the use of seed layers of different materials on an ohmic contact and below a thick copper layer to buffer stress problems caused by the different thermal expansion coefficients of the copper and semiconductor structure. JP 11-307 875 describes an electronic device with multiple submounts soldered together.
[0007] JP 58-052 892 describes a mounting of a compound semiconductor laser element having a submount having a molybdenum plate on top of the submount for reducing stress of the device with regard to the submount during operation of the device.
SUMMARY
[0008] Example embodiments include a light emitting device (LED) manufactured by using a wafer bonding method that reduces bending or warpage, and to a method of manufacturing a LED using a wafer bonding method. Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of example embodiments.
[0010] The LED further includes a bonding material layer between the first electrode and the first stress relaxation layer and between the first stress relaxation layer and the bonding substrate. The bonding material layer may have a thickness in the range of about 0.5 µm to about 3 µm. The first stress relaxation layer may be formed of a material having a melting point greater than the bonding material layer.
[0011] The bonding substrate may be a conductive substrate. The LED may further include a first bonding metal layer under the bonding substrate and a second bonding metal layer on the second electrode. The bonding substrate may be a nonconductive substrate having a thermal expansion coefficient in the range of about 4×10-6 Å/K to about 8×10-6 Å/K. The bonding substrate may be a glass substrate.
[0012] The LED may further include a first bonding metal layer configured to electrically connect to the first electrode on side portions of the semiconductor layer, and a second bonding metal layer on the second electrode. The LED may further include the first bonding metal layer under the first stress relaxation layer and the second bonding metal layer on the second electrode.
[0014] The first and second stress relaxation layers may be bonded by interposing the bonding material layer between the first electrode and the first stress relaxation layer and between the first stress relaxation layer and the second stress relaxation layer. The second stress relaxation layer may be on the bonding substrate.
[0015] The first stress relaxation layer may be bonded by interposing the bonding material layer between the first electrode and the first stress relaxation layer, and in example embodiments, the first stress relaxation layer may be on the bonding substrate. The method may further include removing the bonding substrate. Processing the semiconductor layer may include forming a second electrode on the semiconductor layer.
BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. FIGS. 1 - 8B represent non-limiting, example embodiments as described herein.
[0017] The disclosure contains embodiments from which some are embodiments of the invention.
FIG. 1 is a schematic cross-sectional view illustrating a structure in which a semiconductor layer is grown on a growth substrate, according to a comparative example;
FIG. 2 is a schematic cross-sectional view illustrating a process for bonding a semiconductor layer to a bonding substrate, according to a comparative example;
FIG. 3 is a schematic cross-sectional view illustrating a process for bonding the semiconductor layer of FIG. 1 to a bonding substrate, according to a comparative example;
FIG. 4 is a schematic cross-sectional view illustrating a process for bonding the semiconductor layer of FIG. 1 to a bonding substrate, according to example embodiments;
FIG. 5 is a schematic cross-sectional view illustrating a process for removing a growth substrate through a lift-off process after bonding the bonding substrate of FIG. 4, according to example embodiments;
FIG. 6 is a schematic cross-sectional view illustrating a light emitting diode (LED) completed through the subsequent process after removing the growth substrate, according to example embodiments;
FIGS. 7A and 7B are schematic cross-sectional views illustrating a process for manufacturing a LED after removing the growth substrate, according to example embodiments; and
FIGS. 8A and 8B are schematic cross-sectional views illustrating a process for manufacturing a LED after removing the growth substrate, according to example embodiments.
[0018] It should be noted that these Figures are intended to illustrate the general characteristics of methods, structure and/or materials utilized in certain example embodiments and to supplement the written description provided below. These drawings are not, however, to scale and may not precisely reflect the precise structural or performance characteristics of any given embodiment, and should not be interpreted as defining or limiting the range of values or properties encompassed by example embodiments. For example, the relative thicknesses and positioning of molecules, layers, regions and/or structural elements may be reduced or exaggerated for clarity. The use of similar or identical reference numbers in the various drawings is intended to indicate the presence of a similar or identical element or feature.
DETAILED DESCRIPTION
[0019] Reference will now be made in detail to example embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. In this regard, example embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, example embodiments are merely described below, by referring to the figures, to explain aspects of the present description. In the drawings, the thicknesses and the widths of layers are exaggerated for clarity.
[0020] It will be understood that when an element or layer is referred to as being "on," "connected to" or "coupled to" another element or layer, it may be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
[0021] It will be understood that, although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of example embodiments.
[0022] Spatially relative terms, e.g., "beneath," "below," "lower," "above," "upper" and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would be oriented "above" the other elements or features. Thus, the exemplary term "below" may encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
[0023] The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
[0024] Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized example embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle may, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
[0025] Unless otherwise defined, all terms including technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belongs. It will be further understood that terms, e.g., those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
[0026] Referring to FIG. 1, a first semiconductor layer 21, an active layer 22, and a second semiconductor layer 23 may be sequentially grown on a growth substrate 11, and a first electrode 24 may be grown on the second semiconductor layer 23. The growth substrate 11 may be a sapphire substrate. The first semiconductor layer 21, the active layer 22, and the second semiconductor layer 23 may be formed of a semiconductor material, e.g., a Group III nitride semiconductor which is a combination of GaN-AIN-InN or a Zn-Mg-O-based semiconductor material. The first semiconductor layer 21 may be an n-semiconductor layer doped with an n-type material, and the second semiconductor layer 23 may be a p-semiconductor layer doped with a p-type material. The active layer 22, which is an active region for generating light by recombination of electrons and holes, may have a single- or multi-quantum well structure. The first electrode 24 may be a p-type electrode when the second semiconductor layer 23 is a p-semiconductor layer.
[0027] Although not shown in in FIG. 1, a buffer layer for improving crystal quality may be additionally interposed between the growth substrate 11 and the first semiconductor layer 21. Also, although not shown in FIG. 1, to form a plurality of LED chips on one growth substrate 11, the first semiconductor layer 21, the active layer 22, the second semiconductor layer 23, and the first electrode 24 may be partially etched and divided into a plurality of regions. Because the above process may be the same as a conventional LED manufacturing process, its detailed description will be omitted.
[0028] Before performing the subsequent process for manufacturing a LED, a bonding substrate may be bonded to a structure illustrated in FIG. 1 according to a wafer bonding method. Various examples and embodiments regarding bonding of the bonding substrate to the structure illustrated in FIG. 1 will now be described. Hereinafter, the first semiconductor layer 21, the active layer 22, the second semiconductor layer 23, and the first electrode 24 will be referred to as a semiconductor layer 20 for convenience. Accordingly, in the following description of drawings, only one layer denoted as the semiconductor layer 20 will be illustrated for convenience.
[0029] FIG. 2 is a schematic cross-sectional view illustrating a process for bonding the semiconductor layer 20 of FIG. 1 to a bonding substrate 31, according to example embodiments. As described above, when a wafer bonding method is used, bending or warpage may occur due to a difference of the thermal expansion coefficients between the growth substrate 11 and the bonding substrate 31 during the cooling process. As illustrated in FIG. 2, in order to ease or prevent bending or warpage, an additional stress relaxation layer 33 formed of a metal sheet may be between the semiconductor layer 20 and the bonding substrate 31. For example, a bonding material layer 32 may be interposed between the bonding substrate 31 and the stress relaxation layer 33, and a bonding material layer 34 may be interposed between the stress relaxation layer 33 and the semiconductor layer 20. The bonding material layers 32 and 34 may be melted to bond these layers.
[0030] Bonding material layers 34a and 34b may be respectively coated on a surface of the stress relaxation layer 33 and a surface of the semiconductor layer 20 which face each other, and the bonding material layers 34a and 34b may be melted to form the bonding material layer 34 and bond the stress relaxation layer 33 to the semiconductor layer 20. In FIG. 2, the growth substrate 11 and the semiconductor layer 20 are illustrated in reversed positions as compared to the illustration of FIG. 1. In more detail, the bonding material layer 34 may be interposed between the first electrode 24 and the stress relaxation layer 33, and accordingly, the stress relaxation layer 33 may be bonded onto a surface of the first electrode 24.
[0031] Because the stress relaxation layer 33 absorbs a difference of thermal expansion coefficients between the bonding substrate 31 and the growth substrate 11, bending or warpage may be eased or prevented during the cooling process after the bonding process. For this, a material formed of a metal sheet having improved flexibility may be used as the stress relaxation layer 33.
[0032] When a metal sheet having flexibility is interposed between the bonding substrate 31 and the growth substrate 11, even if the bonding substrate 31 and the growth substrate 11 contract differently during the cooling process, the bonding substrate 31 and the growth substrate 11 may not affect each other due to the flexibility of the metal sheet interposed therebetween. In order to enable the difference of the thermal expansion coefficients between the bonding substrate 31 and the growth substrate 11 and to be sufficiently absorbed, the stress relaxation layer 33 needs to be thick enough. For example, the stress relaxation layer 33 formed of the metal sheet may be formed to have a thickness in the range of about 10 µm to about 1 mm, and more particularly, from about 50 µm to about 300 µm.
[0033] The stress relaxation layer 33 may have electrical conductivity so as to transmit a current that is applied from the outside to the semiconductor layer 20. The stress relaxation layer 33 may also have a melting point greater than the bonding material layers 32 and 34 so as not to be transformed in the bonding process. A material for forming the stress relaxation layer 33 satisfying the above conditions is chrome (Cr), nickel (Ni), tin (Sn), molybdenum (Mo), titanium (Ti), copper (Cu), or an alloy thereof. In FIG. 2, the stress relaxation layer 33 is illustrated as a single-layer, but may be formed in a multi-layered structure in which a plurality of layers each formed of different material are stacked.
[0034] The bonding material layers 32 and 34 may be formed of a eutectic bonding material, for example, an AuSn alloy or an AuGe alloy having electrical conductivity. The bonding material layers 32 and 34 may be formed by e-beam deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD), and the bonding material layers 32 and 34 may be formed to have thicknesses in the range of about 0.5 to about 3 µm. The stress relaxation layer 33 may be bonded to both the bonding substrate 31 and the semiconductor layer 20 by melting the bonding material layers 32 and 34. The AuSn alloy has a melting point of about 280°C, and the AuGe alloy has a melting point above about 300°C. Conventionally, in order to minimize or reduce bending or warpage during a cooling process, the AuSn alloy, which is relatively melted at a low temperature, is mainly used as a bonding material.
[0035] A low-temperature thermal treatment less than about 300°C may be performed in order to prevent or reduce transformation of a bonding material in the thermal treatment for a stable operation of a LED. On the other hand, in example embodiments, because bending or warpage may be prevented or reduced through the stress relaxation layer 33, an AuGe alloy having a relatively high melting point may be used as the bonding material layers 32 and 34. Because a high-temperature thermal treatment above about 300°C may be performed in the subsequent thermal treatment process of a LED, quality and operation stability of the LED may be improved.
[0036] The bonding substrate 31 may generally use a silicon substrate having conductivity. However, the bonding substrate 31 is not limited to the silicon substrate, and various substrates formed of various materials may be used. For example, the bonding substrate 31 may be a nonconductive substrate, e.g., a glass substrate, and the nonconductive substrate may be formed of a material having a thermal expansion coefficient in the range of about 4×10-6 Å/K to about 8×10-6 Å/K.
[0037] FIG. 3 is a schematic cross-sectional view illustrating a process for bonding the semiconductor layer of FIG. 1 to a bonding substrate,. FIG. 3 is different from FIG. 2 in that a stress relaxation layer is not bonded to the bonding substrate 31 by using a bonding material layer, and the stress relaxation layer 35 is directly deposited or grown on the bonding substrate 31. As for the other descriptions, examples described in FIG. 2 may be the same as examples described in FIG. 3. Accordingly, the stress relaxation layer 35 which is previously formed on the bonding substrate 31 may be bonded to a surface of the semiconductor layer 20 through the bonding material layer 34.
[0038] FIG. 4 is a schematic cross-sectional view illustrating a process for bonding the semiconductor layer of FIG. 1 to a bonding substrate, according to an embodiment of the invention. The example embodiment illustrated in FIG. 4 includes both stress relaxation layes illustrated in FIGS. 2 and 3. That is, as illustrated in FIG. 4, the first stress relaxation layer 33 is bonded to the surface of the semiconductor layer 20 by interposing the bonding material layer 34 between the first stress relaxation layer 33 and the semiconductor layer 20. At the same time, the first stress relaxation layer 33 is bonded to the bonding substrate 31 by interposing the bonding material layer 32 between the first stress relaxation layer 33 and the bonding substrate 31 in which the second stress relaxation layer 35 is deposited on the surface of the bonding substrate 31.
[0039] The bonding material layers 34a and 34b may be respectively coated on a surface of the first stress relaxation layer 33 and a surface of the semiconductor layer 20, and the bonding material layers 34a and 34b may be melted to form the bonding material layer 34 and bond the stress relaxation layer 33 to the semiconductor layer 20. Thus, the second stress relaxation layer 35, the bonding material layer 32, the first stress relaxation layer 33, the bonding material layer 34, the semiconductor layer 20, and the growth substrate 11 may be sequentially stacked on the bonding substrate 31.
[0040] In this structure, because two stress relaxation layers 33 and 35 are disposed between the semiconductor layer 20 and the bonding substrate 31, bending or warpage is further reduced. The first and second stress relaxation layers 33 and 35 may be formed of the same material or different materials. Also, the stress relaxation layers 33 and 35 may be formed to have the same thickness or different thicknesses.
[0041] After the semiconductor layer 20 and the bonding substrate 31 are bonded using a wafer bonding method illustrated in FIG. 2 or FIG. 4, as illustrated in FIG. 5, the growth substrate 11 may be removed using a laser lift-off (LLO) method. The semiconductor layer 20 may be externally exposed. In particular, referring to FIG. 1, the first semiconductor layer 21 of the semiconductor layer 20 is externally exposed.
[0042] After the growth substrate 11 is removed, a LED may be completed by processing the semiconductor layer 20 according to the conventional subsequent process. For example, a surface of the semiconductor layer 20 may be partially etched or cleaned via an etching method. Also, texturing for forming a geometrical relief structure may be performed on the surface of the semiconductor layer 20 in order to increase light extraction efficiency. A second electrode may be formed on the surface of the semiconductor layer 20.
[0043] FIG. 6 is a schematic cross-sectional view illustrating a LED completed through the subsequent process after removing the growth substrate, according to example embodiments. FIG. 6 illustrates the LED 10 obtained by performing the subsequent process with respect to the structure of FIG. 4. However, FIG. 6 may also relate to the structures formed according to example embodiments described in FIGS. 2 and 4. Referring to FIG. 6, a second electrode 25 may be disposed on the surface of the semiconductor layer 20. For example, when the first semiconductor layer 21 illustrated in FIG. 1 is an n-semiconductor layer, the second electrode 25 is an n-type electrode. The second electrode 25 may also be a transparent electrode transmitting light, and the second electrode 25 may be formed of indium tin oxide (ITO).
[0044] A first bonding metal layer 41 may be disposed under the bonding substrate 31, and a second bonding metal layer 42 may be disposed on the second electrode 25. The first and second bonding metal layers 41 and 42 may be coupled with a wire (not shown) connected to a lead frame of a package (not shown) when packaging a completed LED. Accordingly, a current applied through the wire from the lead frame may be respectively sent to the first and second electrodes 24 and 25 through the first and second bonding metal layers 41 and 42. In example embodiments, the bonding substrate 31 may be formed of a conductive substrate, e.g., silicon.
[0045] As described above, the bonding substrate 31 may be a nonconductive substrate. In example embodiments, the first bonding metal layer 41 may not be disposed under the bonding substrate 31.
[0046] FIGS. 7A and 7B illustrate a bonding substrate 31 that is a nonconductive substrate, according to example embodiments. FIGS. 7A and 7B illustrate a LED obtained by performing the subsequent process with respect to the structure formed according to example embodiments described in FIG. 4, but FIGS. 7A and 7B may also relate to the structures formed according to example embodiments described in FIGS. 2 and 3.
[0047] As illustrated in FIG. 7A, after the semiconductor layer 20 is processed, the bonding substrate 31 may be removed. The bonding substrate 31 may be more easily removed by polishing, e.g., chemical mechanical polishing (CMP), and only first and second stress relaxation layers 33 and 35 remain under the semiconductor layer 20. As illustrated in FIG. 7B, after the second electrode 25 is formed, the first bonding metal layer 41 may be disposed under the second stress relaxation layer 35, and the second bonding metal layer 42 may be disposed on the second electrode 25. A current applied to the first bonding metal layer 41 may be sent to the first electrode 24 (see FIG. 1) of the semiconductor layer 20 through the second stress relaxation layer 35, the bonding material layer 32, the first stress relaxation layer 33, and the bonding material layer 34, and may be sent to the second semiconductor layer 23 (see FIG. 1) through the first electrode 24 again. A current applied to the second bonding metal layer 42 may also be sent to the first semiconductor layer 21 (see FIG. 1) through the second electrode 25.
[0048] FIGS. 8A and 8B illustrate a bonding substrate 31 that is a nonconductive substrate, according to embodiments of the invention. FIGS. 8A and 8B are schematic cross-sectional views illustrating a process for manufacturing a LED after removing the growth substrate, according to example embodiments. As described above, FIGS. 8A and 8B illustrate a LED obtained by performing the subsequent process with respect to the structure formed according to example embodiments described in FIGS. 2 and 3. Referring to FIG. 8A, after the semiconductor layer 20 is processed and the second electrode 25 is formed, both edge portions of each of the semiconductor layer 20 and the second electrode 25 are etched and thus removed. Both edge portions of the semiconductor layer 20 may be completely removed to expose a part of the bonding material layers 34a and 34b. For example, the etching process may be performed until the bonding material layer 34a attached onto the first stress relaxation layer 33 is exposed. In an alternative example embodiment, the etching process may be performed to expose only a part of the first electrode 24 (see FIG. 1) by removing up to the second semiconductor layer 23 of the semiconductor layer 20.
[0049] As illustrated in FIG. 8B, the first bonding metal layer 41 is disposed on both side portions of the semiconductor layer 20, and the second bonding metal layer 42 may be disposed on the second electrode 25. In FIG. 8B, the first bonding metal layer 41 may be disposed on both side portions of the semiconductor layer 20, but the first bonding metal layer 41 may be formed in a ring-shape surrounding the circumference of the semiconductor layer 20. According to the invention the first bonding metal layer 41 may be electrically connected to the first electrode 24 through the bonding material layer 34. In an example of the disclosure, the first bonding metal layer 41 may directly contact the first electrode 24 and be electrically connected to the first electrode 24. In FIG. 8B, the bonding material layer 34a may remain on the first stress relaxation layer 33, and the first bonding metal layer 41 may be formed on the bonding material layer 34a. In example embodiments, a current applied to the first bonding metal layer 41 may be sent to the first electrode 24 through the bonding material layers 34a and 34b. However, under different conditions, an etching process may be performed until a part of the first electrode 24 is exposed, and the first bonding metal layer 41 may be formed on the first electrode 24.
[0050] It should be understood that these example embodiments described therein should be considered in a descriptive sense only, and not for purposes of limitation, the invention being defined by the appended claims. Descriptions of features or aspects within each example embodiment should typically be considered as available for other similar features or aspects in other example embodiments.
a semiconductor layer (20) including an active region (22) for emitting light and a first electrode (24);
a second electrode (25) on the semiconductor layer; and
a first layer (33) bonded to a surface of the first electrode (24) and formed of a metal; and
a bonding substrate (31) under the first layer, and the first layer (33) comprises at least one selected from the group consisting of chrome (Cr), nickel (Ni), tin (Sn), molybdenum (Mo), titanium (Ti), copper (Cu), and an alloy thereof, and characterized in that the first layer is a stress relaxation layer (33), and is formed to have a thickness in the range of about 10 µm to about 1 mm;
further characterised by a bonding material layer (34) of a eutectic bonding material between the first electrode and the first layer; and
a bonding metal layer (41) disposed on both side portions of the semiconductor layer (20) and electrically connected to the first electrode (24) through the bonding material layer (34)..
bonding material layers (32,34) between the first electrode and the first stress relaxation layer and between the first stress relaxation layer and the bonding substrate.
a second stress relaxation layer (35) between the first stress relaxation layer and the bonding substrate and formed of a metal.
a first bonding metal layer under the bonding substrate; and
a second bonding metal layer on the second electrode.
wherein the LED further comprises a second bonding metal layer (42) on the second electrode.
forming a semiconductor layer (20) on a growth substrate (11), the semiconductor layer including an active region (22) for emitting light and a first electrode (24);
bonding a bonding substrate (31) to a surface of the first electrode (24);
removing the growth substrate (11); and
processing the semiconductor layer (20),
wherein a first stress relaxation layer (33) formed of a metal is bonded between the first electrode (24) and the bonding substrate (31), the first stress relaxation layer (33) comprising at least one selected from the group consisting of chrome (Cr), nickel (Ni), tin (Sn), molybdenum (Mo), titanium (Ti), copper (Cu), and an alloy thereof and wherein the first stress relaxation layer (33) is formed to have a thickness in the range of about 10 µm to about 1 mm,
the method further comprising:
depositing or growing a second stress relaxation layer (35) formed of a metal on the bonding substrate (31),
wherein bonding the bonding substrate includes interposing bonding material layers (32,34) between the first electrode (24) and the first stress relaxation layer (33) and between the first stress relaxation layer (33) and the second stress relaxatin layer (35).
bonding a second stress relaxation layer (35) formed of a metal between the first stress relaxation layer (33) and the bonding substrate (31). wherein bonding the first and second stress relaxation layers includes interposing the bonding material layers (32,34) between the first electrode (24) and the first stress relaxation layer (33) and between the first stress relaxation layer (33) and the second stress relaxation layer (35);wherein the second stress relaxation layer (35) is on the bonding substrate (31).
eine einen aktiven Bereich (22) zum Emittieren von Licht und eine erste Elektrode (24) umfassende Halbleiterschicht (20),
eine zweite Elektrode (25) auf der Halbleiterschicht und
eine erste an eine Oberfläche der ersten Elektrode (24) gebondete und aus einem Metall
gebildete Schicht (33) und
ein Bondsubstrat (31) unter der ersten Schicht
und die erste Schicht (33) weist mindestens einen aus der Gruppe bestehend aus Chrom
(Cr), Nickel (Ni), Zinn (Sn), Molybdän (Mo), Titan (Ti), Kupfer (Cu) und eine Legierung
davon ausgewählten auf, und dadurch gekennzeichnet, dass eine erste Schicht eine Spannungsrelaxationsschicht (33) ist und
gebildet ist, um eine Dicke im Bereich von ungefähr 10 µm bis ungefähr 1mm zu haben,
ferner gekennzeichnet durch eine Bondmaterialschicht (34) aus einem eutektischem Bondmaterial zwischen der ersten Elektrode und der ersten Schicht und
eine auf beiden Seitenabschnitte der Halbleiterschicht (20) angeordnete und elektrisch an die erste Elektrode (24) durch die Bondmaterialschicht (34) angeschlossene Bondmetallschicht (41).
eine zweite Spannungsrelaxationsschicht (35) zwischen der ersten Spannungsrelaxationsschicht und dem Bondsubstrat und aus einem Metall gebildet.
eine erste Bondmetallschicht unter dem Bondsubstrat und
eine zweite Bondmetallschicht auf der zweiten Elektrode.
wobei die LED ferner eine zweite Bondmetallschicht (42) auf der zweiten Elektrode aufweist.
Bilden einer Halbleiterschicht (20) auf einem Zuchtsubstrat (11), wobei die Halbleiterschicht einen aktiven Bereich (22) zum Emittieren von Licht und eine erste Elektrode (24) umfasst,
Bonden eines Bondsubstrats (31) an eine Oberfläche der ersten Elektrode (24), Entfernen
des Zuchtsubstrats (11) und
Verarbeiten der Halbleiterschicht (20),
wobei eine aus einem Metall gebildete erste Spannungsrelaxationsschicht (33) zwischen der ersten Elektrode (24) und dem Bondsubstrat (31) gebondet ist, wobei die erste Spannungsrelaxationsschicht (33) mindestens einen aus der Gruppe bestehend aus Chrom (Cr), Nickel (Ni), Zinn (Sn), Molybdän (Mo), Titan (Ti), Kupfer (Cu) und einer Legierung davon ausgewählten ausweist und wobei die erste Spannungsrelaxationsschicht (33) gebildet ist, um eine Dicke im Bereich von ungefähr 10 µm bis ungefähr 1 mm zu haben, wobei das Verfahren ferner Folgendes umfasst:
Auftragen oder Züchten einer zweiten aus einem Metall gebildeten Spannungsrelaxationsschicht (35) auf dem Bondsubstrat (31),
wobei das Bonden des Bondsubstrats das Einfügen von Bondmaterialschichten (32,34) zwischen der ersten Elektrode (24) und der ersten Spannungsrelaxationsschicht (33) und zwischen der ersten Spannungsrelaxationsschicht (33) und der zweiten Spannungsrelaxationsschicht (35) einschließt.
Bonden einer zweiten aus einem Metall gebildeten Spannungsrelaxationsschicht (35) zwischen der ersten Spannungsrelaxationsschicht (33) und dem Bondsubstrat (31), wobei das Bonden der ersten und zweiten Spannungsrelaxationsschicht das Einfügen der Bondmaterialschichten (32,34) zwischen der ersten Elektrode (24) und der ersten Spannungsrelaxationsschicht (33) und zwischen der ersten Spannungsrelaxationsschicht (33) und der zweiten Spannungsrelaxationsschicht (35) einschließt, wobei die zweite Spannungsrelaxationsschicht (35) sich auf dem Bondsubstrat (31) befindet.
une couche semi-conductrice (20) comprenant une zone active (22) pour l'émission de lumière et une première électrode (24) ;
une seconde électrode (25) sur la couche semi-conductrice ; et
une première couche (33) collée sur une surface de la première électrode (24) et formée d'un métal ; et
un substrat de collage (31) sous la première couche et
la première couche (33) comprenant au moins un élément sélectionné dans le groupe constitué par le chrome (Cr), le nickel (Ni), l'étain (Sn), le molybdène (Mo), le titane (Ti), le cuivre (Cu) et un alliage de ceux-ci, et caractérisée en ce que la première couche est une couche de relaxation de contrainte (33), et
est formée pour posséder une épaisseur comprise dans la plage allant d'environ 10 µm à environ 1 mm ;
caractérisée en outre par une couche de matériau de collage (34) d'un matériau de collage eutectique entre la première électrode et la première couche ; et
une couche métallique de collage (41) disposée sur les deux parties latérales de la couche semi-conductrice (20) et connectée électriquement à la première électrode (24) à travers la couche de matériau de collage (34).
une seconde couche de relaxation de contrainte (35) comprise entre la première couche de relaxation de contrainte et le substrat de collage et constituée d'un métal.
une première couche métallique de collage sous le substrat de collage ; et
une seconde couche métallique de collage sur la seconde électrode.
ladite LED comprenant en outre une seconde couche métallique de collage (42) sur la seconde électrode.
la formation d'une couche semi-conductrice (20) sur un substrat de croissance (11), la couche semi-conductrice comprenant une zone active (22) pour l'émission de lumière et une première électrode (24) ;
le collage d'un substrat de collage (31) sur une surface de la première électrode (24) ;
le retrait du substrat de croissance (11) ; et
le traitement de la couche semi-conductrice (20),
ladite première couche de relaxation de contrainte (33) constituée d'un métal étant collée entre la première électrode (24) et le substrat de collage (31), la première couche de relaxation de contrainte (33) comprenant au moins un élément sélectionné dans le groupe constitué par le chrome (Cr), le nickel (Ni), l'étain (Sn), le molybdène (Mo), le titane (Ti), le cuivre (Cu) et un alliage de ceux-ci et ladite première couche de relaxation de contrainte (33) étant formée pour posséder une épaisseur comprise dans la plage allant d'environ 10 µm à environ 1 mm,
le procédé comprenant en outre :
le dépôt ou la croissance d'une seconde couche de relaxation de contrainte (35) constituée d'un métal sur le substrat de collage (31),
ledit collage du substrat de collage comprenant l'interposition des couches de matériau de collage (32, 34) entre la première électrode (24) et la première couche de relaxation de contrainte (33) et entre la première couche de relaxation de contrainte (33) et la seconde couche de relaxation de contrainte (35).
le collage de la seconde couche de relaxation de contrainte (35) constituée d'un métal entre la première couche de relaxation de contrainte (33) et la substrat de collage (31), ledit collage des première et seconde couches de relaxation de contrainte comprenant l'interposition des couches de matériau de collage (32, 34) entre la première électrode (24) et la première couche de relaxation de contrainte (33) et entre la première couche de relaxation de contrainte (33) et la seconde couche de relaxation de contrainte (35) ; ladite seconde couche de relaxation de contrainte (35) étant sur le substrat de collage (31).
REFERENCES CITED IN THE DESCRIPTION
This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.
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