The present invention relates to a control device for rectifiers of switching converters, in particular of resonant converters.

Resonant converters are a vast class of forced switching converters characterised by the presence of a resonant circuit that actively participates in determining the input-output power flow. In such converters a circuit consisting of a power switching bridge or half-bridge (typically of power MOSFETs), powered by DC voltage, generates a square wave voltage which is applied to a resonant circuit tuned to the fundamental frequency of said square wave. In this manner, because of its selective characteristics, the resonant circuit responds principally to this fundamental component and to a negligible degree to higher-order harmonics. It follows that the circulating power can be modulated by varying the frequency of the square wave, while maintaining the duty cycle constant at 50%, and that, according to the configuration of the resonant circuit, the currents and/or voltages associated with the power flow will have a pattern that is sinusoidal or piecewise sinusoidal. These voltages and/or currents are rectified and filtered so as to supply DC power to the load. In mains network applications, for reasons tied to safety regulations, the rectifier-filter system that supplies power to the load is coupled to the resonant circuit by means of a transformer that provides the isolation between source and load required under the aforesaid regulations. As in all isolated network converters, in this case as well it is customary to distinguish between a primary side (i.e. relating to the primary winding of the transformer) connected to the input source and a secondary side (i.e. relating to the secondary winding - or secondary windings - of the transformer) which supplies power to the load via the rectifier-filter system.

At present, one of the resonant converters most widely used is the LLC resonant converter, especially the half-bridge version. This name derives from the fact that the resonant circuit employs two inductors and one capacitor. The principle schematic of the half-bridge version is shown in figure 1, where a half-bridge of two transistors M1, M2 powered by an input voltage Vin and driven by a device 1, powers a series comprising a capacitor C, an inductance Ls and an inductance Lp, with a transformer 10 connected in parallel with the inductance Lp. The transformer has a secondary winding with a centre tap connected to ground GND, whereas the ends of the secondary winding are connected to rectifier diodes D1 and D2 having the cathodes connected together and to a parallel of a capacitor C1 and a resistance R, across which the output voltage Vout is present.

This converter, in addition to the typical advantages of resonant converters (waveforms without steep fronts, low switching losses of the power switches thank to "soft" switching), has significant advantages over converters which employ resonant circuits with only two reactive elements. In fact, said LLC converter is capable of working in a vast range of operating conditions with respect to input voltage and output current, including no load conditions, with a relatively small frequency variation; it has the possibility of achieving "soft" switching operations with all power switches in all operating conditions with respect to input voltage and output current. In fact as regards the power MOSFETs on the primary side one has zero voltage turn-on (ZVS - Zero Voltage Switching), hence zero associated losses, whereas as regards the rectifiers on the secondary side one has zero current turn-on and turn-off (ZCS, Zero Current Switching) and hence an absence of reverse recovery and the phenomena associated therewith. The turn-off switching losses of the primary side power MOSFETs are also rather low. Furthermore a further advantage is magnetic integration, i.e. the possibility of combining all of the magnetic devices (inductances and transformer) in a single physical component.

A synchronous rectifier implementing soft switching and preventing reverse power flow based on a safety time is described in US 6191964.

As a consequence of such properties, these resonant converters are characterised by a high conversion efficiency (>95% is easily achievable), an ability to work at high frequencies, low generation of EMI (ElectroMagnetic Interference) and, finally, a high power density (which means the possibility of constructing conversion systems of reduced volume).

In current types of converter circuits a high conversion efficiency and high power density are required, as in the case, for example, of the AC-DC adaptors of notebooks. LLC resonant converters are at present the converters that best meet such requirements.

However, the maximum efficiency achievable is limited by the losses in the rectifiers on the secondary side of the converter, which account for over 60% of total losses.

It is known that in order to significantly reduce the losses connected to secondary rectification, recourse can be made to the so-called "synchronous rectification" technique, in which one rectifier diode is replaced by a power MOSFET, with a suitably low turn-on resistance, such that the voltage drop across it is significantly lower than that across the diode, and driven in such a manner as to be functionally equivalent to the diode. This technique is widely adopted in traditional converters, especially in flyback and forward converters, for which there also exist commercially available dedicated integrated control circuits. There is an increasingly pressing need to adopt this technique in resonant converters as well, in particular in LLC converters, in order to enhance their efficiency as much as possible. Figure 2 shows the converter of figure 1 in the version with secondary synchronous rectifiers; in this case, in the place of diodes D1 and D2 there are two transistors T1 and T2, suitably driven by two signals G1 and G2 and connected between the terminals of the two parts of the centre-tapped secondary winding connected to ground GND, while the parallel of C1 and R is disposed between the centre tap of the secondary winding and ground GND. From a functional viewpoint there is no difference, as compared to the schematic in Figure 1. At the present state of the art, there exists no commercially available integrated control circuit specifically dedicated to driving synchronous rectifiers for LLC resonant converters.

To drive the power MOSFETs T1 and T2 as synchronous rectifiers in a resonant converter use is sometimes made of methods borrowed from traditional PWM controlled converters, based, that is, on the "self-driven" approach, in which the drive voltage of the synchronous rectifiers is obtained through the auxiliary windings of the transformer, and the "primary-driven" approach, in which the same signal which drives the primary side power MOSFET gates is used to drive the gates of the synchronous rectifiers on the secondary side. Both methods present major drawbacks. In the case of the self-driven approach, the drive voltage does not have steep fronts which determine fast switching (necessary especially at turn-off) so that, due to the delays, current reversals can be observed in the synchronous rectifiers. These reversals, by acting as a dummy load, discharge the output capacitors, thereby increasing the output voltage ripple and impairing efficiency at medium-low loads, a parameter that is of hardly negligible importance given the most recent legislation regarding the reduction of consumption. In addition, the current regime in the transformer and in the resonant circuit is altered and in certain conditions a loss of ZVS can be observed, with consequences that may range from a moderate increase in power dissipation in the primary-side power MOSFETs to the destruction thereof due to triggering of the parasitic bipolar transistor intrinsic to the structure of the power MOSFETs. In the case of the "primary-driven" approach, the converter functions correctly as long as the conduction of current in each synchronous rectifier occupies the entire switching half-period (CCM, Continuous Conduction Mode). Otherwise, that is if the conduction of current to the secondary winding occupies only a fraction of the switching half-period (DCM, Discontinuous Conduction Mode) the converter will no longer work correctly. In fact, if the same signal is used for the primary-side MOSFETs and the synchronous rectifiers, the latter will remain turned on even if the current falls to zero before completion of the half-cycle, resulting in a reversal of current along with the aforesaid drawbacks. This constitutes a severe limitation to the operating capabilities of the converter: in order to avoid working in DCM, not only is there the constraint of working within a narrow operating range, but it is also necessary for the load never to fall below a certain minimum value because, like all converters, also the LLC resonant converter tends to work in DCM, in the sense described just above, under a low load. Recently, more refined techniques have been developed with the aim of improving the drive logic of secondary synchronous rectifiers in this particular topology. Examples of these techniques are described in patents US7184280 and US7193866. In both cases the driving signals for the primary side power MOSFETs and for the synchronous rectifiers are generated by a single control circuit, which establishes their mutual relation. The fundamental drawback of such methods is that one or the other of the driving signals must cross the isolation barrier between the primary and secondary sides and hence the use of an additional transformer is necessary. In addition to this, neither of the two methods takes into account the fact that the current across the secondary diodes (and thus also in the synchronous rectifiers, if appropriately controlled) may be null not only in the final part of each switching half-cycle but also in the initial part. A final aspect, which is taken marginally into consideration in US7184280, is the advisability of suspending the synchronous rectification when the output current is low and entrusting the secondary rectification function either to the body diodes of the power MOSFETs used as synchronous rectifiers or Schottky diodes connected in anti-parallel with said synchronous rectifiers. In fact, with low currents, the reduction in losses associated with conduction across the turn-on resistance (as compared to the losses across the diode) is cancelled out by the loss of power used to drive the synchronous rectifiers.

In view of the state of the art, the object of the present invention is to provide a control device for rectifiers of switching converters which enables the rectifier to be driven in an autonomous manner, i.e. without any direct connection with the controller that provides driving signals of the transistor of the switching converter. In particular, where resonant converters are concerned, this avoids the use of an additional transformer to transfer the driving signals across the primary-secondary side isolation barrier.

According to the present invention, this object is achieved by means of a control device for a rectifier of a switching converter as defined in claim 1.

Thanks to the present invention it is possible to provide a control device for a rectifier of a switching converter, in particular for a resonant converter, which allows said rectifier to be driven in a manner such as to faithfully reproduce the behaviour of the rectifier diodes from the viewpoint of the currents in the transformer. Said control device is preferably able to autonomously recognise low load conditions for the converter and, in such a case, suspend driving of the rectifier in order to reduce the associated losses and resume driving as soon as the output current increases.

Said control device must therefore increase the conversion efficiency of an LLC-type resonant converter across a range of operating conditions as wide as possible.

The characteristics and advantages of the present invention will become apparent from the following detailed description of an embodiment thereof, illustrated solely by way of non-limitative example in the appended drawings, in which:

• figure 1 is a diagram of an LLC-type resonant converter with a centre-tapped secondary winding and full-wave rectification by means of diodes according to the known art;
• figure 2 is a diagram of an LLC-type resonant converter with a centre-tapped secondary winding and full-wave rectification by means of synchronous rectifiers according to the known art;
• figure 3 shows a block diagram of the control device for a rectifier of a switching converter according to the present invention;
• figure 4 is a more detailed diagram of a block of the control device of figure 3;
• figure 5 is a more detailed diagram of another block of the device of figure 3;
• figure 6 is a state machine relative to the functioning of the circuit block of figure 5;
• figure 7 is a more detailed diagram of a further block of the device of figure 3;
• figure 8 is a state machine relative to the functioning of the circuit block of figure 7.

With reference to figure 3, there is shown a control device for rectifiers of a switching converter, in particular rectifiers of resonant converters according to the present invention, and more particularly of LLC resonant converters as shown in figure 2. The LLC resonant converter is powered by a voltage Vin, preferably a DC voltage, and comprises a transformer 10 and an LLC resonant network (consisting of the inductances Ls and Lp and the capacitor C) coupled to the transformer 10, which has a primary winding 101 and a centre-tapped secondary winding 102; the transformer provides the output current lout of the converter. A rectifier comprising two transistors T1, T2 is coupled to the transformer 10, in particular to the secondary winding 102 of the transformer; more particularly, the transistors T1 and T2 are connected between the terminals of the two parts of the centre-tapped secondary winding 102 and ground GND. Said converter comprises a control device for the rectifier.

Said control device comprises a block 100 capable of detecting the start and end of each converter switching half-cycle and of measuring the length thereof and a block 200 suitable for generating a signal EN-SR for turning on the transistor T1 or T2 after a given number n of measured switching half-cycles of the converter and when the converter output current lout becomes greater than a reference current Iref. The control device preferably comprises a block 300 serving to impose the duration of the turn-on interval of the transistor T1 and of the transistor T2.

The block 100 has as its input parameters the voltages Vt1 and Vt2 across the drain terminals of the power MOSFETs T1, T2 used as synchronous rectifiers in the LLC converter of figure 2 and from the block 300 it receives a set of signals A0, A1..An indicative of the operating state of the aforesaid block within each switching half-cycle. Preferably, the block 100 receives as input a logical signal PG indicative of the operational or non-operational state of the resonant converter. The voltages Vt1 and Vt2 can preferably be read using the RDS(on) of T1 and T2, that is the sense resistors Rs connected in series to the drain terminals of the transistors T1 and T2 as shown in figure 3.

The output of the block 100 consists of a set of signals B0, B1..Bn, which may be analogue and/or digital depending on the configuration of the block 100. The start and end of each half-cycle is preferably obtained through means 111, 112 suitable for comparing the voltages Vt1, Vt2 with the voltage references VR1, VR2, where it is assumed that VR2 > VR1, as may be seen in figure 4. It is imposed that with Vt1<VR1 and Vt2>VR2 there will be the start of the current half-cycle in which the transistor T1 can be turned on whereas the transistor T2 must remain off and the end of the preceding half-cycle in which T2 may have been turned on while T1 had remained off; it is further imposed that with Vt2<VR1 and Vt1>VR2 there will be the start of the current half-cycle in which the transistor T2 can be turned on and transistor T1 remains off and the end of the preceding half-cycle in which T1 may have be turned on while transistor T2 had remained off. The means 113 which receive the outputs of the comparison means 111 and 112 are suitable for generating a pulse signal B0 of finite duration upon the occurrence of one or the other of the aforesaid conditions, indicated as the first and second condition, where the leading edge FS of the pulse B0 is interpreted as the end of the current conduction half-cycle and the trailing edge FD of the pulse B0 is interpreted as the start of the subsequent conduction half-cycle. The duration of each half-cycle, like every other time interval of interest (e.g. duration of the rectifier conduction period or of a certain fraction of the half-cycle), can be measured using any technique of the known art, for example using a high frequency clock synchronised with the pulses B0 or with analogue ramps that are reset on the leading edges FS of the pulses B0 and released on the trailing edges FD of said pulses.

The block 200 has the function of determining, based on the external signals Vt1, Vt2 and the signals B0, B1...Bn originating from the block 100, whether, respectively in the first and second condition described above, the synchronous rectifiers T1 and T2 must be turned on or not. To avoid asymmetries in converter behaviour, it is preferable that the logic of the block 200 be such that if the transistor T1 has been turned on upon occurrence of the first condition, the transistor T2 will likewise be turned on upon occurrence of the second condition, whereas if T1 is maintained in the off state, T2 must also be maintained in the off state. This ensures symmetrical behaviour of the two synchronous rectifier MOSFETs and counteracts the natural trend of the LLC half-bridge to magnify the effects of any asymmetry in its operation. The output of the block 200 is a logical signal EN-SR which determines whether the transistors T1 and T2 can be turned on in their respective cycles or must be kept in the off state.

The operation of the block 200 can be defined by means of a diagram shown in figure 5 and the state machine of figure 6.

When the signal PG is low the block 200 will be turned off, either because it is not sufficiently powered or because forcibly disabled from the outside; this state corresponds to state 19 of the state machine of figure 6. When the device turns on, i.e. with a high signal PG, because it is correctly powered and/or externally enabled to operate, all of the internal circuits will be turned on, the reference voltages will be generated and will adjust to their steady state value; this state corresponds to state 20 of the state machine of figure 6. The block 100, with a high signal PG, will become active, ready to identify the converter switching cycles and to measure the duration of each half-cycle. The block 100 also comprises means 115 (figure 4) able to count that a given number n (with n being a positive integer) of converter switching cycles have been identified and measured by the block 100; once the n converter switching cycles have been measured a signal B2 will be transmitted to the block 200, which is in state 30, i.e. the state in which the block 200 is turned on but in non-operational conditions.

The block 200 comprises means 202 serving to verify whether the converter output current Iout is greater than a given reference current Iref. In order to verify whether Iout>Iref two criteria implemented by the means 203 or 204 can be used. The means 203 are able to measure, with reference to the transistor T1, when the interval of time Td elapsing between the start of a half-cycle and the moment at which the body diode of the transistor T1 begins conducting becomes shorter than a predetermined time Tt1, which may also be equal to a predetermined fraction α of duration of the switching half-cycle THC. The means 204 are instead able to measure, again with reference to the transistor T1, whether the interval of time Tc elapsing between the moment at which the body diode of the transistor T1 begins conducting and the moment at which it ceases conducting exceeds a predetermined time Tt2, which may also be equal to a predetermined fraction α of duration of the switching half-cycle THC. It is possible to operate in the same manner with reference to the transistor T2. The time intervals Td and Tc are provided by the block 100 via the means 114 and are among the signals Bo, B1..Bn.

After n switching cycles have been measured and it has been verified that Iout>Iref, the block 200 will emit the logical signal EN-SR via the block 205, i.e. it will bring it to the high logical level; the block 300 will receive said signal EN-SR and enable the turning on of one of the transistors T1 or T2. The state corresponding to the emission of the signal EN-SR is state 40.

In the preferable case where the duration of the switching half-cycle is used as the term of comparison, it is possible to set EN-SR high either at the moment of completion of the measurement of the time interval under observation (Td or Tc), using the duration of the preceding half-cycle as THC, or at the moment of completion of the current half-cycle, in which case the measurement of Td or Tc will be held in memory and the THC value just acquired will be used.

The high-low transition of the signal EN_SR, which occurs when the output current Iout becomes lower than the current Iref, can be determined instead on the basis of criteria which identically mirror those used to determine the low-high transition thereof and with the same means 203 or 204: that is to say, either when the interval of time Td elapsing between the start of a half-cycle and the moment at which the body diode T1 begins conducting exceeds a predetermined time or, preferably, a predetermined fraction αof duration of the switching half-cycle THC, or when the interval of time Tc elapsing between the moment at which the body diode TR1 begins conducting (or, alternatively, the moment when T1 is turned on) and the moment at which T1 is turned off becomes shorter than a predetermined time or, preferably, than a predetermined fraction α of duration of the switching half-cycle THC.

It is preferable to wait for a given period of time, i.e. it is preferable that the condition for the transition of the signal EN-SR from high to low or vice-versa does not occur on the basis of the result of the comparison Td or Tc versus a percentage of THC in a single switching cycle, but rather that said result is confirmed for a certain number of switching cycles. This is implemented by means 206, which are configured to wait until the condition Iout>Iref is verified for a given number n2 (where n2 is a positive integer) of switching cycles.

It is likewise preferable that said number of switching cycles be different according to whether the transition of the signal EN-SR from low to high or its transition from high to low is considered. The disabling of synchronous rectifiers is something that regards conversion efficiency, and hence the steady state, whereas the enabling thereof also involves aspects regarding the dynamic characteristics of the converter (transient responses to load variations).

Therefore, it is desirable that the transition of the signal EN-SR from high to low occurs when the condition Td > α·THC (or Tc < α·THC) is met for n1 consecutive switching cycles while the transition of the signal EN-SR from low to high occurs when the condition Td < α·THC (or Tc > α·THC) is met for n2 consecutive switching cycles, with n2 < n1. The measurement of the numbers n1 and n2 of switching cycles is obtained via the means 206.

It is possible that the converter may function in an intermittent manner. In such a case, if the half-bridge stops switching, on the secondary side the transition fronts of the voltages Vt1 and Vt2 will cease to be present. It is thus desirable that, if the block 100 does not receive the synchronisation signals (and thus there is no longer the generation of pulses B0), the signal EN-SR be forced to low. This may be achieved either by using a "timeout" (for example, when there are no pulses B0 for longer than a predetermined time) or by bringing the signal EN_SR to low at the end of each conduction half-cycle and then bringing it back to high when the synchronism signal B0 is received and Iout>Iref.

The block 300 has the function of controlling, based on the external signals Vt1, Vt2 and PG, the signal EN-SR originating from the block 200 and the signals B0, B1...Bn originating from the block 100, how long the synchronous rectifiers T1 and T2 must be turned on. In order to avoid asymmetries in the converter behaviour, it is preferable that the logic of the block 300 be such that if the transistor T1 has been turned on upon occurrence of the first condition, the transistor T2 is likewise turned on upon occurrence of the second condition, whereas if T1 is maintained in the off state, T2 must also be maintained in the off state.

The operation of the block 300 can be defined by means of a scheme shown in figure 7 and a state machine, with reference solely to the transistor T1 in figure 8.

When the signal PG is low the block 300 will be turned off, either because it is not sufficiently powered or because forcibly disabled from the outside; this state corresponds to state 11 of the state machine of figure 7.

From state 11 there is a transition to state 12 when it is detected that the voltage Vt1 at the drain of T1 exceeds the reference value VR2 and this state will persist for the entire subsequent switching half-cycle in which T2 may conduct. From state 12 there will be a passage to state 13 on the leading edge of the pulse B0, i.e. when the start of the subsequent half-cycle is identified upon occurrence of the condition Vt1<VR1 and Vt2>VR2. During the time spent in this state, the block 300 will transmit, via means 301, a reset pulse A0 to the block 100 in order to reset all of the time measuring circuits 114, 115 of the block 100 following the acquisition of the duration of the switching half-cycle just determined.

On the trailing edge of the pulse B0 a passage to state 14 occurs.

The block 300 comprises means 302 suitable for turning off the device with a signal A1, that is, for going back from state 14 to state 11, if it is detected that the voltage Vt2 becomes lower than the reference value VR2. Should this occur, it means that the secondary voltages are reversing for some reason and T2 will turn on as soon as the voltage Vt2 becomes lower than VR1. To avoid the simultaneous conduction of the two synchronous rectifiers, the transistor T1 is not turned on (interlocking logic).

When the signal EN-SR=1 and when it is detected that the body diode associated with the transistor T1 is turned on, a passage to state 15 occurs. The block 300 comprises means 303 capable of sensing that the body diode associated with the transistor T1 is turned on; such means 303 compare the voltage Vt1 with a negative reference Vneg (e.g. -0.5V) and deliver an output signal A2. The ceasing of conduction of the body diode of the transistor T1 can be detected in the same way.

In order to be sure that the body diode of the transistor T1 is not turned on due to a spike, it is preferable that the passage to state 15 occurs when the turn-on condition is confirmed for at least a predetermined time period TH; this is ensured by the same means 303. The value of TH represents a compromise between the necessity of masking spikes and that of not overly delaying the turning on of the transistor T1, which would increase the conduction losses and impair efficiency.

The state remains in state 15 for a minimum time TONmin, during which the gate driver G1 will definitely be high and, accordingly, the transistor T1 will definitely be turned on; at the end of this time the passage to state 16 occurs.

From this state it is possible to evolve toward state 11, in the case where the signal PG is low, or where the voltage Vt2 becomes lower than the reference value VR2 (interlocking logic), or where the voltage Vt1 becomes positive or null; the comparison between the voltage Vt2 and the voltage VR2 takes place via the comparison means 112 of the block 100.

The transition from state 16 to state 17 is driven by the block 100 after a predetermined time Ts, which may also be equal to a percentage of the preceding switching half-cycle of the transistor T1 or of the transistor T2. The time Ts is set by the same means 115.

From state 17 the state may evolve toward state 11 if the voltage Vt1 becomes positive or null (reversal of current in the synchronous rectifier) or if Vt2 becomes lower than the reference value VR2 (interlocking logic); or else it may evolve toward a state 18 or a state 19. The decision as to the transition to be effected will be made at the moment the block 100 transmits a signal Tm, originating from the means 115 and corresponding to one half of the duration of the switching half-cycle. At this moment the voltage Vt1 will be compared with a negative reference value Vth close to zero (e.g. -25 mV) via means 305.

If the voltage Vt1 < Vth, there will be a transition to state 18, otherwise to state 19. At the halfway point of the switching half-cycle the current across the transistor T1 has not yet reached the peak value and is therefore still on the rise. State 18 will thus be reached when the current across the transistor T1 is of sufficient entity to give rise to a voltage drop greater than |vth| across its resistance RDSon, tha is the resistance between the drain and source terminals when the transistor is turned on, whereas state 19 will be reached when the current across T1 is not of sufficient entity and the voltage across its RDSon is lower than |Vth|. It is assumed that, in the former case, the converter is working in one of the modes associated with a high current regime, where the current derivative is also rather high, and that, in the latter case, it is working in one of the modes associated with a low current regime, where the derivatives, too, are less accentuated.

In the first case (Vt1<Vth), in order to avoid or minimise the current reversal in T1, it is advisable to turn off the latter in advance relative to the moment at which the current actually falls to zero; this is done so as to take into account the inevitable propagation delays of the zero and T1 turn-off sensing circuits. In fact, in this case T1 will be turned off and will pass from state 18 to state 11 when Vt1 > Vth.

In the second case (Vt1>Vth), the effect of the propagation delays is more limited and it is therefore not deemed necessary to turn off T1 in advance; T1 will be turned off as soon as the zero sensing circuits detect that Vt1 ≥0, an event that marks the passage from state 19 to state 11; the block 300 thus comprises means 306 serving to receive the output signal from the means 305 and able to turn off the transistor T1 by means of a signal Gloff if the voltage drop across the resistance RDSon of the transistor T1 is greater than |Vth|. The advantage of this differentiation of decisions is that, under intermediate loads, the conduction of transistor T1 will not be ended too early (halfway through the period), losing precisely the part in which the current is greatest. Obviously, starting off either from state 18 or state 19, the detection of the condition Vt2 < VR2 (interlocking logic) would lead in any case to state 11.

The decision process relative to the control of the synchronous rectifier T2 can be described by a state machine identical to the one considered for the transistor T1, except, possibly, for the fact that during its cycles the signal EN-SR is not updated.

The control device according to the invention can be used for any rectifier of a switching converter in which it is necessary to rectify the output current of the converter.