Current source and current source arrangement

Abstract

 A current source comprises an output terminal adapted to be connected to a load and a controllable output device connected to the output terminal. A first loop (Loop1) comprises a first sensing path having a sensing transistor (Ms1). A second loop (Loop2) comprises a second sensing path with a sensing transistor (Ms2) and a supply source to provide a supply signal (Vgen) at an output terminal thereof. The controllable output device (Mp) and the first and second sensing paths are coupled to the output terminal of the supply source. The first loop (Loop1) is adapted to provide a control signal (Vg) to the controllable output device and to the sensing transistor of the second sensing path. The second sensing path is coupled to the first sensing path and adapted to restrict the sensing transistor (Ms2) of the second sensing path to operate in a linear region of its characteristics.

Description

[0001] The present invention is related to a current source arrangement comprising a plurality of current source circuits.

[0002] Current sources are commonly used for several applications to provide voltage or current signals to a specific load. Often, such loads require voltages or currents which are different from a voltage or current supplied by a supply source. Such supply sources may include batteries for example. It is therefore common practice to power a current source with a charge pump voltage or a DC/DC converter to convert the voltage provided by a source to the required voltage for the load. For instance, mobile applications, including transmitters, receivers and the like, may require voltages and current signals different from the voltage and the current signal provided by a battery. Accordingly, current sources with DC/DC converters or charge pumps are used to provide the respective signals to the load. Further, current sources are often used for driving light emitting diodes.

[0003] The current source often comprises an adjustment device which receives the supply voltage and provides the respective voltage and current signals to the load. The adjustment device often comprises an adjustable restive element for the purpose of providing the current to the load. The voltage applied to said adjustment device and the current source, respectively, is therefore divided between the load and the adjustment device or current source itself. The loss of power across the current source may now increase with higher voltage drops across the adjustment device, which therefore reduces the overall efficiency.

[0004] Using DC/DC converters or charge pumps for a current source to provide a supply voltage to the adjustment device of the current source is preferably due to the high efficiencies of the DC/DC converters and charge pumps, respectively. However, the loss of power across the adjustment device may reduce this advantage.

[0005] It is therefore desirable to provide a new architecture for a current source which reduces the loss of power, therefore increasing the overall efficiency.

[0006] This and other objects of the present invention are resolved by the respective independent claims. Further aspects and embodiments are a subject matter of the dependent claims.

[0007] The proposed architecture provides a minimum voltage drop across the current source by generating only the minimum voltage required to drive current source and particular the adjustment device. In addition, multiple current sources can be used in an arrangement using a single power source as, for example, a DC/DC converter or a charge pump.

[0008] The proposed current source has a higher dynamic efficiency and can be used with any power source providing a supply voltage to the adjustment device of the current source which in turn provides the respective voltage and current signal to a load connected thereto. The control is accurate and preferably independent of external parameters like process variations or temperature variations.

[0009] In an embodiment, a current source comprises an output terminal which is adapted to be connected to a load. A controllable output device is connected to the output terminal to provide a respective output current signal to the load connected thereto. The current source further comprises a first loop having a first sensing path with a first sensing transistor. A second loop comprises a second sensing path with a second sensing transistor as well as the supply source to provide a supply signal at an output terminal thereof. The controllable output device and the first and the second sensing paths are coupled to the output terminal of the supply source. The first loop is now adapted to provide a control signal to the controllable output device and to the second sensing transistor. The second sensing path is coupled to the first sensing path and adapted to restrict the second sensing transistor to operate in a linear region of its characteristics.

[0010] The current source according to an embodiment therefore comprises two sensing paths, each of them having a sensing transistor arranged therein. While the first sensing transistor, being part of a first loop, is operated in saturation by a first loop control signal, the first loop also controls the adjustment device to provide the respective output signal to the load. At the same time, the second sensing path, being part of a second loop, which also includes the supply source, is operated in linear region of its characteristic and controls the supply source in such a way that a voltage drop across the adjustment device can be maintained to the lowest value possible to achieve a stable regulation of the adjustment device.

[0011] The current source according to an embodiment comprises a first loop and a second loop as well as an adjustment device wherein the first loop comprises a current sensing path to adjust an output current of the adjustment device. A sensing transistor in the first sensing path is controlled by the loop in such a way that it operates in a saturated region of its Source-Drain IV characteristics. A second sensing path with a second sensing transistor is used to control the output voltage of a supply source connected thereto.

[0012] The first loop further provides a control signal to the second sensing transistor of the second sensing path. In addition, the second sensing path comprises means to restrict the operation of its sensing transistor to operate in its linear region of its Source-Drain IV characteristics. In other words, the sensing transistor of the second sensing path is used as a variable resistance. Further, the second sensing path may be coupled to the first sensing path to control the first sensing transistor.

[0013] With the sensing transistor of the second sensing path connected to the supply source and operating in its linear region, its output current is linearly changing with the voltage provided by the supply source. Accordingly, the output voltage provided by the supply source will be set automatically so that regulation of the first and second loops is achieved. Particularly, the second loop comprising the second sensing path and the supply source is regulated in such way that a current given by the voltage difference between the drain source voltages of the sensing transistor of the first sensing path and the sensing transistor of the second sensing path is substantially maintained constant.

[0014] In an embodiment of the current source, the gate source voltages of the sensing transistors of both sensing paths are matched. Particularly, the dimensions of both sensing paths may be substantially equal or differ by a fixed and particularly an integer value.

[0015] In an embodiment, the first and the second sensing path may each comprise a second transistor, the gates of both second transistors being coupled via a voltage source. Said voltage source may provide a voltage restricting the sensing transistor of the second sensing path to operate in its linear region. The voltage source may therefore be arranged between the gates of both second transistors. The said voltage source may also be arranged in series with drain of second sensing transistor. In an embodiment, the current source may comprise a third loop having a comparator or differential amplifier coupled to the first sensing path and to the output terminal to provide a comparison signal to the gate of the second transistor in the first sensing path. Accordingly, the third loop is adapted to regulate the voltage within the first sensing path to the output voltage given by the external load connected to the output terminal of the current source.

[0016] In an embodiment, the adjustment device comprises an adjustment transistor. The adjustment transistor may be matched with the first sensing transistor of the first sensing path.

[0017] In a different embodiment, the first loop may comprise an additional comparator or differential amplifier adapted to receive an output current provided by the first sensing path and a reference current. An output of the comparator may provide the control signal. Additionally or alternatively, an output of the comparator may be coupled to the gate of the sensing transistor of the first sensing path, the adjustment input of the adjustment device and the gate of the sensing transistor of the second sensing path.

[0018] In another embodiment, the second loop may comprise a comparator or differential amplifier which is adapted to receive a reference current and an output current provided by the second sensing path. The comparator may provide an error signal based on a comparison of the received input signals. An output of the comparator is coupled to the supply source within the second loop. The supply source is adapted to control its output signal in response to said control signal. In this respect, the supply source of the second loop may comprise an adjustable DC/DC converter or an adjustable charge pump.

[0019] An adjustable DC/DC converter may comprise one or more amplifiers or comparators to compensate any deviation between an adjustment signal derived by the output current of the second sensing path and a reference current.

[0020] The second loop may also comprise a current/voltage converter adapted to receive a current provided by the second sensing path and to provide a respective voltage control signal thereof. The current/voltage converter is coupled to the adjustment terminal of the supply source.

[0021] Another aspect is related to multiple current sources driven by a DC/DC converter or a charge pump. Particularly a single supply source may provide the supply signal for a plurality of current sources, each of the coupled to a specific load. Logic may be provided to select a current source out of the plurality of current sources which is not yet regulated.

[0022] Such arrangement may comprise in an embodiment at least two current source circuits having an input terminal connected to an output terminal of a supply source, the supply source having an adjustment terminal. The at least two current source circuits may comprise the first loop as well as the second sensing path as indicated above. They may also comprise the third loop.

[0023] The arrangement may further comprise a multiplexer unit or a decoder unit which receives digital regulation signals as well as analog adjustment signals from the at least two current source circuits. In this respect, the regulation signal indicates whether the respective current source circuit and particularly the first loop have achieved regulation of the output current or not. In response thereof, the decoder logic may switch respective switches to apply the analog adjustment signal of the respective current source circuit to the adjustment terminal of the supply source. In an embodiment, the decoder may use a priority of offering locking to a current source circuit whose output voltage is expected to be higher than the other current sources output voltages.

[0024] Further embodiments and several aspects are now explained in greater detail with respect to the accompanying drawing in which

FIG. 1A

shows a schematic view of a current source according to a first embodiment,

FIG. 1B

shows diagram of an IV characteristic of the Source-Gate voltage to illustrate the operation of the sensing transistors,

FIG. 2

illustrates a second embodiment of the present invention,

FIG. 3

shows a schematic view of a third embodiment of the present invention,

FIG. 4

shows a schematic view of a fourth embodiment,

FIG. 4B

illustrates an IV source-drain diagram of the Source-Gate voltage to illustrate the operation of the sensing transistors,

FIG. 5

illustrates an embodiment of a voltage source used to restrict the sensing transistor to operate in its linear region,

FIG. 6

shows an implementation of the embodiment according to FIG. 1A in a more detailed view,

FIG. 7

shows a different implementation of the embodiment according to FIG. 1A,

FIG. 8

illustrates yet another implementation of the embodiment according to FIG. 1A,

FIG. 9

shows a further implementation of the embodiment according to FIG. 1A,

FIG. 10

illustrates an implementation of the embodiment according to FIG. 2,

FIG. 11

shows another implementation according to the embodiment of FIG. 2,

FIG. 12

to 14 illustrate embodiments of a DC/DC converter usable in the current sources according to the previous embodiments,

FIG. 15

to 17 show an illustration of regulated charge pumps usable in the current sources according to the present invention,

FIG. 18

shows an embodiment of an arrangement having a plurality of current source circuits according to the embodiment of the present invention,

FIG. 19

illustrates an embodiment of the decoder logic in accordance with embodiments of the present invention,

FIG. 20

shows a decoder input/output map in accordance with the previous embodiments.

[0025] In the following detailed description, several aspects of the present invention are explained in greater detail with reference to the accompanying drawings. However, those features shown in the figures are not restricted to the respective embodiments, but can be combined in different ways by a person skilled in the art. The switches for the current source according to the present invention are illustrated by simple field-effect transistors for illustration purposes. However, those switches are not restricted to field-effect transistors, but can be implemented in different ways including transmission gates, transistors of any kind and/or other devices for this purpose. The controlled charge pump as well as the DC/DC converter can be implemented in various ways and is therefore not restricted to any exemplary embodiment shown herein.

[0026] Some sub-circuits or elements are represented enlarged with respect to other elements. Such enlargement is for illustration purposes and does not reflect differences in real size when implementing those elements. The circuits and sub-circuits shown herein can be implemented in a single semiconductor body as an integrated circuit or as separated circuits using integrated as well as discrete components and devices.

[0027] FIG. 1A shows an embodiment of a current source according to the proposed idea. The current source comprises three regulation loops Loop1, Loop2 and Loop3. The current source comprises an adjustment device Mp, which in this case is illustrated as field-effect transistor. The device Mp may comprise one or more field-effect transistors arranged in parallel, transmission gates of other devices suitable for the purpose of implementing a variable resistance.

[0028] The adjustment device Mp is coupled to an output terminal of supply source 10 and provides an output voltage and current to an externally applied load 20. The gate of the adjustment device and transistor Mp receives a control voltage Vg which is provided by first loop Loop1. The first loop Loop1 comprises a first sensing path, a comparator or amplifier A1 and a first reference current source Ir1. The first sensing path includes a first current sensing transistor Ms1 connected in series to a second transistor M5. A drain terminal of the second transistor M5 is coupled to an non-inverting input of comparator A1. The inverting input of comparator A1 receives a reference current from reference source Ir1. The output of comparator A1 provides voltage control signal Vg to the gate of the current sensing transistor Ms1 in the first sensing path. The sensing transistor Ms1 is used to sense the current through the adjustment transistor Mp. As a result, the output current Ip is maintained constant with regulation of Loop1.

[0029] A third loop Loop3 is implemented using the transistor M5 of the first current sensing path and a second comparator or amplifier A2. While the output of second comparator A2 is connected to the gate of transistor M5, the inverting input receives a voltage signal Vd1 derived by the resistance of the transistors M5 and Ms1. So, the inverting input of second comparator A2 is connected to a node between transistors Ms1 and M5, respectively. The non-inverting input of comparator A2 is connected to the output terminal to receive the output voltage Vled. The third loop regulates voltage Vd1 of the first current sensing path to the output voltage Vled.

[0030] The loss of power across the adjustment device and the adjustment transistor is dependant on Vcurr, the voltage drop across the adjustment device Mp. This voltage is multiplied by current Ip drawn by load 20 through adjustment device Mp. Accordingly P_loss = Vcurr * Ip. Accordingly, the power loss P_loss may increase with the voltage drop across the adjustment transistor.

[0031] To reduce the power loss and thereby enhance efficiency, a second loop Loop2 is provided comprising a second current sensing path including a second current sensing transistor Ms2 and a second transistor M8 connected in series. The drain terminal of the second transistor M8 provides an output current Ifb which is applied to an I-V converter 11A to generate an adjustment signal Vset as well as a digital regulation signal VREG. The adjustment signal Vset is applied to supply source 10 for adjusting the output voltage signal Vgen generated by the power source 10. In addition, power source 10 is also coupled to an external power supply Vbat. The external power supply may comprise a battery for example.

[0032] In addition, second loop loop2 comprises a voltage generation device 15 arranged between the gate terminals of transistor M5 of the first sensing path and transistor M8 of the second sensing path. The voltage generation device may also be arranged between the drain terminal of Ms2 and source terminal of M8. The additional voltage generation device 15 is illustrated as a voltage source and provides a delta voltage Vδ, thereby restricting the second sensing transistor Ms2 to operate in a linear region of its I-V characteristics. The operation of current sensing transistor Ms2 of the second sensing path in its linear region results in regulation of output current Ifb of the second sensing path to a reference value Ir2 (not shown herein). A proper selection of delta voltage Vδ provided by voltage generation device 15 causes current sensing transistor Ms1 of the first sensing path to operate in saturation of its characteristics at the same time. With transistor Ms2 operating in its linear region, the current Ifb is linearly changing with the output voltage Vgen provided by the supply source. As a result the voltage Vgen applied to adjustment device Mp is adjusted such that adjustment device is still operating, but the voltage drop Vcurr is as small as possible thereby reducing power loss.

[0033] The operation of both transistors which preferably comprise the same source gate voltage are illustrated in FIG. 1B. The figure shows the IV-Source-Drain diagram of transistors Ms1 and Ms2 based on a pre-specified size S0. As illustrated, transistor Ms1 of the first sensing path is operating in its saturated region given by a minimum voltage drop Vds across Drain-Source where it can operate normally. In contrast thereto, transistor Ms2 is operating in its linear region. It should be noted that the basic units with Size S0 are shown herein. The difference between both operation points is given by Vδ and Iδ.

[0034] In steady state, the (basic) output current Ifb of the second sensing path is given by the difference of N_Ms2*(I0-Iδ), wherein 10 is a basic unit current in steady state.

[0035] The second sensing transistor Ms2 is matched with the first sensing transistor Ms1, particularly with respect to their Source-Gate voltage V_SG as indicated in FIG. 1B. However, their size ratio may differ with a fixed and particularly integer value. For instance, the size ratio is N_Ms2/N_Ms1 wherein N is a respective integer. Even with the size ratio as given, the steady state current in Ms2 and Ms1 does not have the same ratio. In fact, the current in the second sensing transistor Ms2 is regulated to a somewhat lower value. Accordingly, I_Ms2 is smaller than N_Ms2/N_Ms1 * I_Ms1. Hence, transistor Ms2 is actually operating in a linear region of its characteristics as illustrated in FIG. 1B.

[0036] The operation of transistor Ms2 of the second sensing path is achieved by the equation


wherein Vδ is a predetermined reference voltage given by the voltage generation device 15 and Vds is the source-Drain voltage across Ms2. As a result, the drain voltage of the first sensing transistor Ms1 is Vδ volts smaller than the drain voltage Vd2 of transistor Ms2 of the second sensing transistor. With the proper choice of Vδ, which is explained later in greater detail, it is possible that transistor Ms1 is operating in saturation and it can regulate current Is1 to the reference current of the first reference source Ir1 in the first loop with comparator A1.

[0037] Accordingly, if second loop Loop2 can achieve the regulation, then Loop1 regulation is guaranteed. The voltage drop Vcurr across the adjustment device and adjustment transistor Mp is by Vδ higher than the voltage drop across second sensing transistor Ms2. With minimum selection of Vδ given by the voltage generation device 15, which can maintain regulation of Loop1, the voltage drop across the adjustment device Mp can be maintained to lowest value. The output voltage of the supply source 10 will be set automatically so that all loops are stable.

[0038] The proper choice of Vδ can be achieved and determined by first defining a base unit device size S0 having a base current 10 through the basic device in steady state and size S0 = W0/L0 wherein W0 is the width of the basic device and L0 the length of the basic device. In a next step, the size of adjustment transistor Mp and the steady state current through Mp is determined. The size S_Mp is given by N_Mp * S0 wherein N_Mp is to be adjusted accordingly and an integer value. As a result, the steady state value of the current Ip is given by Ip = N_Mp * I0.

[0039] In a further step, the size of the first sensing transistor Ms1 is determined, wherein S_Ms1 = N_Ms1 * S0. Accordingly, the steady state value of current Is1 through the first sensing transistor is given by Is1 = N_Ms1 * I0. Then, the size S_Ms2 of the sensing transistor Ms2 of the second sensing path is determined by finding the respective integer value N_Ms2, wherein the size S_Ms2 = N_Ms2 * S0. The current Is2 through the sensing transistor Ms2 is not the steady state value Ifb, but a design variable.

[0040] In a next step, the minimum drain source voltage Vds(min) is determined. The minimum drain source voltage Vds(min) is given by Vgen, the output voltage of the supply source 10 minus the minimum output voltage Vled(min). The minimum drain source voltage Vds(min) corresponds to the minimum value at which Loop1 can regulate current Is1 through the sensing transistor Ms1 to the steady state value.

[0041] At this point, the source gate voltage V_SG is given by the difference between the output voltage Vgen-Vg wherein Vg is the output signal of the comparator A1 comparing a reference current Ir1 with the output current of the first sensing path. The found Source-Gate voltage V_SG is now used to plot the basic IV characteristics of the basic device as presented in FIG. 1B. The voltage Vδ to be generated by the voltage generation device 15 can be chosen from the above-mentioned characteristics. Accordingly, 10 can be determined by choosing the appropriate voltage drop Vδ. The second reference current Ir2 is now given by the current through the second sensing transistor Ir2 = Is2 - Iδ * N_Ms2, wherein Ir2 is the steady state value of the output current Ifb of the second sensing path.

[0042] Figure 5 illustrates an embodiment of the voltage generation device 15. The device comprises two current sources Ik. A first one is arranged between a terminal at which voltage Vgen is applied and a first output node connected to gate of transistor M8. A second one of the current source is arranged between ground terminal and a second node coupled to the gate of transistor M5. between both nodes a resistor Rk is provided. Said resistor may be adjustable. In any case a voltage drop as indicates occurs across resistor Rk, thereby generating voltage Vδ. Alternatively, any other method of generating voltage drop can be used to generate potential difference Vδ.

[0043] FIG. 2 illustrates another embodiment according to the present invention. In this embodiment, the output current Ifb of the second sensing path is applied to an I-V converter 11b (current voltage converter) providing an output voltage Vfb instead of an adjustment voltage Vset. The output voltage Vfb can be applied to an inverting input of an error amplifier included in the supply source 10. Said error amplifier can be part of a DC/DC converter or a charge pump, respectively.

[0044] FIG. 3 shows yet another embodiment of a current source according to the present invention. In this embodiment, an error signal Verr is generated directly using second loop Loop2. For this purpose, output current Ifb of the second sensing path is applied to an inverting input of a current comparator A4. The non-inverting input of the current comparator A4 receives a reference current provided by second reference current source Ir2. As seen in the previous equation, the output error current Ierr becomes zero if the output current Ifb of the second sensing path is in steady state and therefore corresponding to the reference current provided by the second reference current source Ir2.

[0045] In any case, the output error current Ierr is converted to an output voltage Verr using a capacitor CC which also works as a compensation capacitor. If the output current Ifb increases, then the error current Ierr decreases and vice-versa. The error voltage signal Verr is directly applied to the source 10. Accordingly, any additional error amplifier within the supply source 10 is not required. Particularly, the design of a DC/DC converter or charge pump can be simplified.

[0046] In addition to the adjustment signal Vset, the feedback signal Vfb or the error voltage signal Verr according to the embodiments, a second digital signal VREG is generated by the respective I-V converter 11a, 11b or 11c. Digital signal VREG is used to indicate whether the current source and particularly Loop1 of the current source has achieved regulation or has not achieved regulation. In this respect, a high value for signal VREG indicates a regulation for Loop1, while a low signal indicates that Loop1 has not yet achieved regulation.

[0047] For this purpose, the output current Ifb of the second sensing path is compared with an additional reference current. Said reference current Iref is chosen to be smaller than the current 10 used for the basic unit of sensing transistor Ms1 of the first sensing path but greater than the basic current flowing through the basic unit of a sensing transistor Ms2 of the second sensing path. It may be given by N_Ms2 * 10 > Iref > N_Ms2 * (I0 - Iδ).

[0048] In this respect, the basic unit is given by the respective currents through the first and second sensing transistors divided by the respective size values N_Ms1, N_Ms2. If the current Ifb is higher than the respective reference current, VREG becomes high. Otherwise, the control signal VREG is low.

[0049] A further, slightly different embodiment is presented in FIG. 4A. FIG. 4B illustrates the respective IV source drain diagram for the basic units of transistors Mp and Ms2. In this embodiment, a resistor method is used for regulation of a constant current in the adjustment transistor Mp. The second sensing transistor Ms1 is omitted. Particularly, adjustment transistor Mp is also used as sensing transistor Ms1 of the first sensing path given by adjustment transistor Mp and transistor M5.

[0050] The second sensing path is a series circuit including resistor Rd, second sensing transistor Ms2 and second transistor M8. The first sensing path comprises resistor Rsns, adjustment transistor Mp and second transistor M5. The size ratio of adjustment transistor Mp to sensing transistor Ms2 of the second sensing path is equal to the ratio of resistor RD to resistor Rsns. The voltage drop Vrsns across the resistor Rsns equals Viref. The source of the adjustment transistor Mp is connected to resistor Rsns and to an inverting input of a comparator or amplifier 16. A non-inverting input of comparator 16 is connected to voltage source Viref. Accordingly, the current through Rsns is maintained constant. The current through reference Ird connected to the output of the first sensing path is very small compared to a load current drawn by load 20. Accordingly, the load current is maintained constant. An alternative arrangement can consist of no Rd and the source of Ms2 and Mp can be connected together.

[0051] FIG. 6 shows a more detailed view of an implementation of FIG. 1A using field-effect transistors. The current source according to FIG. 6 comprises a supply source 10 generating an output voltage signal Vgen. Output voltage signal Vgen supplies first bias current source Ib1 and is also applied to the first sensing path, adjustment transistor Mp and transistor Ms2 of the second sensing path. Adjustment transistor Mp is connected with its drain terminal to the output terminal of the current source at which the load 20 is connected to. Output voltage Vled is derived by the resistance of load 20. The output terminal is also coupled to comparator A2 as illustrated in FIG. 1A, said comparator implemented by transistors M2, M6 and M7 as well as bias current sources Ib2 and Ib3. Particularly, the output terminal of the current source is coupled to source terminals of transistors M2 and M6. Transistor M6 is coupled with its gate to the drain terminal, thereby forming a diode. Drain terminal of transistor M6 is also coupled to source terminal of transistor M7. The gate of transistor M7 is connected to its drain terminal and coupled to a bias current source Ib4. The respective output voltage VC2 is applied to transistor M8 of the first sensing path as well as to transistor M5 of the second sensing path.

[0052] The output terminal of the current source is also connected to transistor M2, the gate of transistor M2 coupled to its drain terminal. The gate terminal is also connected to the gate terminal of transistor M1, said transistor M1 connected in series to transistor M5 and Ms1 of the first sensing path as well as to the voltage generation device 15. The other terminal of the voltage generation device 15 is connected to transistor M3, arranged between transistor M8 and Ms2 of the second sensing path.

[0053] Finally, Loop1 comprises transistor M4 connected to drain terminal of transistor M5 as well as the bias current source Ib2. The source of transistor M4 represents the output for providing the gate voltage Vg to sensing transistors Ms1, adjustment transistor Mp and sensing transistor Ms2. The gate of transistor M4 receives a first bias voltage Vb1.

[0054] In operation of the current source according to the embodiment of FIG. 6, transistor Ms2 is restricted to operated in a linear region due to voltage generation device 15. Output current Ifb of the second sensing path is mirrored in current mirror 50, said current mirror having current mirror ratio J1. The current mirror is connected to a supply terminal for receiving external supply voltage Vbat, which is also applied to supply source 10. Current mirror 50 comprises a first current mirror transistor M10 connected in series to a second current mirror transistor M9. A first terminal of current mirror transistor M10 is connected to a node between a reference current source Ir4 and drain terminal of transistor M8, said transistor being part of the second sensing path. Current mirror transistors M9 and M10 mirror the current to transistors M11 and M12 to provide an output current If. Transistor M12 is also connected to reference current source Ir5. A node between transistor M12 and reference current source Ir5 is coupled to the adjustment input of supply source 10.

[0055] In the embodiment, voltage Vd1 between transistor M1 and sensing transistor Ms1 of the first sensing path is equalized to the output voltage Vled using transistors M1, M2, M5, M6 and M7 together with bias current sources Ibl, Ib2, Ib3 and Ib4. The first loop Loop1 regulates the current Is1 to the difference of bias source current Ib2 - Ib1. Second sensing path including transistors Ms2, M3 and M8 is used to regulate the output voltage Vgen. If the current through sensing transistor Ms2 increases, the output voltage will increase resulting in a decrease of the adjustment voltage Vset.

[0056] Supply source 10, particularly a DC/DC converter or a charge pump, uses the adjustment voltage Vset as a reference voltage to increase or decrease output voltage Vgen of the supply source 10. Any increase in the output current Ifb from the steady state value is compensated by decreasing the output voltage Vgen.

[0057] The arrangement according to FIG. 6 allows providing output voltage Vled with lower values than other implementations and particularly the implementations according to FIG. 8 and 9.

[0058] FIG. 7 shows a slightly different implementation. In this embodiment, the reference source Ir5 is replaced by a constant resistor R. The resistor R functions as a current voltage converter resulting in a linear relationship between the output current Ifb and the adjustment voltage Vset.

[0059] FIG. 8 illustrates an embodiment which does not use intermediate current mirrors for the generation of the adjustment voltage Vset. In this embodiment, the drain terminal of transistor M8 providing the output current Ifb is connected to a first transistor and a second transistor arranged in series. The first transistor receives at its gate terminal a bias voltage vb2, thereby implementing a cascode. The gate of the second transistor is connected to the drain terminal of transistor M8. The output side also comprises first and second transistors. The first also receives bias voltage Vb2 while the second is connected to drain of transistor M8.

[0060] In any case, both second transistors mirror the current to respective output with ratio J3. A reference current Ir3 is connected to the first output transistor of the current mirror to provide the adjustment signal Vset to the respective adjustment input of supply source 10. Due to the presence of the diode in the path of output current Ifb, the circuit cannot be operated with low output voltages Vled applied to load 20.

[0061] In yet another embodiment according to FIG. 9, the relationship between the output current Ifb of the second sensing path and the adjustment signal Vset applied to the supply source 10 is made linear due to the presence of resistor R connected between ground terminal and the adjustment terminal of the supply source.

[0062] A different embodiment and an implementation according to FIG. 2 are illustrated in FIG. 10. The structure of Loop1 as well as of the comparators and the sensing paths are similar to the embodiments of FIG. 8 and 9.

[0063] In the embodiment, however, the drain terminal of transistor M8 being part of the second sensing path is connected to an I-V converter implemented by a resistor R. Particularly, resistor R is arranged between the drain terminal of transistor M8 and ground terminal. A node between transistor M8 and resistor R provides a feedback voltage Vfb to the adjustment input of the supply source 10. In summary, the implementation generates the feedback voltage Vfb instead of an adjustment signal Vset. The relation between the output current Ifb of the second sensing path and feedback voltage Vfb is linear and directly proportional due to the resistor R. Supply source 10 may comprise an error amplifier as explained in greater detail below.

[0064] A further embodiment which can achieve higher diode voltage operations is shown in FIG. 11. In this embodiment, the output current Ifb is mirrored by a first current mirror comprising transistors M9, M10 and M11, M12. Particularly, transistor M10 is connected to a node between reference current source IR4 and transistor M8 of the second sensing path. Output current Ifb is mirrored in transistor M9. Transistors M10 and M12 of the first current mirror receive a bias voltage at their gate terminals. Further, transistor M12 is connected to a reference current source providing the same reference current as the reference current source connected to transistor M8. Accordingly, the output current of the first current mirror is given by the current of reference current source Ir4 less the output current Ifb. Said current is again mirrored in a second current mirror having the same structure as the first current mirror. Particularly, size and current mirror ratio of the first and second current mirror may be substantially equal as indicated herein by the same reference signs. The output current Ifb of transistor M12 of the second current mirror generates a voltage drop through I-V converter R to provide a feedback voltage VFB to the supply source 10.

[0065] FIG. 12 shows an implementation of a DC/DC converter as a supply source using the adjustment signal Vset. The DC/DC converter according to the embodiment of FIG. 12 can be implemented in the current source according to FIG. 1A, 6, 7, 8 and 9.

[0066] The DC/DC converter may comprise an error amplifier ErrorAmp having a first input connected to the adjustment terminal to receive the adjustment signal Vset and a feedback signal Vfb. Said feedback signal is derived by a voltage divider comprising resistors R1, R2 which are arranged between the ground terminal and the output of the DC/DC converter. The resistive divider divides the output voltage Vgen of the converter to provide the feedback voltage Vfb. The error signal Ve provided by comparator ErrorAmp is applied to an adder unit 120, which also receives a compensation signal Vc for slope compensation as indicated in FIG. 12. The difference between the error signal Ve and compensation signal Vc is applied to an inverting input of a comparator 121. Comparator 121 is part of a feedback loop also comprising a digital control unit 123, the converter and a coil current sensing device 124. The digital control unit 123 receives also a clock signal for driving the converter. The feedback using the coil current sensing provides the required feedback signal to achieve a stable output voltage Vgen.

[0067] FIG. 13 shows a different implementation of a DC/DC converter. It can be used as a supply source for the current source according to the embodiments of FIG. 2, FIG. 10 and 11. The error amplifier 119 receives the feedback voltage signal Vfb and a reference signal which is externally applied.

[0068] In the embodiments which provide directly an error signal as shown in current source according to FIG. 3, the additional error amplifier in the DC/DC converter may be omitted. FIG. 14 shows a respective embodiment. In the embodiment the error signal Verr is applied directly to the adder 120.

[0069] It is also possible to use controlled charge pumps as supply sources as indicated in the previous embodiments. FIG. 15 illustrates a charge pump, which may be implemented in embodiments according to FIG. 1A, 8, 7, 6, 4A and 9. Again, error amplifier 119 receives the adjustment signal Vset and a feedback signal derived by a voltage divider comprising resistors R1, R2. The error signal Ve is converted to a frequency by a voltage-to-frequency converter 125 to provide a respective frequency-dependent clock signal to drive the charge pump.

[0070] FIG. 16 and 17 illustrate respective implementations to process the voltage feedback signal Vfb or directly the error signal Verr.

[0071] The present invention also allows implementing a plurality of current source circuits connected to a common supply source 10, each of them providing different output voltages Vled0, Vled1 and Vled2 dependent on the load connected thereto. Accordingly, current source circuits Cs0, Cs1 and Cs2 provide respective regulation signals VREG0, VREG1, VREG2 as well as adjustment signals Vset0, Vset1 and Vset2. In this respect, it is noted that the current source circuits Cs0, Cs1, Cs2 can be implemented using parts of the previous explained embodiments.

[0072] The arrangement in FIG. 18 shows multiple current source circuits Cs0, Cs1 and Cs2 driven by a single DC/DC converter, said converter being the supply source. The adjustment terminal of DC/DC converter 10 is connected to a plurality of switches 60, 61 and 62 arranged in parallel. Each switch is switched in response to a control signal Con0, Con1, Con2 each of them provided by decoder logic 70. Decoder logic 70 receives voltage regulation signals VREG0, VREG1 and VREG2 of the respective current source circuits. Switches 60, 61 and 62 may apply, in response to the respective control signals, adjustment signals Vset0, Vset1, Vset2 provided by the current source circuits to the adjustment terminal of the supply source 10.

[0073] Here, the corresponding regulation loop Loop2 is achieved with current source circuits Cs0, Cs1 and Cs2. Each load connected to the current source circuits may have different resistance, so the current provided by the circuits Cs0, Cs1 and Cs2 may differ as well. Accordingly, output voltages Vled0, Vled1 and Vled2 may differ. Current source circuits Cs may include the circuitry of loopl, loop3 and the second sensing path as described earlier.

[0074] The present invention proposes to use a decoder logic which automatically locks to the current source with the highest output voltage Vled. Such process will ensure a stable operation of all current sources implemented in this arrangement. The decoder logic 70 may use a priority of offering locking to a current source whose output voltage Vled is expected to be higher than the other current sources output voltages. Such a feature may reduce the time of locking the current source with the highest output voltage to the DC/DC converter.

[0075] Decoder logic 70 determines the state of the regulation signals VREG of each current source Cs0, Cs1 and Cs2. If two or more of those signals are at low level, the decoder logic determines the current source with the pre-specified highest priority and provides a respective control signal Con to one of the switches 60, 61 or 62. All other control signals will remain low.

[0076] If only one of the digital regulation signals VREG of the respective current source circuits is low, all others are high, the corresponding control signal Con for which the regulation signal VREG is low should be made high to close the respective switch, thereby connecting the respective adjustment signal to the adjustment terminal of supply source 10. This will provide a regulation of the supply source to the output voltage Vgen required to achieve a stable regulation. If no digital regulation signal VREG is low, the decoder logic will determine to stay in the last state and not change any control signals CON.

[0077] FIG. 19 shows the state diagram for the decoder logic according to the embodiment of FIG. 18.

[0078] FIG. 20 shows the decoder input/output map for different regulation signals VREG and the respective control signals CON. As can be seen, any input combination will end up the last state in which all current sources are regulated. In this embodiment, it is assumed that the first current source CSO has the highest priority. Accordingly, if two or more regulation signals are low, the decoder logic will switch the control signal Con assigned to the current source with the highest priority not yet regulated to high state. If only one regulation signal is low, the corresponding control signal for which the regulation signal is low is switched to high state. In any case, if one regulation signal VREG of any current source is high, the respective control signal Con assigned to that current source will not become high during the non-regulation state as seen in the decoder input/output map of FIG. 20.

[0079] The present invention allows providing current sources with higher efficiencies which can be used with any DC/DC converters or charge pumps. Combining a plurality of such current sources may provide a multiple current source arrangement which can particularly be supplied by a single supply source, for instance a single DC/DC converter or charge pump. The current source according to the present invention comprises a first loop controlling an adjustment transistor for providing the respective output current to a load connected thereto and a second loop. That second loop forces the supply source to generate an output voltage, which is set to a value small enough to reduce any power loss due to a voltage drop across the adjustment device of the current source.

Claims

1. A current source, comprising:

- an output terminal (Vled) adapted to be connected to a load;

- a controllable output device (Mp) connected to the output terminal;

- a first loop (loop1) comprising a first sensing path (Ms1, M5) having a sensing transistor (Ms1);

- a second loop (loop2), the second loop (loop2) comprising a second sensing path (Ms2, M8) with a sensing transistor (Ms2) and a supply source to provide a supply signal (Vgen) at an output terminal thereof, wherein the controllable output device (Mp) and the first and second sensing paths are coupled to the output terminal of the supply source (10);

wherein the first loop (loop1) is adapted to provide a control signal (Vg) to the controllable output device and to the sensing transistor of the second sensing path (Ms2, M8);
and wherein the second sensing path (Ms2, M8) is coupled to the first sensing path and adapted to restrict the sensing transistor of the second sensing path to operate in a linear region of its characteristic.

2. The current source according to claim 1, wherein the first sensing path (Ms1, M5) and the second sensing path (Ms2, M8) each comprise a second transistor (M5, M8), gates of both second transistors (M5, M8) being coupled via a voltage source (Vδ).

3. The current source according to any of claims 1 to 2, wherein the second sensing path (Ms2, M8) provides a sensing current (Ifb) dependent on a current (Iδ) derived by the difference of source-drain voltages of the sensing transistors (Ms1, Ms2) of the first and second sensing path (Ms1, M5, Ms2, M8) in operation.

4. The current source according to any of claims 2 to 3, wherein an output current (Ifb) of the second sensing path is dependant on a difference of steady states currents through the first sensing transistor and a current given by the voltage source.

5. The current source according to any of claims 1 to 4, wherein the gate-source voltages of the sensing transistor (Ms1) of the first sensing path (Ms1, M5) and the sensing transistor (Ms2) of the first sensing path (Ms2, M8) are substantially equal.

6. The current source according to any of claims 2 to 5, further comprising a third loop (loop3) comprising a comparator or amplifier (A2) coupled to the first sensing path (Ms1, M5) and the output terminal (Vled) to provide a comparison signal (Vc2) to the gate of the second transistor (M5) in the first sensing path (Ms1, M5).

7. The current source according to any of claims 1 to 6, wherein the supply source (10) comprises an adjustable charge pump or an adjustable DC/DC converter.

8. The current source according to any of claims 1 to 7, wherein the first loop (loop1) comprises a comparator or amplifier (A1) adapted to receive a current provided by the first sensing path (Ms1, M5) and a reference current (Ir1), an output of the comparator (A1) providing the control signal (Vg).

9. The current source according to any of claims 1 to 8, wherein the second loop (loop2) further comprises:

- a comparator or amplifier adapted to receive a current provided by the second sensing path (Ms2, M8) and a reference current (Ir2) to provide an error signal based on a comparison of the received input signals, an output of the comparator coupled to the supply source.

10. The current source according to any of claims 1 to 9, wherein the second loop (loop2) further comprises:

- a current/voltage converter adapted to receive a current provided by the second sensing path (Ms2, M8) and to provide a voltage control signal (Vset, Vfb) to the supply source.

11. The current source according to claim 10, wherein the current voltage converter comprises a current mirror adapted with its current mirror transistors (M9, M10) to receive the current provided by the second sensing path (Ms2, M8) and to provide a mirrored current to a resistive element.

12. The current source according to any of claims 1 to 11, further comprising a comparator to receive a signal derived by the output current of the second sensing path and to provide a digital output signal in response to a comparison of the signal with a reference signal, said reference signal in an interval, said interval dependant on the current through the first sensing transistor and the second sensing transistor.

13. Current source arrangement, comprising:

- a plurality of current source circuits, each of them comprising:

- an output terminal (Vled) adapted to be connected to a load;

- a controllable output device (Mp) connected to the output terminal;

- a first loop (loop1) comprising a first sensing path (Ms1, M5) having a sensing transistor (Ms1);

- a second sensing path (Ms2, M8) with a sensing transistor (Ms2) to provide an control signal (Vset, Ifb);

- a circuit to provide a digital indication signal (VREG) in response to a comparison of the control signal with a reference signal, said indication signal (VREG) indication whether a stable regulation of an output current of the respective current source circuit is achieved;

wherein the first loop (loop1) is adapted to provide a control signal (Vg) to the controllable output device and to the sensing transistor of the second sensing path (Ms2, M8);
and wherein the second sensing path (Ms2, M8) is coupled to the first sensing path and adapted to restrict the sensing transistor (Ms2) of the second sensing path to operate in a linear region of its characteristic;

- a controlled common supply source (10) to provide a supply signal to the plurality of current source circuits;

- a decoder (70) adapted to provide one of the control signals of the second sensing path of the plurality of current source circuits (Cs0, Cs1, Cs2) to the common supply source (10) in response to the indications signals (VREG).

14. The current source arrangement according to claim 13, wherein the decoder logic (70) is adapted to provide the control signal of the current source circuit of the plurality of current source circuits (Cs0, Cs1, Cs2) to the common supply source (10), which also provides an indication signal different from the indication signals of the other common supply source (Cs0, Cs1, Cs2) to the decoder logic (70).

15. The current source arrangement according to any of claims 13 to 14, wherein different priorities are assigned to each of the current source circuits (Cs0, Cs1, Cs2) and wherein the decoder logic (70) is adapted to provide the control signal of the current source circuit of the plurality of current source circuits (Cs0, Cs1, Cs2) to the common supply source (10) in response to the priorities, if all indication signals indicate that stable regulation is not achieved.

Drawing