METHOD FOR FABRICATING A POWER SEMICONDUCTOR DEVICE HAVING A VOLTAGE SUSTAINING LAYER WITH A TERRACED TRENCH FACILITATING FORMATION OF FLOATING ISLANDS - Patent 2232536

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EP 2 232 536 A1

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(43)	Date of publication:
	29.09.2010 Bulletin 2010/39

(21)	Application number: 08858220.0

(22)	Date of filing: 04.12.2008

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International Patent Classification (IPC):

H01L 21/26^(2006.01)

(86)	International application number:
	PCT/US2008/085509

(87)	International publication number:
	WO 2009/073773 (11.06.2009 Gazette 2009/24)

(84)	Designated Contracting States:
	AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MT NL NO PL PT RO SE SI SK TR
	Designated Extension States:
	AL BA MK RS

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Priority:

04.12.2007 US 950156

(71)	Applicant: Vishay General Semiconductor LLC
	Hauppauge, NY 11788 (US)

(72)	Inventors:
	BLANCHARD, Richard, A. Los Altos CA 94024 (US) GUILLOT, Jean-michel Cloyne (IE)

(74)	Representative: Jungblut, Bernhard Jakob et al
	Jungblut & Seuss Patentanwälte Max-Dohrn-Strasse 10 10589 Berlin 10589 Berlin (DE)

(54)	METHOD FOR FABRICATING A POWER SEMICONDUCTOR DEVICE HAVING A VOLTAGE SUSTAINING LAYER WITH A TERRACED TRENCH FACILITATING FORMATION OF FLOATING ISLANDS