(19)
(11) EP 2 278 590 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
02.03.2011 Bulletin 2011/09

(43) Date of publication A2:
26.01.2011 Bulletin 2011/04

(21) Application number: 08022019.7

(22) Date of filing: 18.12.2008
(51) International Patent Classification (IPC): 
G11C 16/02(2006.01)
(84) Designated Contracting States:
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MT NL NO PL PT RO SE SI SK TR
Designated Extension States:
AL BA MK RS

(30) Priority: 05.02.2008 US 026249

(71) Applicant: Qimonda AG
81739 München (DE)

(72) Inventors:
  • Happ, Thomas
    01109 Dresden (DE)
  • De Ambroggi, Luca
    81667 München (DE)
  • Kreupl, Franz
    80802 München (DE)
  • Schrögmeier, Peter
    81547 München (DE)
  • Steinlesberger, Gernot
    83624 Otterfing (DE)
  • Pho-Duc, Cristian
    85635 Höhenkirchen-Siegertsbrunn (DE)
  • Philipp, Jan Boris
    81673 München (DE)

   


(54) Integrated circuit including memory having limited read


(57) An integrated circuit including a memory with an array of memory cells, each memory cell comprising a non-volatile memory element; and a limited read circuit communicatively coupled to the array of memory cells.







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