(19)
(11) EP 2 400 498 A8

(12) CORRECTED EUROPEAN PATENT APPLICATION
Note: Bibliography reflects the latest situation

(15) Correction information:
Corrected version no 1 (W1 A1)

(48) Corrigendum issued on:
07.03.2012 Bulletin 2012/10

(43) Date of publication:
28.12.2011 Bulletin 2011/52

(21) Application number: 11171351.7

(22) Date of filing: 24.06.2011
(51) International Patent Classification (IPC): 
G11C 11/404(2006.01)
H01L 21/84(2006.01)
 H01L 29/786(2006.01)
H01L 27/12(2006.01)
(84) Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated Extension States:
BA ME

(30) Priority: 25.06.2010 US 358508 P
03.12.2010 US 419341 P

(71) Applicant: IMEC
3001 Leuven (BE)

(72) Inventors:
  • Lu, Zhichao
    Santa Clara, CA 95054 (US)
  • Collaert, Nadine
    3052 Blanden (BE)
  • Aoulaiche, Marc
    3001 Leuven (BE)
  • Jurczak, Malgorzata
    3001 Leuven (BE)

(74) Representative: Sarlet, Steven Renaat Irène et al
Gevers Intellectual Property House Holidaystraat 5
1831 Diegem
1831 Diegem (BE)

   


(54) Methods for operating a semiconductor device


(57) A capacitorless memory device based on a multi-gate MOSFET and requiring relatively low bias voltages. By providing a sufficient body factor and inducing a VT-feedback loop, using an accumulation layer to link threshold voltage with gate-to-body voltage, a hysteresis window (H) can be induced allowing the MOSFET to store '1' or '0' values (54, 51), and to read (within a program window PW) and hold (50) the stored values. The device operates with relatively low operating voltages such as 1.5V, high reliability e.g. 1016 operations, and long retention time such as ~5sec.