(19)
(11) EP 2 422 287 B8

(12) CORRECTED EUROPEAN PATENT SPECIFICATION
Note: Bibliography reflects the latest situation

(15) Correction information:
Corrected version no 1 (W1 B1)

(48) Corrigendum issued on:
01.07.2020 Bulletin 2020/27

(45) Mention of the grant of the patent:
20.05.2020 Bulletin 2020/21

(21) Application number: 10767488.9

(22) Date of filing: 31.03.2010
(51) International Patent Classification (IPC): 
G06F 30/367(2020.01)
G06F 119/10(2020.01)
H01L 21/768(2006.01)
H01L 27/02(2006.01)
G06F 30/392(2020.01)
G06F 119/18(2020.01)
H01L 21/8238(2006.01)
H01L 29/78(2006.01)
(86) International application number:
PCT/US2010/029326
(87) International publication number:
WO 2010/123659 (28.10.2010 Gazette 2010/43)

(54)

METHOD AND APPARATUS FOR PLACING TRANSISTORS IN PROXIMITY TO THROUGH-SILICON VIAS

VERFAHREN UND VORRICHTUNG ZUR PLATZIERUNG VON TRANSISTOREN IN DER NÄHE VON THROUGH-SILICON VIAS

PROCÉDÉ ET APPAREIL POUR PLACER DES TRANSISTORS À PROXIMITÉ DE TROUS D'INTERCONNEXION TRAVERSANT LE SILICIUM (TSV)


(84) Designated Contracting States:
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO SE SI SK SM TR

(30) Priority: 24.04.2009 US 430008

(43) Date of publication of application:
29.02.2012 Bulletin 2012/09

(73) Proprietor: Synopsys, Inc.
Mountain View, CA 94043 (US)

(72) Inventors:
  • SPROCH, James, David
    Monte Sereno CA 95030 (US)
  • MOROZ, Victor
    Saratoga CA 95070 (US)
  • XU, Xiaopeng
    Cupertino CA 95014 (US)
  • KARMARKAR, Aditya, Pradeep
    Hyderabad 50016 (IN)

(74) Representative: Epping - Hermann - Fischer 
Patentanwaltsgesellschaft mbH Schloßschmidstraße 5
80639 München
80639 München (DE)


(56) References cited: : 
US-A1- 2008 127 005
US-A1- 2009 070 728
US-A1- 2008 220 565
US-A1- 2009 091 333
   
  • Maxime Rousseau ET AL: "Through-silicon via based 3D IC technology: Electrostatic simulations for design methodology", , 16 April 2008 (2008-04-16), XP055157684, Retrieved from the Internet: URL:http://hal-cea.archives-ouvertes.fr/do cs/00/27/37/66/PDF/Rousseau_-_simulations_ for_design_methodology.pdf [retrieved on 2014-12-09]
  • PATRICK LEDUC ET AL: "Enabling technologies for 3D chip stacking", VLSI TECHNOLOGY, SYSTEMS AND APPLICATIONS, 2008. VLSI-TSA 2008. INTERNATIONAL SYMPOSIUM ON, IEEE, PISCATAWAY, NJ, USA, 21 April 2008 (2008-04-21), pages 76-78, XP031258823, ISBN: 978-1-4244-1614-1
  • CHUKWUDI OKORO ET AL: "Prediction of the Influence of Induced Stresses in Silicon on CMOS Performance in a Cu-Through-Via Interconnect Technology", THERMAL, MECHANICAL AND MULTI-PHYSICS SIMULATION EXPERIMENTS IN MICROE LECTRONICS AND MICRO-SYSTEMS, 2007. EUROSIME 2007. INTERNATIONAL CONFE RENCE ON, IEEE, PI, 1 April 2007 (2007-04-01), pages 1-7, XP031088097, ISBN: 978-1-4244-1105-4
  • NEWMAN M W ET AL: "Fabrication and Electrical Characterization of 3D Vertical Interconnects", ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE 2006, 56TH SAN DIEGO, CA MAY 30 - JUNE 2, 2006, PISCATAWAY, NJ, USA,IEEE, 30 May 2006 (2006-05-30), pages 394-398, XP010923362, DOI: 10.1109/ECTC.2006.1645676 ISBN: 978-1-4244-0152-9
  • BART VANDEVELDE ET AL: "Thermo-mechanics of 3D-wafer level and 3D stacked IC packaging technologies", THERMAL, MECHANICAL AND MULTI-PHYSICS SIMULATION AND EXPERIMENTS IN MICROELECTRONICS AND MICRO-SYSTEMS, 2008. EUROSIME 2008. INTERNATIONAL CONFERENCE ON, IEEE, PISCATAWAY, NJ, USA, 20 April 2008 (2008-04-20), pages 1-7, XP031255111, ISBN: 978-1-4244-2127-5
  • CHUKWUDI OKORO ET AL: "Analysis of the Induced Stresses in Silicon During Thermcompression Cu-Cu Bonding of Cu-Through-Vias in 3D-SIC Architecture", ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, 2007. ECTC '07. PROCEEDINGS. 57TH, IEEE, PI, 1 May 2007 (2007-05-01), pages 249-255, XP031180506, ISBN: 978-1-4244-0984-6
  • NEWMAN, M. W. ET AL.: 'Fabrication and Electrical Characterization of 3D Vertical Interconnects.' 2006 ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE. IEEE 2006, pages 394 - 398, XP010923362
   
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