ATBECHDEDKESFRGBGRITLILUNLSEMCPTIESILTLVFIROMKCY..TRBGCZEEHUPLSK..HRIS..MTNO....SM..................*JBDM Ver 1.7.2 (20 November 2019) - 2999001/02422287CORRECTED EUROPEAN PATENT SPECIFICATIONB8B120200701W173deBibliographieenBibliographyfrBibliographieEP10767488.9201003312011110920160624enenen43000820090424US2020070120202720120229201209202005202020212020022720200701202027G06F 30/367 20200101AFI20200211BHEP G06F 30/392 20200101ALI20200211BHEP G06F 119/10 20200101ALI20200211BHEP G06F 119/18 20200101ALI20200211BHEP H01L 21/768 20060101ALN20200211BHEP H01L 21/8238 20060101ALN20200211BHEP H01L 27/02 20060101ALN20200211BHEP H01L 29/78 20060101ALN20200211BHEP deVERFAHREN UND VORRICHTUNG ZUR PLATZIERUNG VON TRANSISTOREN IN DER NÄHE VON THROUGH-SILICON VIASenMETHOD AND APPARATUS FOR PLACING TRANSISTORS IN PROXIMITY TO THROUGH-SILICON VIASfrPROCÉDÉ ET APPAREIL POUR PLACER DES TRANSISTORS À PROXIMITÉ DE TROUS D'INTERCONNEXION TRAVERSANT LE SILICIUM (TSV)US-A1- 2008 127 005US-A1- 2008 220 565US-A1- 2009 070 728US-A1- 2009 091 333Maxime Rousseau ET AL: "Through-silicon via based 3D IC technology: Electrostatic simulations for design methodology", , 16 April 2008 (2008-04-16), XP055157684, Retrieved from the Internet: URL:http://hal-cea.archives-ouvertes.fr/do cs/00/27/37/66/PDF/Rousseau_-_simulations_ for_design_methodology.pdf [retrieved on 2014-12-09]PATRICK LEDUC ET AL: "Enabling technologies for 3D chip stacking", VLSI TECHNOLOGY, SYSTEMS AND APPLICATIONS, 2008. VLSI-TSA 2008. INTERNATIONAL SYMPOSIUM ON, IEEE, PISCATAWAY, NJ, USA, 21 April 2008 (2008-04-21), pages 76-78, XP031258823, ISBN: 978-1-4244-1614-1CHUKWUDI OKORO ET AL: "Prediction of the Influence of Induced Stresses in Silicon on CMOS Performance in a Cu-Through-Via Interconnect Technology", THERMAL, MECHANICAL AND MULTI-PHYSICS SIMULATION EXPERIMENTS IN MICROE LECTRONICS AND MICRO-SYSTEMS, 2007. EUROSIME 2007. INTERNATIONAL CONFE RENCE ON, IEEE, PI, 1 April 2007 (2007-04-01), pages 1-7, XP031088097, ISBN: 978-1-4244-1105-4NEWMAN M W ET AL: "Fabrication and Electrical Characterization of 3D Vertical Interconnects", ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE 2006, 56TH SAN DIEGO, CA MAY 30 - JUNE 2, 2006, PISCATAWAY, NJ, USA,IEEE, 30 May 2006 (2006-05-30), pages 394-398, XP010923362, DOI: 10.1109/ECTC.2006.1645676 ISBN: 978-1-4244-0152-9BART VANDEVELDE ET AL: "Thermo-mechanics of 3D-wafer level and 3D stacked IC packaging technologies", THERMAL, MECHANICAL AND MULTI-PHYSICS SIMULATION AND EXPERIMENTS IN MICROELECTRONICS AND MICRO-SYSTEMS, 2008. EUROSIME 2008. INTERNATIONAL CONFERENCE ON, IEEE, PISCATAWAY, NJ, USA, 20 April 2008 (2008-04-20), pages 1-7, XP031255111, ISBN: 978-1-4244-2127-5CHUKWUDI OKORO ET AL: "Analysis of the Induced Stresses in Silicon During Thermcompression Cu-Cu Bonding of Cu-Through-Vias in 3D-SIC Architecture", ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, 2007. ECTC '07. PROCEEDINGS. 57TH, IEEE, PI, 1 May 2007 (2007-05-01), pages 249-255, XP031180506, ISBN: 978-1-4244-0984-6NEWMAN, M. W. ET AL.: 'Fabrication and Electrical Characterization of 3D Vertical Interconnects.' 2006 ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE. IEEE 2006, pages 394 - 398, XP01092336220150623SPROCH, James, David18480 Bicknell RoadMonte Sereno CA 95030USMOROZ, Victor17035 Bohlman RoadSaratoga CA 95070USXU, Xiaopeng20220 Patric CourtCupertino CA 95014USKARMARKAR, Aditya, PradeepSynopsys (india)) Private Ltd. My Home Tycoon 4th Floor Block A Begumpet Andhra PradeshHyderabad 50016INSynopsys, Inc.101857495P2018,1236 EP N690 East Middlefield RoadMountain View, CA 94043USEpping - Hermann - Fischer101426474Patentanwaltsgesellschaft mbH Schloßschmidstraße 580639 MünchenDEATBEBGCHCYCZDEDKEEESFIFRGBGRHRHUIEISITLILTLULVMCMKMTNLNOPLPTROSESISKSMTRUS201002932620100331enWO201012365920101028201043