SYSTEM AND METHOD FOR MEASURING CAPACITANCE

Description

BACKGROUND

[0001] The present invention is generally directed to testing capacitance of a circuit. In particular, the present invention is directed to a device and method for detecting the capacitance of a circuit coupled to an output of a driving circuit.

[0002] Testing capacitance of a circuit has long been performed. Testing capacitance of a circuit coupled to an output of a driving circuit (e.g., an IC chip) has posted a new challenge. Nowadays, integrated circuits chips are widely used to control or drive a variety of actuators (e.g., micro actuator, MicroElectroMechanical Systems (MEMS) actuator). For example, ICs are used in electronic appliances such as cameras to control or drive a motor that drives an adjustable mechanical component (e.g., a lens). An actuator coupled to an IC chip may appear as a capacitor coupled to an output pin of the IC chip.

[0003] It would be desirable for an IC chip to test capacitance of a circuit coupled to an output of the IC chip (e.g., to determine on its own whether a load device is connected to chip pin before driving the pin with an activating current.) No known tests are available that provide a simple, inexpensive circuit for this purpose.

[0004] Related prior art is available in EP-A-0 652 445 and US-A-3 761 805.

[0005] Accordingly, there is a need in the art for a circuit that efficiently tests for capacitance of a circuit coupled to an IC pin with minimal complexity.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] 

FIGs. 1A and 1B are schematic diagrams of a capacitance sensing circuit in accordance with an exemplary embodiment of the present invention.

FIG. 2 is a graph illustrating exemplary signal outputs of a capacitance sensing circuit in accordance with an exemplary embodiment of the present invention.

FIG. 3 is a graph illustrating exemplary signal outputs of a capacitance sensing circuit in accordance with an exemplary embodiment of the present invention.

FIG. 4 is a flow diagram illustrating a process of using a capacitance sensing circuit in accordance with an exemplary embodiment of the present invention.

FIG. 5 is a schematic diagram of a capacitance sensing circuit in accordance with an exemplary embodiment of the present invention.

FIG. 6 is a graph illustrating exemplary signal outputs of a capacitance sensing circuit in accordance with an exemplary embodiment of the present invention.

FIG. 7 is a flow diagram illustrating a process of using a capacitance sensing circuit in accordance with an exemplary embodiment of the present invention.

DETAILED DESCRIPTION

[0007] According to the invention a system and method for testing capacitance of a load circuit connected to an output pin of a driving circuit are defined in claims 10 and 1 respectively.

[0008] FIG. 1A is a schematic diagram of a capacitance sensing circuit 100 in accordance with an exemplary embodiment of the present invention. The capacitance sensing circuit 100 may comprise an amplifier 102, a comparator 104 and a counter (e.g., timer) 108. The amplifier 102 may generate an output voltage that is applied to an output pin 110. The comparator 104 may compare the voltage applied to the output pin 110 to a reference voltage V_REF. In one embodiment, the capacitance sensing circuit 100 may be provided within a common IC chip. A load circuit (e.g. a load device modeled as capacitor 106 in FIG. 1) may be coupled to the IC chip via the pin 110.

[0009] The amplifier 102 may take an input signal V_IN at one input pin and take the output voltage V_OUT at another input pin via a feedback path. The output voltage V_OUT may match the input voltage V_IN with a response delay. The response delay may be affected by how fast the voltage V_OUT may match to the V_IN. Thus, the response delay may be affected by how fast the load circuit may be charged. In this embodiment, the charge current may be provided by the output current of the amplifier 102, which may be controlled by a current source 112. The current source 112 may provide a constant charge current I_CHARGE to the output electrical current of the amplifier 102. In one embodiment, the amplifier 102 may be a voltage output amplifier and the input V_IN may be coupled to an output from a digital to analog converter (DAC). In another embodiment, the feedback signal may be coupled via a resistive divider.

[0010] The comparator 104 and counter 108 may estimate the response time for the load circuit coupled to the pin 110 to be charged to a certain voltage. For example, if a load device (e.g., capacitor 106) is coupled to the pin 110, the load device may have a capacitance. The capacitance may be determined by the response delay for output voltage V_OUT to match the reference voltage V_REF. The output signal V_COMP of the comparator 104 may be coupled to an input pin of the counter 108. Another input pin of the counter 108 may be coupled to a clock signal F_CLK. Thereby, the counter 108 may count the response time (e.g., the response delay) for the output voltage V_OUT to match the reference voltage V_REF. Accordingly, the capacitance of the load circuit may be determined. In one embodiment, the counter 108 may be part of a decision logic (not shown) the capacitance sensing circuit 100 to estimate the capacitance of the load circuit coupled to the pin 110. The estimation of the capacitance may be based on the estimated response time for the load circuit coupled to the pin 110 to be charged to the reference voltage. In one or more embodiments, whether a load device may be present may be determined based on the capacitance.

[0011] In the embodiment as shown in FIG. 1A, the output signal V_OUT may be connected to the input pin of the comparator 104 directly for the comparator 104 to compare V_OUT to V_REF.

[0012] In another embodiment, the reference voltage used by the comparator 104 may be the input voltage V_IN. Thus, the output voltage V_OUT may be compared with the input voltage V_IN. The capacitance may be determined by the response delay for output voltage V_OUT to match the input voltage V_IN. However, as shown in FIG. 2(a), the rise of the output voltage V_OUT may not be linear when the level approaches the input voltage V_IN. Therefore, the output signal V_OUT may be connected to an input pin of the comparator 104 via an offset voltage V_OFF (shown in dashed lines).

[0013] FIG. 1B is a schematic diagram of showing the capacitance sensing circuit 100 with more detail in the output portion of the amplifier 102. The output portion of the amplifier 102 may comprise a transistor 114 and the current source 112 may be coupled to one terminal of the transistor 114. The output pin 110 may be coupled to another terminal of the transistor 114. The control terminal of the transistor 114 may be coupled to an output of the amplifier 102. In the embodiment shown in FIG. 1B, the transistor 114 may be a PMOS transistor. However, the transistor 114 is not limited to only PMOS transistors but may be a NMOS transistor or a bipolar transistor (either p-channel or n-channel).

[0014] In one embodiment, the capacitance sensing circuit 100 may comprise another transistor (e.g., a NMOS transistor, not shown) as a current sink coupling the drain of the PMOS transistor 114 to ground. The gate of the NMOS transistor may be coupled to the output of the amplifier 102 similar to the PMOS transistor 114. Because the PMOS transistor 114 may inverse the output signal of the amplifier 102, the positive and negative inputs to the amplifier 102 of Fig. 1B may be switched compared to the amplifier 102 of Fig. 1A to generate similar output signals at the output pin 110. Other components of the capacitance sensing circuit 100 shown in FIG. 1B may function similarly to the counterparts shown in FIG. 1A.

[0015] FIG. 2 illustrates exemplary waveforms that may be generated by the system of FIG. 1. For the embodiment shown in FIG. 2, the reference voltage V_REF may be set to be V_IN. FIG. 2(a) illustrates the output voltage V_OUT of the amplifier 102 generated in response to an input voltage V_IN. From time t₀ to time t₁, V_IN and V_OUT are at the same voltage level. At time t₁, V_IN may have a sudden change by an amount of ΔV. The output signal V_OUT will change during the time from t₁ to t₂ based on a capacitance C_OUT present at the output pin 110 as follows:

At some time later (t₂), V_OUT may reach to within a predetermined range of V_IN and lose the linear rising rate. The counter 108 may stop counting at the time t₂. The count value may be read from the counter 108 and analyzed to determine the value of C_OUT. If a load device is absent, the value of C_OUT will be low. V_OUT may reach V_IN almost instantly and a relatively low count value for the counter 108 will occur. By contrast, if a load device is present, a larger value of C_OUT will be observed and a higher count value will occur.

[0016] FIG. 2(b) illustrates the comparator's output signal V_COMP in response to waveforms of FIG. 2(a) when the output voltage V_OUT is connected to the comparator 104 via the offset voltage V_OFF. When the input voltage V_IN is greater than the voltage at the output pin V_OUT plus the offset voltage V_OFF, the counter 108 is enabled. FIG. 2(c) illustrates the counter 108 counting from time t₁ to time t₂, but being disabled from counting again at time t₂. At time t₂, the comparator 104 triggers when V_OUT reaches to within a predetermined range of V_IN. After time t₂, the count value may be maintained at the counter 108 until it is reset. In one embodiment, the counter 108 may be reset by a reset signal as shown in FIG. 1.

[0017] In one embodiment, the comparator 104 may be triggered when V_OUT reaches to within a threshold offset value V_OFF of V_IN. For the purpose of determining the capacitance C_OUT, an offset voltage V_OFF may ensure that the amplifier 102 is still slewing (e.g., voltage change is linear) when the comparator 104 triggers. Also, the signals of the amplifier 102 and the comparator 104 may have error sources and not be as ideal as shown in FIG. 2(a). Thus, the offset voltage V_OFF may provide a safety factor and may need to be bigger than a combined offset of the amplifier 102 and the comparator 104. The capacitance C_OUT present at the output pin 110 may be determined as follows:

[0018] In one or more embodiments, the capacitance C_OUT may vary with the applied voltage, thus, the input V_IN to the amplifier 102 may keep the pin 110 at a desired voltage V and a small ΔV may help to more accurately determine the capacitance close to the desired voltage V. On the other hand, the voltage change value ΔV may be limited by the offset voltage, because ΔV must be larger than the V_OFF.

[0019] In the exemplary embodiment shown in FIG. 1, V_IN may be connected to the inverting input and V_OUT may be connected to the non-inverting input of the comparator 104. However, in another embodiment, the connection may be switched, e.g., V_IN may be connected to the non-inverting input and V_OUT may be connected to the inverting input of the comparator 104, and the offset voltage V_OFF may be applied accordingly as well.

[0020] FIG. 3 illustrates exemplary signal outputs of the capacitance sensing circuit 100 in accordance with another exemplary embodiment of the present invention. In contrast to FIG. 2, for the embodiment shown in FIG. 3, the reference voltage V_REF may be set other than the input voltage V_IN. As shown in FIG. 3, at time t₁, the input V_IN may have a step change ΔV from an initial voltage level V. Also at time t₁, the reference voltage V_REF may be set to a level of V + ΔV₁ with ΔV₁ to be less than ΔV, and thus reference voltage V_REF to be less than the input voltage V_IN at time t₁. The time t₂ may be determined by triggering of the comparator 104 when the output voltage V_OUT matches the reference voltage V_REF of V + ΔV₁. The comparator 104 may trigger the counter 108 to start counting the time. At the time t₂, the reference voltage V_REF may be set to a new value V + ΔV₁ + ΔV₂, with ΔV₁ + ΔV₂ to be less than the input change ΔV and the rise of the output voltage V_OUT to be still linear. The comparator 104 may have a short response time t₃-t₂ to trigger again after the output voltage V_out does not match reference voltage V_REF any more. But at the time t₃, the counter 108 may not be affected and keep counting. At time t₄, the output voltage V_OUT matches to the reference voltage V_REF again and the comparator 104 may be triggered again. The counter 108 may then be triggered to stop counting at the time t₄. The capacitance C_OUT present at the output pin 110 may be determined by the equation of:

[0021] In one or more embodiments, the capacitance C_OUT may vary according to the voltage applied to the load circuit. In one embodiment, the output voltage V_out may be driven to a desired voltage by the input voltage V_IN. Then the step change ΔV may be applied to V_IN, and the two step changes ΔV₁ and ΔV₂ may be applied to reference voltage V_REF. The two step changes ΔV₁ and ΔV₂ may be equal or different but the output voltage V_OUT during these two changes may be linear. Using the two triggering of the comparator may help avoid system errors (e.g., slewing and/or response delay for the comparator) because the charge period is counted between the two triggering of the comparator when V_OUT twice matches to the reference voltage V_REF.

[0022] FIG. 4 illustrates a method 400 of using a load detector circuit in accordance with an exemplary embodiment of the present invention. The method 400 may start with step 402. At step 402, the method 400 configures an electrical circuit (e.g., a driving circuit) to drive a load circuit (e.g., a load device) with an amplifier. The amplifier may be, for example, a voltage output amplifier. As shown in FIG. 1, an exemplary embodiment may use the amplifier 102 to drive an external load device. The load device may be a motor with a capacitance C_OUT. The load device may be coupled to the output pin 110, which is electrically connected to output of the amplifier 102. Next, at step 404, the method 400 may load an input of the amplifier at a desired voltage V to perform capacitance sensing. In one or more embodiments, the capacitance of the load circuit C_OUT may vary with the applied voltage, thus, the capacitance sensing may be performed at or about the desired voltage.

[0023] From step 404, the method 400 may proceed to step 406. At step 406, the method 400 may generate a fast voltage change +ΔV at the input of the amplifier. As describe above, the amplifier's output voltage will rise in response to the voltage change ΔV at the input. Next, at step 408, the method 400 may limit the output current of the amplifier to I_CHARGE. Thus, the load circuit may be charged by a certain current I_CHARGE. In one embodiment, the charge current I_CHARGE may be controlled by a current source coupled to the output of the amplifier(as shown in FIG. 1). Next, the method 400 may proceed to step 410. At step 410, the method 400 may measure the time T_CHARGE it takes for the voltage at the output pin to have a voltage change ΔV' (e.g., ΔV - V_OFF in FIG. 2, or ΔV₂ in FIG. 3). For example, a comparator may compare the two inputs of the amplifier 102 as shown in FIG. 1. In one embodiment, an offset Voltage V_OFF may be added to the comparator. V_OFF may need to be bigger than the combined offset of the amplifier and the comparator. Also, an offset voltage V_OFF may ensure that the amplifier is still slewing when the comparator triggers. T_CHARGE may be t₂ - t₁ as shown in FIG. 2 or t₄ - t₂ as shown in FIG. 3.

[0024] At step 412, the capacitance C_OUT of the load device may be determined. In one embodiment, the voltage change ΔV' may be the input voltage change with an offset value (as shown in FIG. 2), the capacitance C_OUT may be calculated as follows:

In another embodiment, the voltage change ΔV' may be a change by the reference voltage V_REF, and the capacitance C_OUT may be calculated as follows:

In one or more embodiment, based on the capacitance C_OUT, a determination may be made as to whether the load device is present. For example, a threshold value for the C_OUT may be 300 picofarad (pF). That is, a C_OUT lager than 300 pF may be sufficient for the capacitance sensing circuit 500 to determine a load (e.g., a motor) is present. And a C_OUT less than 300 pF may show that a motor is absent.

[0025] FIG. 5 illustrates a capacitance sensing circuit 500 in accordance with an exemplary embodiment of the present invention. The capacitance sensing circuit 500 may comprise an amplifier 502, a comparator 504, a counter 508, a test switch 522, a current switch 524 and a current source 512. An output pin 510 may be coupled to the output of the amplifier 502, to which a load device 506 may be electrically connected. The comparator 504 may compare the voltage level V_OUT at the output pin 510 to a reference voltage V_REF. Based on the comparison, the counter 508 may count the time for the voltage level V_OUT at the output pin 510 to be charged to the reference voltage V_REF. In one embodiment, the counter 508 may be part of decision logic (not shown) of the capacitance sensing circuit 500 to estimate the capacitance of the load device 506. The estimation of the capacitance may be based on the estimated response time for the load circuit coupled to the pin 510 to be charged to the reference voltage.

[0026] In some embodiments, one input of the amplifier 502 may be coupled to an output from a digital to analog converter (DAC). A second input pin of the amplifier 502 may be coupled to the output signal V_OUT' of the amplifier 502 via a feedback path. During the operations, after the switch 522 is disconnected, the voltage level V_OUT at the output pin 510 may be different from the output signal V_OUT' of the amplifier 502. In one embodiment, the amplifier 502 may be a voltage output amplifier. In one embodiment, the DAC may be a 10 bits DAC (e.g., output having 2¹⁰ levels). Also, in one embodiment, the feedback signal may be coupled via a resistive divider.

[0027] During normal operations, the switch 522 may be on (e.g., connected) and the switch 524 may be off (e.g., disconnected). The amplifier 502 may drive the output (e.g., the load device 506 coupled to the output pin 510). The capacitance sensing components (e.g., the comparator 504, the counter 508 and the current source 512) may be in a standby mode.

[0028] In the capacitance sensing circuit 500, the current source 512 may be coupled to the output pin via the switch 524. This may be different from the capacitance sensing circuit 100 shown in FIG. 1, in which the charge current provided by the current source 112 may be provided via the output of the amplifier 102. In a capacitance sensing operation, the amplifier 502 may drive the output pin to a desired voltage level. Then the switch 522 may be turned off (e.g., disconnected) and the switch 524 may be turned on (e.g., connected). Afterwards, the reference voltage provided to the comparator may have a sudden change (e.g., a step change as shown in Fig. 6(a)). Thus, the output pin 510 and the external circuit (e.g., load device 506) may be driven by the current source 512. The current source 512 may be external to the amplifier 502 and not affected by the amplifier 502's operation. Thus, the rise of the output voltage V_OUT may rise linearly. In contrast, in an embodiment according to FIG. 1, when output voltage V_OUT (hence, the feedback input to the amplifier 102) gets closer the input voltage V_IN, the rise of the output voltage V_OUT may not be linear.

[0029] FIG. 6 illustrates exemplary signal outputs of the capacitance sensing circuit 500 in accordance with another exemplary embodiment of the present invention. As shown in FIG. 6, at time t₁, the reference voltage V_REF may be set to a level of V + ΔV₁ and the comparator 504 may trigger the counter 508 to start counting the time. Also at time t₁, the output voltage V_OUT at the output pin 510 may start rising in response to the switch 524 being turned on (e.g., connected) and thus the output pin 510 starting to be charged by the current source 512. At the time t₂, the output voltage V_OUT matches to the reference voltage V_REF and the comparator 104 may be triggered to send a signal to stop the counter 508. The capacitance C_OUT present at the output pin 110 may be determined by the equation of:

[0030] FIG. 7 illustrates a method 700 of using a load detector circuit in accordance with an exemplary embodiment of the present invention. The method 700 may be used by the capacitance sensing circuit 500. The method 400 may start with step 402. At step 402, the method 400 configures an electrical circuit (e.g., a driving circuit) to drive a load circuit (e.g., a load device) with an amplifier. The amplifier may be, for example, a voltage output amplifier. As shown in FIG. 5, an exemplary embodiment may use the amplifier 502 to drive an external load device. The load device may be a motor with a capacitance C_OUT. The load device may be coupled to the output pin 510, which is electrically connected to output of the amplifier 502 via a switch 522. Next, at step 704, the method 700 may load an input of the amplifier at a desired voltage V to perform capacitance sensing. In one or more embodiments, the capacitance of the load circuit C_OUT may vary with the applied voltage, thus, the capacitance sensing may be performed at or about the desired voltage.

[0031] From step 704, the method 700 may proceed to step 706. At step 706, the method 700 may disconnect the output pin 510 from the amplifier 502 and connect the output pin 510 to the current source 512. Thus, in FIG. 5, the switch 522 may be disconnected, switch 524 may be connected, and the current source 512 may start to charge the load circuit at the output pin 510 with a constant charge current I_CHARGE. Next, the method may proceed to step 508. At step 508, the method 700 may generate a fast voltage change +ΔV₁ at the input of the comparator 504 (e.g., the reference voltage V_REF is set to V+ΔV₁). But, as the switch 522 is disconnected, the output voltage V_OUT' from the amplifier 502 will not affect the charge rate for the output pin 510. Next, the method 700 may proceed to step 710. At step 710, the method 700 may measure the time T_CHARGE it takes for the voltage at the output pin 510 to reach the reference voltage V_REF (e.g., V + ΔV₁ in FIG. 6(a)). For example, the comparator 504 may control the counter 508 to count the charge time period between t₁ and t₂.

[0032] At step 712, the capacitance C_OUT of the load device may be determined. For example, based the voltage change ΔV1 of the reference voltage V_REF, and the capacitance C_OUT may be calculated as follows:

[0033] In one or more embodiments, a current source (e.g., current source 112, or current source 512) may be a current sink and the capacitance C_OUT at the output pin may be calculated (e.g., estimated) by a discharge current I_DISCHARGE. That is, a current sink (e.g., a current drain) may be coupled to the output pin to drain electrical charges from the output pin (e.g., a load coupled thereon) to ground. With a discharge current I_DISCHARGE, the voltage changes ΔVs as discussed above may be negative changes (e.g., decreases instead of increases). Triggering of the amplifiers and comparators may be similar but the discharging slope for the output voltage V_OUT may be a decline slope instead of a rising slope, and the counter may count time similarly by using reference voltages to start and/or stop, as for charging periods. The capacitance may be calculated using the absolute value of the voltage changes. For example, if no offset voltage is used, the capacitance may be calculated as follows:

[0034] Those skilled in the art may appreciate from the foregoing description that the present invention may be implemented in a variety of forms, and that the various embodiments may be implemented alone or in combination. Therefore, while the embodiments of the present invention have been described in connection with particular examples thereof, the true scope of the embodiments and/or methods of the present invention should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, specification, and following claims.

Claims

1. A method for testing a capacitance of a load circuit connected to an output pin of a driving circuit, said method being carried out on a system of any of claims 10 to 14, said method comprising:

driving a voltage at the output pin to a first voltage using a driving amplifier;

in response to receiving a sudden voltage change at an input of the driving amplifier, triggering an onset of a timed voltage change period;

applying a predetermined current to the output pin using the driving amplifier; comparing the voltage at the output pin to a reference voltage; and

when the voltage at the output pin matches the reference voltage, generating an estimate of the capacitance present at the output pin based on a number of clock cycles occurring between the onset of the timed voltage change period and the time at which the voltage at the output pin matches the reference voltage

wherein the timed voltage change period starts when the voltage at the output pin matches to a first value of the reference voltage after a sudden voltage change at an input of the voltage output amplifier and ends when the voltage at the output pin matches to a second value of the reference voltage.

2. The method of claim 1, wherein one of the following conditions applies:

a) the capacitance varies based upon the voltage at the output pin and the first voltage is a desired voltage for the load circuit;

b) the predetermined current is a charge current and the output pin is charged during the timed voltage change period;

c) the predetermined current is a sink current and the output pin is discharged during the timed voltage change period.

3. The method of claim 1, wherein comparing the voltage is performed by a comparator with a first input coupled to the output pin and a second input coupled to the reference voltage.

4. The method of claim 3, wherein the load circuit includes a motor and the output pin is driven to the first voltage by a voltage output amplifier, the voltage output amplifier outputs control signals from a digital-to-analog converter.

5. The method of claim 4, wherein a current source is provided in the voltage output amplifier and connected to the output pin in a current-limited mode.

6. The method of claim 1, wherein the output pin is coupled to an input of the comparator via an offset voltage and the reference voltage is equal to the first voltage and the sudden voltage change combined.

7. The method of claim 5, wherein the first value of the reference voltage is less than the second value of the reference voltage, and the second value of the reference voltage is less than the first voltage and the sudden voltage change combined.

8. The method of claim 4, wherein a current source is provided separate from the voltage output amplifier.

9. The method of claim 8, wherein the onset of the timed voltage change period is triggered by connecting the current source to the output pin, the reference voltage is equal to the first voltage and the voltage change combined.

10. A system for testing a capacitance of a load circuit coupled to an output pin of an electrical circuit, comprising:

a driving amplifier having an output coupled to the output pin, the driving amplifier being adapted to drive the output pin to an input voltage, wherein a first input of the amplifier is coupled to an input signal and a second input of the amplifier is coupled to the output of the amplifier;

a current source selectively coupled to the output pin, the current source being adapted to apply a current to the output pin during a testing period;

a comparator having inputs coupled to the output pin and to a reference voltage;

decision logic coupled to an output of the comparator, the decision logic being adapted to determine the capacitance present at the output pin based on a response of time of the voltage at the output pin,

wherein the decision logic includes a counter; and

wherein the counter is adapted to count a timed voltage change period for the output pin to match the reference voltage, and the decision logic is adapted to use the timed voltage change period, the charge current and rate of charge to determine the capacitance of the load circuit coupled to the output pin,

wherein the timed voltage change period is determined by starting the counter when the voltage at the output reaches a first value of the reference voltage after a step change is applied to the input signal, and stopping the counter when the voltage at the output pin reaches a second value of the reference voltage.

11. The system of claim 10, further comprising a first and second electrical switches wherein the output of the driving amplifier is coupled to the output pin via the first switch, and the current source is selectively coupled to the output pin via the second switch.

12. The system of claim 10, wherein the reference voltage is provided by the input signal, and the output pin is coupled to the comparator via an offset voltage.

13. The system of any of claims 10 to 12, wherein the timed voltage change period is determined by starting the counter when a step change is applied to the input signal and stopping the counter when the voltage at the output pin reaches the reference voltage minus the offset voltage.

14. The system of claim 11, wherein one of the following conditions applies:

a) the amplifier is a voltage output amplifier, the load circuit includes a motor and the amplifier outputs control signals for the motor from a digital to analog converter;

b) the capacitance of the external circuit varies with the voltage at the output pin;

c) the current is a charge current and the output pin is charged during the timed voltage change period;

d) the current is a sink current and the output pin is discharged during the timed voltage change period.

Ansprüche

1. Verfahren zum Testen einer Kapazität einer Lastschaltung, die mit einem Ausgangsstift einer Treiberschaltung verbunden ist, wobei das Verfahren an einem System nach einem der Ansprüche 10 bis 14 ausgeführt wird, wobei das Verfahren umfasst:

Ansteuern einer Spannung am Ausgangsstift unter Verwendung eines Treiberverstärkers auf eine erste Spannung;

als Reaktion auf das Empfangen einer plötzlichen Spannungsänderung an einem Eingang des Treiberverstärkers, Auslösen eines Beginns einer zeitgesteuerten Spannungsänderungsperiode;

Anlegen eines vorbestimmten Stroms an den Ausgangsstift unter Verwendung des Treiberverstärkers;

Vergleichen der Spannung am Ausgangsstift mit einer Referenzspannung; und,

wenn die Spannung am Ausgangsstift mit der Referenzspannung übereinstimmt, Erzeugen einer Schätzung der Kapazität, die am Ausgangsstift vorhanden ist, basierend auf einer Anzahl von Taktzyklen, die zwischen dem Beginn der zeitgesteuerten Spannungsänderungsperiode und der Zeit, zu der die Spannung am Ausgangsstift mit der Referenzspannung übereinstimmt, auftreten,

wobei die zeitgesteuerte Spannungsänderungsperiode beginnt, wenn die Spannung am Ausgangsstift nach einer plötzlichen Spannungsänderung an einem Eingang des Spannungsausgangsverstärkers mit einem ersten Wert der Referenzspannung übereinstimmt, und endet, wenn die Spannung am Ausgangsstift mit einem zweiten Wert der Referenzspannung übereinstimmt.

2. Verfahren nach Anspruch 1, wobei eine der folgenden Bedingungen zutrifft:

a) die Kapazität variiert auf der Grundlage der Spannung am Ausgangsstift und die erste Spannung ist eine gewünschte Spannung für die Lastschaltung;

b) der vorbestimmte Strom ist ein Ladestrom und der Ausgangsstift wird während der zeitgesteuerten Spannungsänderungsperiode geladen;

c) der vorbestimmte Strom ist ein Senkenstrom und der Ausgangsstift wird während der zeitgesteuerten Spannungsänderungsperiode entladen.

3. Verfahren nach Anspruch 1, wobei das Vergleichen der Spannung durch einen Komparator durchgeführt wird, wobei ein erster Eingang mit dem Ausgangsstift verbunden ist und ein zweiter Eingang mit der Referenzspannung verbunden ist.

4. Verfahren nach Anspruch 3, wobei die Lastschaltung einen Motor umfasst und der Ausgangsstift durch einen Spannungsausgangsverstärker auf die erste Spannung getrieben wird, wobei der Spannungsausgangsverstärker Steuersignale von einem Digital-Analog-Wandler ausgibt.

5. Verfahren nach Anspruch 4, wobei eine Stromquelle im Spannungsausgangsverstärker vorgesehen ist und in einem strombegrenzten Modus mit dem Ausgangsstift verbunden ist.

6. Verfahren nach Anspruch 1, wobei der Ausgangsstift über eine Offset-Spannung mit einem Eingang des Komparators verbunden ist und die Referenzspannung gleich der Kombination der ersten Spannung und der plötzlichen Spannungsänderung ist.

7. Verfahren nach Anspruch 5, wobei der erste Wert der Referenzspannung kleiner ist als der zweite Wert der Referenzspannung und der zweite Wert der Referenzspannung kleiner ist als die Kombination der ersten Spannung und der plötzlichen Spannungsänderung.

8. Verfahren nach Anspruch 4, wobei eine Stromquelle getrennt vom Spannungsausgangsverstärker vorgesehen ist.

9. Verfahren nach Anspruch 8, wobei der Beginn der zeitgesteuerten Spannungsänderungsperiode durch Verbinden der Stromquelle mit dem Ausgangsstift ausgelöst wird, wobei die Referenzspannung gleich der Kombination der ersten Spannung und der Spannungsänderung ist.

10. System zum Testen einer Kapazität einer Lastschaltung, die mit einem Ausgangsstift einer elektrischen Schaltung verbunden ist, umfassend:

einen Treiberverstärker mit einem Ausgang, der mit dem Ausgangsstift verbunden ist, wobei der Treiberverstärker geeignet ist, den Ausgangsstift auf eine Eingangsspannung zu steuern, wobei ein erster Eingang des Verstärkers mit einem Eingangssignal verbunden ist und ein zweiter Eingang des Verstärkers mit dem Ausgang des Verstärkers verbunden ist;

eine Stromquelle, die selektiv mit dem Ausgangsstift verbunden ist, wobei die Stromquelle ausgelegt ist, einen Strom am Ausgangsstift während einer Testperiode anzulegen;

einen Komparator mit Eingängen, die mit dem Ausgangsstift und mit einer Referenzspannung verbunden sind;

Entscheidungslogik, die mit einem Ausgang des Komparators verbunden ist, wobei die Entscheidungslogik ausgelegt ist, um die Kapazität zu bestimmen, die am Ausgangsstift vorhanden ist, basierend auf einer Zeitantwort der Spannung am Ausgangsstift, wobei die Entscheidungslogik einen Zähler aufweist; und

wobei der Zähler ausgelegt ist, um eine zeitgesteuerte Spannungsänderungsperiode für den Ausgangsstift zum Angleich an die Referenzspannung zu zählen, und die Entscheidungslogik ausgelegt ist, um die zeitgesteuerte Spannungsänderungsperiode, den Ladestrom und die Ladungsrate zu verwenden, um die Kapazität des Lastschaltkreises, der mit dem Ausgangsstift verbunden ist, zu bestimmen,

wobei die zeitgesteuerte Spannungsänderungsperiode durch Starten des Zählers, wenn die Spannung am Ausgang einen ersten Wert der Referenzspannung erreicht, nachdem eine wesentliche Veränderung am Eingangssignal angelegt wurde, und Stoppen des Zählers, wenn die Spannung am Ausgangsstift einen zweiten Wert der Referenzspannung erreicht, bestimmt wird.

11. System nach Anspruch 10, des Weiteren umfassend einen ersten und einen zweiten elektrischen Schalter, wobei der Ausgang des Treiberverstärkers über den ersten Schalter mit dem Ausgangsstift verbunden ist und die Stromquelle über den zweiten Schalter selektiv mit dem Ausgangsstift verbunden ist.

12. System nach Anspruch 10, wobei die Referenzspannung durch das Eingangssignal bereitgestellt wird und der Ausgangsstift über eine Offset-Spannung mit dem Komparator verbunden ist.

13. System nach einem der Ansprüche 10 bis 12, wobei die zeitgesteuerte Spannungsänderungsperiode durch Starten des Zählers, wenn eine wesentliche Veränderung am Eingangssignal angelegt wird, und Stoppen des Zählers, wenn die Spannung am Ausgangsstift die Referenzspannung minus der Offset-Spannung erreicht, bestimmt wird.

14. System nach Anspruch 11, wobei eine der folgenden Bedingungen zutrifft:

a) der Verstärker ist ein Spannungsausgangsverstärker, die Lastschaltung umfasst einen Motor und der Verstärker gibt Steuersignale für den Motor von einem Digital-Analog-Wandler aus;

b) die Kapazität der externen Schaltung variiert mit der Spannung am Ausgangsstift;

c) der Strom ist ein Ladestrom und der Ausgangsstift wird während der zeitgesteuerten Spannungsänderungsperiode geladen;

d) der Strom ist ein Senkenstrom und der Ausgangsstift wird während der zeitgesteuerten Spannungsänderungsperiode entladen.

Revendications

1. Procédé pour tester une capacité d'un circuit de charge connecté à une broche de sortie d'un circuit d'entraînement, ledit procédé étant réalisé sur un système selon l'une quelconque des revendications 10 à 14, ledit procédé comprenant :

- l'entraînement d'une tension au niveau de la broche de sortie à une première tension en utilisant un amplificateur d'entraînement ;

- en réponse à la réception d'un changement de tension soudain au niveau d'une entrée de l'amplificateur d'entraînement, le déclenchement d'un début d'une période de changement de tension temporisée ;

- l'application d'un courant prédéterminé à la broche de sortie en utilisant l'amplificateur d'entraînement ;

- la comparaison de la tension au niveau de la broche de sortie à une tension de référence ; et

- quand la tension au niveau de la broche de sortie correspond à la tension de référence, la génération d'une estimation de la capacité présente au niveau de la broche de sortie sur la base d'un nombre de cycles d'horloge survenant entre le début de la période de changement de tension temporisée et le moment où la tension au niveau de la broche de sortie correspond à la tension de référence

dans lequel la période de changement de tension temporisée commence quand la tension au niveau de la broche de sortie correspond à une première valeur de la tension de référence après un changement de tension soudain au niveau d'une entrée de l'amplificateur de sortie de tension et prend fin quand la tension au niveau de la broche de sortie correspond à une seconde valeur de la tension de référence.

2. Procédé selon la revendication 1, dans lequel l'une des conditions suivantes s'applique :

a) la capacité varie sur la base de la tension au niveau de la broche de sortie et la première tension est une tension souhaitée pour le circuit de charge ;

b) le courant prédéterminé est un courant de charge et la broche de sortie est chargée pendant la période de changement de tension temporisée ;

c) le courant prédéterminé est un courant absorbé et la broche de sortie est déchargée pendant la période de changement de tension temporisée ;

3. Procédé selon la revendication 1, dans lequel la comparaison de la tension est effectuée par un comparateur avec une première entrée couplée à la broche de sortie et une seconde entrée couplée à la tension de référence.

4. Procédé selon la revendication 3, dans lequel le circuit de charge comporte un moteur et la broche de sortie est entraînée à la première tension par un amplificateur de sortie de tension, l'amplificateur de sortie de tension sort des signaux de commande depuis un convertisseur numérique-analogique.

5. Procédé selon la revendication 4, dans lequel une source de courant est prévue dans l'amplificateur de sortie de tension et connectée à la broche de sortie dans un mode à courant limité.

6. Procédé selon la revendication 1, dans lequel la broche de sortie est couplée à une entrée du comparateur par l'intermédiaire d'une tension de décalage et la tension de référence est égale à la combinaison de la première tension et du changement de tension soudain.

7. Procédé selon la revendication 5, dans lequel la première valeur de la tension de référence est inférieure à la seconde valeur de la tension de référence, et la seconde valeur de la tension de référence est inférieure à la combinaison de la première tension et du changement de tension soudain.

8. Procédé selon la revendication 4, dans lequel une source de courant est prévue séparée de l'amplificateur de sortie de tension.

9. Procédé selon la revendication 8, dans lequel le début de la période de changement de tension temporisée est déclenché en connectant la source de courant à la broche de sortie, la tension de référence est égale à la combinaison de la première tension et du changement de tension.

10. Système pour tester une capacité d'un circuit de charge couplé à une broche de sortie d'un circuit électrique, comprenant :

- un amplificateur d'entraînement ayant une sortie couplée à la broche de sortie, l'amplificateur d'entraînement étant adapté pour entraîner la broche de sortie à une tension d'entrée, dans lequel une première entrée de l'amplificateur est couplée à un signal d'entrée et une seconde entrée de l'amplificateur est couplée à la sortie de l'amplificateur ;

- une source de courant couplée sélectivement à la broche de sortie, la source de courant étant adaptée pour appliquer un courant à la broche de sortie pendant une période de test ;

- un comparateur ayant des entrées couplées à la broche de sortie et à une tension de référence ;

- une logique de décision couplée à une sortie du comparateur, la logique de décision étant adaptée pour déterminer la capacité présente au niveau de la broche de sortie sur la base d'une réponse de temps de la tension au niveau de la broche de sortie,

dans lequel la logique de décision inclut un compteur ; et
dans lequel le compteur est adapté pour compter une période de changement de tension temporisée pour la broche de sortie pour qu'elle corresponde à la tension de référence, et la logique de décision est adaptée pour utiliser la période de changement de tension temporisée, le courant de charge et le taux de charge pour déterminer la capacité du circuit de charge couplé à la broche de sortie,
dans lequel la période de changement de tension temporisée est déterminée en démarrant le compteur quand la tension au niveau de la sortie atteint une première valeur de la tension de référence après qu'un changement d'étape est appliqué au signal d'entrée, et en arrêtant le compteur quand la tension au niveau de la broche de sortie atteint une seconde valeur de la tension de référence.

11. Système selon la revendication 10, comprenant en outre des premier et second commutateurs électriques dans lequel la sortie de l'amplificateur d'entraînement est couplée à la broche de sortie par le biais du premier commutateur, et la source de courant est sélectivement couplée à la broche de sortie par le biais du second commutateur.

12. Système selon la revendication 10, dans lequel la tension de référence est fournie par le signal d'entrée, et la broche de sortie est couplée au comparateur par le biais d'une tension de décalage.

13. Système selon l'une quelconque des revendications 10 à 12, dans lequel la période de changement de tension temporisée est déterminée en démarrant le compteur quand un changement d'étape est appliqué au signal d'entrée et en arrêtant le compteur quand la tension au niveau de la broche de sortie atteint la tension de référence moins la tension de décalage.

14. Système selon la revendication 11, dans lequel l'une des conditions suivantes s'applique :

a) l'amplificateur est un amplificateur de sortie de tension, le circuit de charge comporte un moteur et l'amplificateur sort des signaux de commande pour le moteur depuis un convertisseur numérique-analogique ;

b) la capacité du circuit externe varie avec la tension au niveau de la broche de sortie ;

c) le courant est un courant de charge et la broche de sortie est chargée pendant la période de changement de tension temporisée ;

d) le courant est un courant absorbé et la broche de sortie est déchargée durant la période de changement de tension temporisée.

Drawing