The invention relates to a phased array antenna signal processing structure, comprising a processor that includes a digital beam forming unit for generating partial beam data from digitized samples of a set of phased array antenna elements.
Digital beam forming in active electronic antenna arrays is complex. When the beam forming is performed in the digital domain, a central processor is heavily loaded both in terms of processing load and in communication load. Current implementations of analog and digital beam formers are very inflexible and poorly scalable. When the number of (phased array) antenna elements increases, the computational requirements of the used processor increases exceptionally.
It is noted that patent publication
It is an object of the invention to provide a more efficient signal processing structure according to the preamble for processing phased array antenna element data. Thereto, according to the invention, a phased array antenna signal processing structure according to claim 1 is provided.
By both generating partial beam data and adding intermediate beam data from another processor, the processing capacity as well as the communication load of the signal processing structure can be distributed, thereby optimally exploiting the processor capacity. Especially when the processors are communicatively connected in a ring structure for cyclically performing the adding function, all processors can in principle be loaded equally.
The processing functions that are needed for computing a digital beam can be effectively distributed over the available processors. Further, the processor according to the invention allows a highly scalable ring structure wherein the number of processors increases linearly with number of phased array antenna elements and the communication load remains the same. The structure is thus fully scalable regarding the number of digital beams, the number of phased array antenna elements and the number of processors. In addition, since only intermediate results are transmitted, there is a low communication load on array level while the communication between the processors is minimal. Further, a hierarchical beam forming structure can be realized without a hierarchy in the processor structure.
Further, the invention relates to a method according to claim 11.
In addition, the invention relates to a computer program product according to claim 16. A computer program product may comprise a set of computer executable instructions stored on a data carrier, such as a flash memory, a CD or a DVD. The set of computer executable instructions, which allow a programmable computer to carry out the method as defined above, may also be available for downloading from a remote server, for example via the Internet.
Other advantageous embodiments according to the invention are described in the following claims.
By way of example only, embodiments of the present invention will now be described with reference to the accompanying figures in which
The figures are merely schematic views of a preferred embodiment according to the invention. In the figures, the same reference numbers refer to equal or corresponding parts.
More specifically, the processor 2 includes a first set of input terminals 7 for receiving intermediate beam data 44a from a preceding processor in the ring 1, a first set of output terminals 8 for transmitting new intermediate beam data 44a to a subsequent processor in the ring 1, a second set of input terminals 9 for receiving digitized samples 12 of a phased array antenna set, a third set of input terminals 10 for receiving digital beam coefficients 11, a fourth set of input terminals 13 and a second set of output terminals 14 for receiving and transmitting, respectively, final beam data 44b.
In order to obtain the ring structure, the first set of input terminals 7 of a particular processor 2c are connected the first set of output terminals 8 of a preceding processor 2b in the ring 1. Similarly, the first set of output terminals 8 of the particular processor 2c are connected to the set of input terminals 7 of a subsequent processor 2d in the ring 1. Analogously, the fourth set of input terminals 13 and the second set of output terminals 14 of subsequent processors 2 in the ring structure 1 form the second set of communication lines for the final beam data 44b.
Each processor 2 contains the same number of input terminals in the second set of input terminals 9, so that each processor can process the same number of samples 12. In the shown example, the processor 2 includes 32 first input terminals 9, also called sample input channels. Then, the ring structure 1, including in the shown example 8 processors 2, is able to process 256 channels of digital samples. Thereto, a phased array antenna structure is split into 8 sets of phased array antenna elements, each feeding a corresponding processor 2.
Also the central unit 3 is provided with corresponding sets of input terminals and output terminals for receiving the intermediate beam data 44a and the final beam data 44b.
During operation of the ring structure 1 according to the invention, each processor 2a-h receives, via the second set of input terminals 9 digitized samples 12 from the corresponding set of phased array antenna elements. Thereto, the samples have been digitized using analog to digital converters ADC's. Each processor 2 processes the samples 12 to generate partial beam data. In this process, digital beam coefficients 11 are received via the third set of input terminals 10. The digital beam forming unit 5 includes a set of multipliers for multiplying the received samples 12 with corresponding digital beam coefficients 11. Further, the digital beam forming unit 5 includes a second adder for adding corresponding multiplied samples to generate partial beam data.
In order to obtain a digital beam, each sample is multiplied with a corresponding coefficient. Then, all multiplied samples are added. Thus, in each processor 2 receiving, in the shown embodiment, 32 samples, 32 multiplied samples are added. However, according to an aspect of the invention, a multiple number of digital beams can be computed. Thereto, the same samples 12 are also multiplied with other digital beam coefficients 11 to arrive at a second set of digital beam data. Preferably, the number of digital beams is in the same order as the total number of samples, in this example, 256 digital beams. The data that is generated in the digital beam forming unit 5 are called partial beam data, since the adding process has not yet been performed over all samples, but only over the samples that are received by a common processor 2. In the following, the process of adding the partial beam data is described.
The partial beam data 15 is internally transmitted to the first adder 6 that receives also intermediate beam data 44a from the preceding processor 2 in the ring structure 1, via the first set of input terminals 9. Using the first adder, the partial beam data 15 generated by the digital beam forming unit 5 is added to the intermediate beam data 44a to get a new update of the intermediate beam data 44a. Corresponding digital beam data are added, i.e. a summation is performed over partial beam data that relate to the same digital beam. The new update of the intermediate beam data 44a is transmitted to the next processor 2 in the ring structure 1. When this process is repeated, subsequently, by the eight processors 2, all digital beams have been computed. The data of the complete digital beams are called final beam data 44b.
According to an aspect of the invention, final beam data are generated by adding intermediate beam data received at a processor to corresponding partial beam data generated by the processor, wherein the intermediate beam data are based on corresponding partial beam data generated by all other processors in the ring 1. The final beam data 44b is transmitted via the second set of output terminals.
The central unit 3 obtains all blocks of final data 44b for further processing. The fully beam formed data referred to as final beam data available for further processing can be transmitted to units outside the ring structure. In a first embodiment, the final beam data can be transmitted to a single processor unit. However, the communication load is herewith locally increased. In a further embodiment, the final beam data are transmitted to a dedicated processor node embedded at any location in the ring structure. In yet a further embodiment, one or a few beam data sets are allocated to a single processor, so that the communication load is distributed over available processors. The latter method of communicating final beam data has the added advantage that any additional processing required per final beam data set (e.g. range-doppler processing) can be equally divided over processors as well.
In order to facilitate a proper time management of the data to be processed and transmitted, a number of further input terminals and output terminals can be provided. As an example, the processor might include terminals for time controlling signals and/or for reading data such as multiplication coefficients that have been input to the processor.
It is noted that, preferably, the number of first and second input terminals, and the number of first and second output terminals coincides to optimally benefit from digital I/O terminals in the processor 2. In a different embodiment the data passed between processors can contain time stamp data to align partial beam data and intermediate beam data.
As an example, the digital samples are received at a rate of 96 K samples per second, per ADC, each sample having 8 bits that are transmitted serially.
According to a further aspect of the invention, a defect in the performance of a specific processor in the ring structure can be detected. Then, the intermediate data and the final data can be transmitted by a preceding processor in the ring, towards a subsequent processor in the ring, thus circumventing the processor having the defect. Apparently, measures have to be taken to properly delay the data or time stamp the data, so that the other processors continue in meaningfully processing the intermediate results. Advantageously, by applying a data transfer by-pass, the ring structure can continue processing phased array antenna data, also with a defect processor, albeit with a reduced performance since the functionally eliminated processor and connected antenna element data do not contribute anymore in computing a digital beam.
In this respect it is noted that the steps of detecting a defect in the performance of a specific processor, and forwarding the intermediate data and final data transmitted by a preceding processor towards a subsequent processor can not only be performed in combination with a phased array antenna signal processing structure wherein a multiple number of processors are communicatively connected in a ring structure, but also, in combination with a more general phased array antenna signal processing structure wherein a multiple number of processors are communicatively connected in a chain structure.
The processor can be implemented in various ways, e.g. as an FPGA, an ASIC, a DSP or a general purpose processor, e.g. using a laptop.
transmitting (130) the new intermediate beam data to yet a further processor processing digitized samples received from a further set of phased arrays.
The method of processing phased array antenna digitized samples can be performed using dedicated hardware structures, such as FPGA and/or ASIC components. Otherwise, the method can also at least partially be performed using a computer program product comprising instructions for causing a processor of the computer system to perform the above described steps of the method according to the invention. All steps can in principle be performed on a single processor. However it is noted that at least one step can be performed on a separate processor, e.g. the step of transmitting the new intermediate beam data to yet a further processor processing digitized samples received from a further set of phased arrays.
The invention is not restricted to the embodiments described herein. It will be understood that many variants are possible.
It is noted that another number of processors and another total number of samples can be chosen. Further, another number of input terminals in the second set of input terminals of the processors can be chosen.
In addition, the processor can include further processing functions such as analog-digital conversion, calibration etc. Calibration can be implemented as an additional multiplication, for the sake of a simple design, or as an additional addition, for the sake of computational efficiency.
The digital beam forming unit can process on the real and imaginary part of the samples. Otherwise, also the amplitude and phase components can be processed. Further, by signal decomposition in frequency and phase components, an efficient Hilbert operation can optionally be applied.
Other such variants will be apparent for the person skilled in the art and are considered to lie within the scope of the invention as determined in the following claims.
This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.