(19)
(11) EP 2 654 261 B8

(12) CORRECTED EUROPEAN PATENT SPECIFICATION
Note: Bibliography reflects the latest situation

(15) Correction information:
Corrected version no 1 (W1 B1)

(48) Corrigendum issued on:
28.02.2018 Bulletin 2018/09

(45) Mention of the grant of the patent:
20.12.2017 Bulletin 2017/51

(21) Application number: 13158504.4

(22) Date of filing: 11.03.2013
(51) International Patent Classification (IPC): 
H04L 12/40(2006.01)
H04L 12/741(2013.01)
 H04L 29/06(2006.01)
H04L 12/26(2006.01)

(54)

Circuit for the fast analysis of packet headers transferred via a data bus

Schaltkreis für schnelle Analyse von über einen Datenbus übertragenen Paket-headern

Circuit pour une analyse rapide des en-tetes des paquets transférés par un bus de données

(84) Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30) Priority: 17.04.2012 CZ 20120264

(43) Date of publication of application:
23.10.2013 Bulletin 2013/43

(73) Proprietor: Cesnet, Zajmove Sdruzeni Pravnickych Osob
160 00 Praha 5 (CZ)

(72) Inventor:
  • Pus , Viktor
    66434 Kurim (CZ)

(74) Representative: Kratochvil, Vaclav 
Patent and Trademark Office P.O. Box 26
295 01 Mnichovo Hradiste
295 01 Mnichovo Hradiste (CZ)


(56) References cited: : 
EP-A1- 2 096 832
 JP-A- 2004 040 196
   
  • SHIMONISHI H ET AL: "A network processor architecture for flexible QoS control in very high-speed line interfaces", IEEE WORKSHOP ON HIGH PERFORMANCE SWITCHING AND ROUTING, 29 May 2001 (2001-05-29), pages 402-406, XP010542836, ISBN: 978-0-7803-6711-1
   
Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).