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(11) | EP 2 728 462 A3 |
| (12) | EUROPEAN PATENT APPLICATION |
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| (54) | Arithmetic logic unit |
| (57) An arithmetic logic unit (320) including a first routing grid (408) connected to
multiple data lanes (400) to drive first data to the data lanes (400). A second routing
grid (412) is connected to the data lanes (400) to drive second data to the data lanes
(400). Each of the data lanes (400) include multiple, e.g. N, functional units with
first inputs from the first routing grid and second inputs from the second routing
grid. The functional units compute pairwise a function of the respective first data
on the respective first inputs and the respective second data on the respective second
inputs. Each of the data lanes include a reduction unit with inputs adapted to receive
K' bits per word from the functional units. The reduction unit is configured to perform
a reduction operation configured to output an output result having a reduced number
J' bits per word, wherein J' is less than N multiplied by K'.
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