Voltage polarity detection for DCM/CCM boundary detection in DC/DC converters

Description

BACKGROUND

Technical Field

[0001] The present disclosure generally relates to DC/DC convertors and methods for DC/DC conversion. More particularly, it concerns a voltage polarity detection circuit adapted for the detection of Continuous Conduction Mode (CCM) to Discontinuous Conduction Mode (DCM) boundary of a switched DC/DC converter.

[0002] It finds application, for instance, in power-management platforms for wireless devices such as mobile phones, smart phones, digital audio players, PDAs, e-books readers, or the like.

Related Art

[0003] The approaches described in this section could be pursued, but are not necessarily approaches that have been previously conceived or pursued. Therefore, unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.

[0004] A DC/DC converter is an electronic circuit which converts a source of direct current (DC) from one voltage level to another, higher or lower voltage level. Electronic Switched Mode Power Supply (SMPS) circuits convert one DC voltage level to another, by controlling a switch to store the input energy temporarily and then release that energy to the output at a different voltage. The storage may be in either magnetic field storage components (inductors, transformers) or electric field storage components (capacitors). In magnetic DC/DC converters, the energy is periodically stored into and released from a magnetic field in an inductor or a transformer, typically in the range from 300 kHz to 10 MHz. By adjusting the duty cycle of the switching, i.e., the ratio of ON/OFF time of the switch, the amount of energy transferred to the output can be controlled. Usually, this is applied to control the output voltage, and therefore a switch driving circuit is adapted to sense the output voltage and generate a control signal for driving the switch.

[0005] With reference to Figures 1A-1C, SMPS circuits achieve synchronous DC/DC conversion by means a converter comprising an inductance L switched by at least one power switch S controlled by a pulse-width modulated control signal, a capacitor C, a flywheel diode D acting as a rectifier, and a switch driving circuit (not shown) adapted to generate the control signal. The power switch S may be a power Metal Oxyde Semiconductor (power-MOS) transistor of the N-conduction type (commonly referred to as a NMOS) or of the P-conduction type (commonly referred to as a PMOS).

[0006] Depending on the arrangement of the inductor L, switch S, capacitor C and rectifying diode D, the DC/DC converter can be of the Buck, Boost or Buck-Boost type. A DC/DC converter of the Buck type (as shown in Figure 1A) allows reducing a DC input voltage V_i or current to generate a lower DC output voltage or current. A DC/DC converter of the Boost type (as illustrated by Figure 1B) allows elevating a DC input voltage V_i or current to generate a higher DC output voltage or current. A DC/DC converter of the Buck-Boost type (as illustrated by Figure 1C) is capable of performing both functions. In all types of DC/DC converters, the feedback circuit is adapted to generate the PWM control signal based on the DC output voltage V_o (or current) across the load R, so as to regulate said DC output voltage (or current) to a desired value.

[0007] The efficiency of such DC/DC converters has increased thanks to the use of synchronous rectification, by replacing the flywheel diode with a power-MOS with lower ON-resistance, thereby reducing losses and allowing generation of supply voltages of lower value.

[0008] As shown in Figure 2, the switch S may be a PMOS power transistor M₃ arranged, in a power stage 10, in series with a NMOS power transistor M₂ acting as synchronous rectifier. Power transistors M₂ and M₃ are controlled by a driving signal CMD_N and a driving signal CMD_P, respectively. These signals may be generated by a Pulse-Width Modulation (PWM) unit 21 of the switch driving circuit 20, based on the output voltage V_o of the converter (not shown in Figure 2 in which only the inductance L of the DC/DC converter is represented), that is to say the voltage across the load R as shown in Figures 1A-1C. In a Step-down (Buck) DC/DC converter, the output voltage is lower than the input voltage, and of the same polarity. In a Step-up (Boost) DC/DC converter, the output voltage V_o is higher than the input voltage V_i. In a Single-Ended Primary-Inductor Converter (SEPIC) the output voltage V_o can be lower or higher than the input voltage V_i (Buck-Boost).

[0009] Discontinuous Conduction Mode (DCM) is a mode of operation of the DC/DC converter wherein in order to protect inductance current I_L against polarity inversion during the conduction cycle of the power switch S, the power stage is disconnected (said power stage is in high impedance state). Likewise, Continuous conduction Mode (CCM) is a mode of the operation of DC/DC converter wherein the inductance current I_L is not inverted during the conduction cycle. The converter operates in DCM when low current is drawn by the load R, and in CCM at higher load current levels. Indeed, when the amount of energy required by the load R is small enough to be transferred in a time lower than the switching period, the current through the inductor falls to zero during part of this period.

[0010] The DCM/CCM boundary detection is a fundamental functionality of each modern DC/DC convertor, enabling the convertor to be operated in various operating modes, for instance pure PWM mode or pulse-skipping mode. Pulse skipping mode is an operation mode which enables to decrease the power consumption of the DC/DC converter and thus to increase the battery-life of the mobile device, e.g, mobile phone. The accurate detection of the boundary between DCM and CCM is an important issue having a major role on the power efficiency and reliability of the DC/DC converter.

[0011] The boundary between the DCM and CCM is defined by the zero-valley inductor current, i.e. zero-current at the end of the NMOS conduction cycle. If this zero-current is not properly detected, the conduction on the PMOS transistor body-diode occurs, which considerably increases the power losses of the converter. In fact, when inductor current is inverted, the output capacitor is discharged by the power stage. This is opposite compared to the required features of the power stage, which is supposed to drive the power into the output capacitor during the whole PWM conduction cycle.

[0012] Therefore, and as shown further in Figure 2, the switch driving circuit 20 cooperates with a zero-current detection circuit 30, adapted to detect whether the inductor current I_L changes polarity during or at the end of the conduction period of the power switch, namely of the NMOS in the shown example. Said zero-current detection circuit 30 has an input 31 connected to the output of the power switch, i.e., the drain of the NMOS power transistor M₂ in the shown example, for receiving its V_DS voltage. Further, it has an output 32, whose output voltage V_OUT in indicative of the polarity of the V_DS voltage of the NMOS power transistor M₂, and is fed back to the switch driving circuit 20 along with the output voltage V_o of the DC/DC converter.

[0013] There are two methods which may be used in practice to detect the current polarity of the inductor current I_L at the end of NMOS conduction period. In a first method used in DC/DC convertors with low operating frequencies, the conduction on the body-diodes of the power-MOS is observed. In a second method suitable for DC/DC converters with higher switching frequency (when the non-overlapping time is not properly defined), the voltage V_DS on the power-MOS drain is observed.

[0014] The present disclosure addresses DC/DC converters relying on this second polarity detection method.

[0015] With reference to Figure 3, there is observed the polarity of the V_DS voltage at the end of the conduction of the switch S, i.e., at time t = T_CLK, where V_DS voltage refers to the drain-source voltage of the output NMOS power transistor. In the case of a negative voltage as shown by the curve in dotted line, no inversion occurs during the conduction period of the NMOS, which means that the converter operates in the CCM mode of operation. In contrast, when the voltage V_DS at the end of the NMOS conduction period is positive as shown by the curve in continuous line, inversion occurs, and the pulse skipping mode is preferred in order to increase the power efficiency of the converter.

[0016] The voltage V_Ds(t=TCLK) at the end of NMOS conduction period is equal to:

where R_{DS_N} is the ON-resistance of the power NMOS and is in order of 100 mΩ. It follows that polarity detection circuit must handle with very low voltage levels, with accuracy below 1 mV, and must therefore be extremely accurate.

[0017] Zero-current detection solutions known in the art are based on a comparator having a differential input pair. In order to ensure the required accuracy, this comparator must either be trimmed after fabrication (which is expensive) or must use a special design technique, leading to important silicon surface and current consumption. When the comparator is not trimmed, the system must exhibit a high robustness due to increased dispersion, which considerably lowers the power efficiency of the convertor. Sometimes, an additional sensing resistance is inserted to increase the V_DS voltage, which leads to additional power losses.

[0018] Other existing solutions also use sampling of the V_DS voltage at the end of NMOS conduction period, which is subsequently evaluated with a slower, but more accuracy, differential pair based comparator.

[0019] Reference US 2011/291632 discloses a power converter which includes a power converting unit and a switch driving circuit. A zero-current detector is configured to adjust the offset voltage based on a first detection voltage signal generated by a switch driving circuit and to generate a zero-current detecting signal based on the offset voltage. The offset voltage and the zero-current detecting signal are associated with a current in the power converting unit.

[0020] Stephen Bryson: "Using auto-zero comparator techniques to improve PWM performance (Part 1 of 2)" discloses using auto-zero comparator techniques to improve PWM control used in power management. To eliminate offset variation inherent in conventional CMOS comparator circuits, an auto-zeroing comparator is provided where a DRIVE signal is used in combination with a capacitor C1 for changing the status of an output comparison signal.

[0021] EP 0 049 024 A2 discloses an operational amplifier designed to eliminate the effects of voltage offsets, wherein a switched capacitor is provided in a feedback loop of the operational amplifier.

[0022] This solution requires a high performance, i.e., high speed and high accuracy comparator, however leading to high power consumption, or requires post-fabrication trimming of the comparator to enhance its quality. Obtaining such high quality comparator contributes to an important part of the DC-DC convertor design, and it costs lots of resources.

[0023] An accurate CCM to DCM boundary detection would allow to improve the converter device features such as efficiency, and reliability of the control. This is a challenging improvement in particular for the devices having very low resistance of power switches. The design of a new offset-free polarity detection circuit can allow further improvement of the DC-DC convertors efficiency, mainly for higher switching frequencies, as required by the new power-management platforms for e.g. wireless devices.

SUMMARY

[0024] These deficiencies are overcome, at least in part, by the invention defined in the subject matter of the independent claims. Advantageous embodiments are covered by the dependent claims.

[0025] To address these needs, embodiments of the proposed solution rely on detecting the inversion of the coil current at the end of the NMOS conduction cycle, defining the crossing of the DCM/CCM boundary, by using a design based on dynamic current mirror and auto-zero comparator providing an offset-free and very fast polarity detection.

[0026] More particularly, a first aspect relates to a voltage polarity detection circuit adapted for the detection of a Continuous Conduction Mode to Discontinuous Conduction Mode boundary of a power switch in a switched DC/DC converter, said circuit comprising:

• an input for receiving an input voltage representative of the conduction voltage of the power switch;
• an output for outputting a voltage polarity detection signal;
• a dynamic current mirror having an input connected to the input of the circuit through a first capacitor, and an output, said dynamic current mirror being controlled to store a voltage representative of the input voltage in the first capacitor at the end of a conduction cycle of the power switch; and,
• an auto-zero comparator having a first input connected to the output of the dynamic current mirror, a second input connected to a second capacitor, and an output connected to the output of the circuit, said auto-zero comparator being controlled to:
  • charge the output voltage of the dynamic current mirror into the second capacitor, during a first phase of operation corresponding to the conduction cycle of the NMOS power switch; and,
  • detect the polarity of the input voltage at the end of the first phase of operation, by comparing the voltage stored in the second capacitor with the output voltage of the dynamic current mirror in a second phase of operation corresponding to a non-conduction cycle of the power NMOS switch.

[0027] The dynamic current mirror acts as an input memory element and a first comparator stage, whereas the auto-zero comparator acts as a fast output stage providing additional voltage gain of the voltage polarity detection circuit. As it will become apparent from reading the following description of embodiments, the proposed circuit has the further advantages of having no inherent comparison offset and of having a very high detection speed (in the order of a few nanoseconds), along with very low power consumption.

[0028] A second aspect relates to a method of detecting a voltage polarity for the detection of a Continuous Conduction Mode to Discontinuous Conduction Mode boundary of a power switch used in a switched DC-DC converter, comprising:

• using a dynamic current mirror to store in a first capacitor a voltage representative of the conduction voltage of the power switch, at the end of a conduction cycle of the power switch; and,
• using an auto-zero comparator to:
  • charge the output voltage of the dynamic current mirror, into a second capacitor during a first phase of operation corresponding to the conduction cycle of the power switch; and,
  • detect, , the polarity of the conduction voltage of the power switch at the end of the first phase of operation, by comparing the voltage stored in the second capacitor during the first phase of operation with the output voltage of the dynamic current mirror in a second phase of operation corresponding to a non-conduction cycle of the power switch.

[0029] A third aspect relates to a DC-DC converter comprising a voltage polarity detection circuit according to the first aspect.

[0030] A fourth aspect relates to a wireless device comprising a Power Management Unit (PMU) having a DC-DC converter circuit according to the third aspect.

BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Embodiments of the present invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings, in which like reference numerals refer to similar elements and in which:

• Figures 1A, 1B and 1C are schematic views of a buck DC-DC converter, a boost DC-DC converter, and a buck-boost DC-DC converter, respectively.
• Figure 2 is a schematic view of a synchronous rectification DC-DC converter having a pull-up PMOS transistor and a pull-down NMOS transistor.
• Figure 3 is a graph of the drain voltage of the NMOS transistor as a function of time over the switching cycle of the DC-DC converter of Figure 2.
• Figure 4 is a schematic block diagram of a voltage polarity detection circuit used for the DCM/CCM boundary detection according to embodiments.
• Figure 5 are chronograms showing the waveform of the simplified schematic diagram from Figure 4.
• Figure 6 is a detailed schematic block diagram of a voltage polarity detection circuit used for the DCM/CCM boundary detection according to other embodiments.
• Figure 7 is a schematic block diagram of a wireless device incorporating a DC/DC converter as shown in Figure 4 or 6.

DESCRIPTION OF PREFERRED EMBODIMENTS

[0032] Various example embodiments will now be described more fully with reference to the accompanying drawings in which some embodiments are shown. The proposed inventive concepts may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, example embodiments are provided so that this disclosure is thorough and complete and fully conveys these inventive concepts to those skilled in the art.

[0033] Referring to Figure 4, there is shown therein a schematic block diagram of a voltage polarity detection circuit suitable for the DCM/CCM boundary detection according to embodiments of the proposed solution.

[0034] Embodiments rely on the association of a dynamic current mirror (also known as "current copier") together with a simple, i.e., low performance and low cost auto-zero comparator. In a dynamic current mirror, one and the same transistor is sequentially used at the input and the output of the mirror. Such current mirror is independent of the intrinsic and unavoidable mismatch between the at least two transistors of standard current mirrors or differential input pair, and thus has a very high accuracy. More details about dynamic current mirrors can be consulted in the book "Analogue IC Design: The Current-Mode Approach" - Chris Toumazou, F. J. Lidgey, David Haigh - 1993 - pp 302-303, Chapter 7.4 entitled "Principle of dynamic current mirrors".

[0035] In the contemplated implementation, the dynamic current mirror acts as the input memory element and a first comparator stage, whereas the auto-zero comparator acts as a fast output stage providing additional voltage gain of the voltage polarity detection circuit. As it will become apparent from reading the following description of embodiments, the proposed circuit has the further advantages of having no inherent comparison offset and of having a very high detection speed (in the order of a few nanoseconds), along with very low power consumption.

[0036] As shown in Figure 4, the voltage polarity detection circuit 10, also referred to as a zero-current detector in the present description, has an input 31 and an output 32. Only the NMOS power transistor M₂ of the power stage 10 is represented in Figure 4. Also, the switch driving circuit 20 as shown in Figure 2 is not represented in Figure 4, in order to keep the latter as simple and readable as possible. However, the one with ordinary skills in the art will understand that the proposed zero-current detector of Figure 4 is adapted to be substituted to the zero-current detector of Figure 2, namely may have its input 31 terminal and output terminal 32 connected to the same elements of the power stage 10 and the switch driving circuit 20 as described above with reference to Figure 2. More precisely, the input terminal 31 is connected to the output, i.e., the drain of the NMOS transistor M₂ of the power stage 10, and the output terminal 32 is connected to an input of the switch driving circuit 20 to feed-back the zero-current detection signal V_OUT.

[0037] In the embodiment shown if Figure 4, the power stage 30 further comprises a delay unit 11, which is adapted to delay the control signal CMD_N by a given time t₀. This ensures the absence of overlapping between the conduction periods of the power switch M₂ controlled by signal CMD_N on one hand, and power transistor M₃ controlled by the control signal CMD_P on the other hand.

[0038] Embodiments of the proposed polarity detection circuit 30 used for the detection of the Direct Current Mode (DCM) of the power switch M₂ comprise a dynamic current mirror and an auto-zero comparator, the combination of which provides a fast, accurate and offset-free polarity detection.

[0039] As shown in Figure 4, the dynamic current mirror may comprise a single NMOS transistor M₁, whose drain is connected to a current source 61 for receiving a constant current I₀ output from said current source. The source of M₁ is connected to the ground GND. The control gate of M₁ is connected to the input 31 of the circuit through a capacitor C₁ and a first switch SW₁. It is further connected to the ground GND through capacitor C₁ and a second switch SW₂. The control gate of M₁ is finally connected to its drain through a third switch SW₃. Let us call V_HZ the voltage at the node corresponding to the drain of transistor M1, which thus also corresponds to the output voltage of the dynamic current mirror.

[0040] Further, the auto-zero comparator may comprise a standard two stage Operational Amplifier (OA) whose non inverting input "+" is connected to the drain of M₁, whose inverting input "-" is connected to the ground through a capacitor C₂, and whose output is connected to its inverting input "-" through a fourth switch SW₄. Let us call V_C2 the voltage across capacitor C₂, and V_OUT the voltage at the output of the AO. Voltage V_OUT is also the output voltage of the auto-zero comparator and, hence, the voltage at the output 32 of the polarity detection circuit 30.

[0041] In one example, switches SW₁, SW₂, SW₃ and SW₄ each comprise, for instance are implemented by, e.g., a NMOS transistor M₇, M₉, M₅ and M₁₂, respectively.

[0042] Switches SW₁, SW₃ and SW₄ on one hand, and switch SW₂, on the other hand, are driven by two complementary clock signals Φ₁ and Φ₂, respectively.

[0043] The operation of the circuit of Figure 4 will now be detailed with reference to the simplified chronograms of Figure 5.

[0044] The first chronogram at top of Figure 5 shows the pulse-width modulated control signal CMD_N generated by the switch driving circuit 20 for driving the power switch M₂. The second chronogram corresponds to the voltage V_{g_}N on the control gate of transistor M₂, showing in particular the delay t₀ introduced by the delay unit 11 of the power stage 10. The third and fourth chronograms show the complementary clock signals Φ₁ and Φ₂. These clock signals Φ₁ and Φ₂ may be generated by the switch driving circuit 20. They have the same period as the control signals CMD_N and CMD_P, which may correspond to the period T_CLK of a master clock CLK of the power management unit which incorporates the DC-DC converter. Control signal CMD_N is in phase with clock signal Φ₁, and control signal CMD_P is in phase with clock signal Φ₂. Note, however, that a slight non-overlap of the Φ₁ and Φ₂ clock signals may be introduced.

[0045] The operation of the polarity detection circuit 30 is cyclic, one cycle corresponding to a period of the complementary clock signals Φ₁ and Φ₂. A cycle is divided in two phases of operation.

[0046] A first phase of operation is defined by the time when clock signal Φ₁ is active, for example at the high logical state, and control signal Φ₂ is inactive, at the low logical state in such example. Conversely, the second phase of operation is defined by the time when clock signal Φ₁ is inactive and control signal Φ₂ is active. In view of the above convention, the first phase of operation will sometimes be referred to as phase Φ₁, and the second phase of operation will be referred to as phase Φ₂, in what follows.

[0047] The NMOS transistor M₂ of the power stage is conductive during the first phase of operation (i.e., phase Φ₁), and is blocked during the second phase of operation (i.e., phase Φ₂). Stated otherwise, the first phase of operation of the polarity detection circuit corresponds to the conduction period of the power transistor M₂ of the DC-DC converter. Also, the switches SW₁, SW₃ and SW₄ are closed during the first phase of operation, and are open during the second phase of operation. Conversely, switch SW₂ is open during the first phase of operation, and is closed during the second phase of operation.

[0048] During phase Φ₁, the drain-source voltage V_DS of the power NMOS transistor M₂ is applied to the first terminal (1) of the memory capacitor C₁ through the closed switch SW₁. Switch SW₃, being closed, configures the transistor M₁ to be diode-connected. The terminal (2) of capacitor C₁ on the side of switch SW₃ is at the voltage gate-source voltage V_GS(M1) of transistor M₁, which is therefore given by:

where :

I_D is the drain current flowing through M₁;

L and W designate the length and the width, respectively, of M₁; and,

V_TH is the threshold voltage of M₁.

[0049] If follows that, during phase Φ₁, the voltage V_C1 across the capacitor C₁ is given by:

where V_DS(M2) is the drain-source voltage of the power transistor M₂.

[0050] It will be appreciated that voltage V_C1 is thus directly representative of voltage V_DS(M2)(t), since the drain current I_D is flowing through M₁ is equal to the constant current I₀ from current source 61 (I_D = I₀), so that voltage V_GS(M1) is constant during phase Φ₁. Voltage V_C1 across capacitor C₁ as a function of time is shown by the fifth chronogram from the top of Figure 5.

[0051] During this phase Φ₁, the auto-zero comparator, namely the Operational Amplifier OA, is configured as a voltage follower (switch SW₄ being closed). Thus, the substantially constant voltage V_Hz at the high-impedance node corresponding to the drain of transistor M₁, is recopied to the capacitor C₂ as voltage V_C2. Voltage V_HZ as a function of time is shown in the sixth chronogram from the top of Figure 5. It may be noted, that an eventual offset of the comparator is added to the V_C2.

[0052] Let us now describe the configuration of the circuit in the second phase Φ₂. In phase Φ₂, terminal (1) of capacitor C₁ on the side of switch SW₂ is connected to the ground GND through closed switch SW₂, and switches SW₁, SW₃ and SW₄ are open. Whatever the polarity of the drain-source V_DS of M₁ voltage at the end of first phase Φ₁ (noted V_DS(t=TCLK) in Figure 5), namely irrespective of whether voltage V_DS(M2) is positive or negative at the end of the conduction period of the NMOS transistor M₂, a complementary, i.e. negative or positive excursion will immediately appear on the gate of transistor M₁. Indeed, the voltage across capacitor C₁ remains constant upon switching of transistor M₂ from the conduction state to the non-conduction state. Further, from the end of phase Φ₁ and beginning of phase Φ₂ we have the following relationship:

[0053] Thus, comparing above relations (3) and relation (4) at t=T_CLK, gives the following changes in the gate-source voltage V_GS(M1) of transistor M₁ :

• if the drain-source voltage V_DS(t=TCLK) of transistor M₂ at the end of phase Φ₁ is positive (as shown on the left part of the fifth chronogram from top of Figure 5 which corresponds to the case illustrated by the graph in continuous line of Figure 3), then the gate-source voltage V_GS of transistor M₁ is shifted down by V_DS(t=TCLK). It follows that voltage V_GS(M1) of transistor M₁ at the beginning of phase Φ₂ is lower than at the end of phase Φ₁ (which may be expressed as V_GS(Φ2) < V_GS(Φ1)); and, conversely,
• if the drain-source voltage V_DS(t=TCLK) of transistor M₁ at the end of phase Φ₁ is negative (as shown on the right part of the fifth chronogram from top of Figure 5 which corresponds to the case illustrated by the graph in dotted line in Figure 3), then the gate-source voltage V_GS of transistor M₁ is shifted up by the absolute value of V_DS(t=TCLK). It follows that voltage V_GS(M1) of transistor M₁ at the beginning of phase Φ₂ is higher than at the end of phase Φ₁ (which may be expressed as V_GS(Φ2) > V_GS(Φ1))-

[0054] This implies the following changes in the drain-source voltage V_DS of transistor M₁, as shown in the sixth chronogram from the top of Figure 5, on the left side, and on the right side, respectively, wherein the substantially constant value V_C2 stored in capacitor C₂ is represented by a horizontal dotted line:

• when V_GS(Φ2) < V_GS(Φ1), then voltage V_DS of M₁ increases from voltage value V_C2; and, conversely,
• in the opposite case when V_GS(Φ2) > V_GS(Φ1), then the drain voltage V_DS of M₁ decreases from the value V_C2 stored in capacitor C₂.

[0055] Let us now concentrate on the operation of the auto-zero comparator.

[0056] In phase Φ₁, the switch SW₄ is closed thereby connecting the output voltage of the AO to its inverting, i.e., negative or "-" input. The AO is thus configured to operate as a voltage follower, as already stated above. Its output voltage, which thus corresponds to the V_HZ voltage plus any offset value of the AO, is charged into capacitor C₂.

[0057] In phase Φ₂, the switch SW₄ is open and the AO thus operates as a comparator, whereby its output voltage is at +V_sat if V_HZ > V_C2, and at -V_sat if V_HZ < V_C2, where +V_sat and -V_sat are the positive and negative saturation voltages, respectively, of the AO, which corresponds to its high supply voltage and its low supply voltage, respectively. In one example, the high supply voltage corresponds to the battery voltage V_l of the device, and the low supply voltage corresponds to the potential of the ground GND, namely 0 Volt.

[0058] To summarize, and as is illustrated by the last chronogram at the bottom of Figure 5, the output voltage V_OUT of the comparator is:

• at voltage V_C2 during phase Φ₁, said voltage V_C2 being substantially constant and mainly defined by the current I₀ output by current source 61;
• at voltage +V_sat = V_l (where V_l is, e.g., the battery voltage) during phase Φ₂ in the case where V_DS(t=TCLK) > 0, namely in the inverted coil current mode of operation of the DC/DC converter; and,
• at voltage -V_sat (e.g 0 Volt) during phase Φ₂ in the case where V_DS(t=TCLK) < 0, namely in the CCM mode of operation of the converter.

[0059] In other words, the output signal V_OUT at the output of the zero-current detector 30 is indicative of the polarity of the drain-source voltage V_DS(t=TCLK) of the power transistor M₂ at the end of its conduction phase Φ₁. Yet in other words, this output signal V_OUT is representative of the result of the CCM/DCM boundary detection. Signal V_OUT is used by the switch driving circuit 20 as shown in Figure 20, for defining the best switch strategy depending on the particular requirements of the contemplated application.

[0060] As can be understood by the one with ordinary skills in the art, using an auto-zero comparator as described above allows removing the effect of any offset of the AO, thus achieving an offset-free comparison result.

[0061] Besides, as the input voltage variation in gate-source voltage V_GS of transistor M₁ from phase Φ₁ to phase Φ₂ can be very low, the voltage excursion in the V_HZ node during phase Φ₂ can be very slow. Nevertheless, one further advantage of the association of the dynamic current mirror with an auto-zero comparator is that voltage V_HZ(Φ2) is compared with voltage V_HZ(Φ1) (stored in C₂) by the auto-zero comparator whose output response is very fast. Therefore, as illustrated by the fifth, sixth and seventh chronograms from the top of Figure 5 showing voltages V_C1, V_HZ, and V_OUT, respectively, even a slow voltage ramp can be detected substantially immediately after the end of phase Φ₁ and beginning of phase Φ₂. This is due to the fact, that the comparator is pre-biased, i.e. the starting-point of its output voltage variation is from an intermediate voltage value V_C2. This effects allow obtaining the comparison result in a very short time compared to the standard solutions.

[0062] Further improvements of the proposed design will now be described with reference to the more elaborated schematic circuit diagram of Figure 6.

[0063] One key aspect of the accuracy of proposed solution as described above is to protect the capacitor voltage V_C1 during the switching from phase Φ₁ to phase Φ₂. This is because the capacitor C₁ stores the information about the compared voltage V_DS of the power NMOS transistor M₂ of the DC-DC converter, and it is critical not to alter this information V_DS(=TCLK) at the end of the conduction phase Φ₁ of the power transistor M₂.

[0064] It will be noted that small amount of error current is passing through capacitor C₁. This is due to the constant voltage at the plate (2) given by Eq.(2), and a small variation of the V_DS(M2) during the conduction of the NMOS transistor M₂. This variation is caused by the triangular shape of I_L (see shape of V_C(1) in the fifth graph from top of Figure 5). As a result, in order to bring this current to a few nanoampers, the value of capacitor C₁ should be very small, for instance 1 pF, or even less. This, however, makes the V_C1 voltage sensitive due to the possible charge injection caused by the switching. It will be appreciated that this is not valid for C₂ which can thus have a higher value.

[0065] Thus, some refinements of the basic design may be implemented, which will now be explained in more details. It will be appreciated, however, that these further embodiments may or not be implemented, either separately or in combination, in any manner suitable for the specific implementation. Stated otherwise, these further embodiments provide additional advantages but are not necessary for implementing the inventive principle of the proposed solution.

[0066] In one embodiment, for instance, provision can be made of a regulated cascode arrangement 63 for stabilising the V_DS voltage of transistor M₁. This solution allows preventing eventual detection errors which may be caused by the charge injection through the drain-to-gate parasitic capacitance of transistor M₁.

[0067] This result may be achieved by the stabilisation of V_DS voltage of M₁ with the help of at least one cascode stage in the dynamic current mirror, said cascode stage comprising two additional transistors M₃ and M₄. The source of M₃ is connected to the source of the main transistor M₁, its drain being connected to the battery voltage through an additional current source 62 delivering an additional constant current I_Aux, and it control gate being connected to the drain of the main transistor M₁. Transistor M₄ is cascaded with transistor M₁, i.e. arranged in series within the drain path of transistor M₁. More precisely, transistor M₄ is connected by its source to the drain of transistor M₁, and by its drain to the main current source 61 which delivers the main current I₀, having its control gate connected to the drain of transistor M₃ in the current path comprising the additional current source 62.

[0068] The stabilisation effect of this cascode arrangement is obtained at the cost of consumption of a small additional current I_AUX of e.g. a few micro-amperes (µA).

[0069] In other embodiments, dummy switches may be used to prevent the "clock feed-through" effect from the clock signals. By "dummy switches", it must be understood dummy transistors, that is to say transistors of same technology as their associated main transistor, and having their current path short-circuited, namely their drain permanently connected to their source at silicon level. In the application considered here, the gate of any dummy transistor used as dummy switch receives a control clock signal which is complementary to the clock signal received by the gate of their associated main transistor.

[0070] For example, one or two such dummy switches may be associated to the third switch SW₃. For example, these dummy switches may be dummy transistors which have a size 0.5xW and 1xL, as compared with the size W and L of the main transistor M₅ of switch SW₃, respectively, and are provided in the current path of said main transistor M₅. In the shown example, one such dummy transistor is connected on each side of transistor M₅, namely on the drain side and the other on the source side of M₅. The former is adapted to prevent charge injection from transistor M₅ to the second capacitor C₂, and the latter is adapted to prevent charge injection from transistor M₅ to the first capacitor C₁. To that end, these dummy transistors are each controlled by the clock signal Φ₂ which is complementary to the clock signal Φ₁ controlling the transistor M₅ which implements the control switch SW₃.

[0071] It shall be appreciated that, other and possibly all control switches used in the zero-current may have one or two associated dummy switches. For instance, a dummy transistor may also be associated to the transistor M₁₂ of switch SW₄, as shown in Figure 6 as well. More precisely, a dummy transistor is provided in the current path of the transistor M₁₂ implementing the control switch SW₄, on the side of the second capacitor C₂, said dummy transistor being controlled by the clock signal Φ₂ which is complementary to the clock signal Φ₁ controlling said main transistor implementing the fourth control switch. Being so arranged, the dummy transistor associated with transistor M₁₂ of switch SW₄ is adapted to prevent charge injection from said transistor M₁₂ to the second capacitor C₂.

[0072] In still other embodiments, provision can be made of a serially connected series and shunt switching arrangement 64, avoiding leakage of the inductor voltage V_LX at the drain of the power NMOS transistor M₂ when its body-diode is conducting.

[0073] In the shown example, such series and shunt switching arrangement is implemented at the first switch SW₁. Stated otherwise, the circuit comprises a series and shunt switching arrangement associated to the first switch SW₁. It may thus comprise, in addition to the serially connected transistor M₇ of switch SW₁ as described above, another serially connected transistor NMOS M₆ which is controlled by the same clock signal Φ₁ as transistor M₇, and a parallel connected (i.e. shunt) NMOS transistor M₈ controlled by a clock signal which is complementary to Φ₁, for instance by the clock signal Φ₂.

[0074] In yet other embodiments, the clock signals Φ₁ and Φ₂ are generated by the switch driving circuit so as to be slightly non-overlapping, in order to avoid the cross-conduction current through the switches SW₂ and SW₃. By "non-overlapping" it must be understood that both signals are not active, i.e. for instance at the logical high state, at the same time. As shown by the three first chronograms from the top of Figure 5, clock signals Φ₁ and Φ₂ are driven by the NMOS control signal CMD_N instead of control voltage Vg_N. This allows sampling the drain-source voltage V_DS(t=TCLK) of the NMOS transistor M₁ at the end of phase Φ₁ slightly before the end of the transistor conduction, when the power stage 10 is still in steady-state.

[0075] In further embodiments the voltage polarity detection circuit may further comprise a reference ground switching arrangement 65. This allows that that the reference ground is the power ground GND_POWER of the power stage of the DC/DC converter during the first phase of operation Φ₁, and is a "clean" ground GND_CLEAN, distinct from said power ground, during the second phase of operation Φ₂. Indeed, it is better that the reference ground of the voltage polarity detection circuit be the power ground of the power stage of the DC/DC converter during the first phase of operation Φ₁ because this provides a better accuracy of the copy of the drain-source voltage V_DS(M2) of the power MOS transistor M₂ in the first transistor C₁. However, in the remaining of the time, that is to say during the second phase of operation Φ₂, it is better that the reference ground the voltage polarity detection circuit be distinct from the power ground of the power stage of the DC/DC converter, because the latter may vary depending on the load current and may convey various kinds of interferences.

[0076] This result may be achieved, as shown in Figure 4, by providing in the reference ground switching arrangement 65, a first NMOS transistor M₁₀ in series between the source of the main transistor M₁ of the dynamic current source and the clean ground GND_CLEAN terminal, which is controlled by signal Φ₂, and a second NMOS transistor M₁₁ in series between the source of transistor M₁ and the power ground GND_POWER terminal of the power stage 10, said transistor M₁₁ being controlled by signal Φ₁.

[0077] Finally, some embodiments may implement a dynamic bias in order to provide very low current consumption. According to such embodiments, the circuit is powered during the first phase of operation Φ₁ of the DC/DC converter, only until the voltage V_HZ at the first input of the auto-zero comparator crosses the voltage V_C2 at the second input of said auto-zero comparator, and is then turned off to save current consumption until the beginning of the next conduction cycle of the power switch M₂ of the DC/DC converter, that is to say until the beginning of the next iteration of the first phase of operation Φ₁ of the DC/DC converter. In other words, the circuit is switched off and is placed e.g. in a sleep mode, until the beginning of the next NMOS conduction cycle.

[0078] The design presented above has a major impact on the efficiency and reliability of the DC/DC converter for e.g. mobile-phone platforms. Using such architecture can bring a significant advancement compared to existing solutions and can also find usage in similar products, such as any type of wireless devices.

[0079] The block diagram in Figure 7 shows the elements of a wireless device 100 incorporating a DC/DC converter 110 as described above. Such a device 100 can be a mobile telephone, a smart phone, a digital audio player, a PDA, an e-book reader, or any other battery powered device.

[0080] The device 100 as shown comprises a control unit 101 such as a processor (CPU), and a number of functional units such as, for instance, a communication unit 102 for transmitting and receiving information to and from the outside, in particular by modulating a radio frequency carrier, a memory 103 which can store information in digital form, for example a piece of music, etc. The processor 101 communicates with the functional units like 102 and 103, via a communication bus 120. Each of the CPU and the functional units is powered from the battery voltage Vbat delivered by a battery 106, through a Power Management Unit (PMU) 130.

[0081] To generate supply voltages from the battery voltage Vbat, the PMU 130 comprises at least one voltage DC/DC converter 131 of the SMPS type, for which embodiments have been described above. More than one such DC/DC converter may be provided for generating a plurality of supply voltages Vdd1, Vdd2, ... of different values for e.g. supplying respective groups of functional units, and/or respective functional blocks thereof. The DC/DC converters may be of any one of the buck, boost or buck-boost type, as previously described with reference to Figures 1A-1C.

[0082] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which inventive concepts belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0083] It will be further understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of inventive concepts.

[0084] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of inventive concepts. As used herein, the singular forms "a," "an" and "the" are intended to include the plural aims as well, unless the context clearly indicates otherwise.

[0085] Also; expressions such as "comprise", "include", "incorporate", "contain", "is" and "have" are to be construed in a non-exclusive manner when interpreting the description and its associated claims, namely construed to allow for other items or components which are not explicitly defined also to be present. Reference to the singular is also to be construed in be a reference to the plural and vice versa.

[0086] While there has been illustrated and described what are presently considered to be the preferred embodiments of the present invention, it will be understood by those skilled in the art that various other modifications may be made, and equivalents may be substituted, without departing from the true scope of the present invention. Additionally, many modifications may be made to adapt a particular situation to the teachings of the present invention without departing from the central inventive concept described herein. Furthermore, an embodiment of the present invention may not include all of the features described above. Therefore, it is intended that the present invention not be limited to the particular embodiments disclosed, but that the invention include all embodiments falling within the scope of the appended claims.

[0087] The present invention can be implemented in hardware, software, or a combination of hardware and software. Any processor, controller, or other apparatus adapted for carrying out the functionality described herein is suitable. A typical combination of hardware and software could include a general purpose microprocessor (or controller) with a computer program that, when loaded and executed, carries out the functionality described herein.

[0088] The present invention can also be embedded in a computer program product, which comprises all the features enabling the implementation of the methods described herein, and which - when loaded in an information processing system - is able to carry out these methods. Computer program means or computer program in the present context mean any expression, in any language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after either or both of the following a) conversion to another language. Such a computer program can be stored on a computer or machine readable medium allowing data, instructions, messages or message packets, and other machine readable information to be read from the medium. The computer or machine readable medium may include non-volatile memory, such as ROM, Flash memory, Disk drive memory, CD-ROM, and other permanent storage. Additionally, a computer or machine readable medium may include, for example, volatile storage such as RAM, buffers, cache memory, and network circuits. Furthermore, the computer or machine readable medium may comprise computer or machine readable information in a transitory state medium such as a network link and/or a network interface, including a wired network or a wireless network, that allow a device to read such computer or machine readable information.

[0089] A person skilled in the art will readily appreciate that various parameters disclosed in the description may be modified and that various embodiments disclosed and/or claimed may be combined without departing from the scope of the invention.

[0090] It is stipulated that the reference signs in the claims do not limit the scope of the claims, but are merely inserted to enhance the legibility of the claims.

Claims

1. A voltage polarity detection circuit (30) comprising:

an input (31) configured to receive an input voltage (VLx) representative of the conduction voltage of a power switch FET;

an output (32) configured to output a voltage polarity detection signal;

a current source (61) adapted to output a constant current (10);

a MOS transistor (M1) having:

- a drain connected to the current source for receiving said constant current,

- a gate connected to the input through a first capacitor (C1) and a first control switch (SW1), to its drain through a third control switch (SW3) and to a first power supply (GND) through the first capacitor (C1) and a second control switch (SW2); and

- a source connected to the first power supply (GND);

characterized in that the voltage polarity detection circuit (30) is further comprising:
a comparator comprising an Operational Amplifier (OA) having:

- a non-inverting input connected to the drain of the MOS transistor,

- an inverting input connected to the first power supply (GND) through a second capacitor (C2), and

- an output connected to the non-inverting input through a fourth control switch (SW4) and to the output (32); wherein the voltage polarity detection circuit (30) is configured so that:

during a first phase of operation (ϕ1) corresponding to a conduction cycle of the power switch FET, the first, second and fourth control switches are closed and the third control switch is open, such that an output voltage (V_Hz) of the MOS transistor (M1) is charged into the second capacitor (C₂); and

during a second phase of operation (Φ₂) corresponding to a non-conduction cycle of the power switch FET; the first, second and fourth control switches are open and the third control switch is closed, and the polarity of the input voltage (VLx) at the end of the first phase of operation is detected by comparing the voltage stored in the second capacitor with the output voltage (VHz) of the MOS transistor; and wherein

the first, second and fourth control switches are driven by a first clock signal and the third control switch is driven by a second clock signal complementary to the first clock signal.

2. The voltage polarity detection circuit of claim 1, further comprising a cascode stage having a first additional MOS transistor (M₃) whose source is connected to the source of the main MOS transistor (M₁), whose drain is connected to an additional current source (62) adapted to output an additional constant current (I_aux), and whose control gate is connected to the drain of said main transistor (M₁), as well as a second additional MOS transistor (M₄) whose source is connected to the drain of the main transistor (M₁), whose drain is connected to the main current source (61) for receiving the main constant current (I₀), and whose control gate is connected to the drain of the first additional transistor (M₃).

3. The voltage polarity detection circuit of claim 1 or 2, wherein the third control switch (SW₃) is implemented by a main transistor (M₅) the voltage polarity detection circuit further comprising a first and/or a second dummy transistor provided in the current path of said main transistor implementing the third control switch, on either side of said main transistor implementing the third control switch, respectively, namely on the drain side and on the source side of said main transistor, respectively, said first and/or second dummy transistors each being controlled by the first clock signal.

4. The voltage polarity detection circuit of claim 3, wherein the first and/or second dummy transistors have a size 0.5xW and 1xL, as compared with the size W and L of said main transistor, respectively.

5. The voltage polarity detection circuit of any one of claims 1 to 4, wherein the fourth control switch (SW₄) is implemented by a main transistor (M₁₂), the voltage polarity detection circuit further comprising a dummy transistor provided in the current path of said main transistor implementing the fourth control switch, on the side of the second capacitor (C₂) said dummy transistor being controlled by the second clock signal.

6. The voltage polarity detection circuit of any one of claims 1 to 5, wherein the first control switch (SW₁) is implemented by a main transistor (M₇), the voltage polarity detection circuit further comprising a series and shunt switching arrangement (64) associated to said main transistor implementing the first control switch (SW₁), said series and shunt switching arrangement comprising, in addition to the serially connected main transistor (M₇) implementing the first control switch (SW₁), another serially connected transistor (M₆) which is controlled by the same first clock signal (Φ₁) as said main transistor (M₇) implementing the first control switch (SW₁), and a parallel connected transistor (M₈) controlled by the second clock signal (Φ₂).

7. The voltage polarity detection circuit of any one of claims 1 to 6, wherein the two complementary first and second clock signals (Φ₁,Φ₂) are non-overlapping.

8. The voltage polarity detection circuit of any one of claims 1 to 7, further comprising a reference ground switching arrangement (65), so arranged that the first power supply is the power ground of the power stage of the DC/DC converter during the first phase of operation (Φ₁) and is distinct from said power ground during the second phase of operation (Φ₂).

9. The circuit of any one of claims 1 to 6, wherein the circuit is powered during the first phase of operation (Φ₁), only until the voltage (V_Hz) at the first input of the comparator crosses the voltage (V_c2) at the second input of said comparator, and is then be turned off until the beginning of the next conduction cycle of the power switch.

10. A DC/DC converter comprising:

a. a power stage (10) having at least one power switch FET (M₂); and,

b. at least one voltage polarity detection circuit (30) according to any one of claims 1 to 9.

11. The DC/DC converter of claim 11, wherein the power switch FET (SW₁) comprises a power Metal Oxyde Semiconductor, MOS, transistor (M₁) and wherein the input voltage of the voltage polarity detection circuit (30) is the drain-source voltage (V_DS(M₁)) of said power MOS transistor.

12. A mobile device comprising a DC/DC converter according to claim 10 or 11.

Ansprüche

1. Spannungspolaritäts-Erfassungsschaltung (30), umfassend:

einen Eingang (31), der konfiguriert ist, um eine Eingangsspannung (VLx) zu empfangen, die für die Leitungsspannung eines Leistungsschalters-FET repräsentativ ist;

einen Ausgang (32), der konfiguriert ist, um ein Spannungspolaritätserfassungssignal auszugeben;

eine Stromquelle (61), die angepasst ist, um einen Konstantstrom (I0) auszugeben;

einen MOS-Transistor (M1) aufweisend:

- einen Drain, der mit der Stromquelle verbunden ist, um den Konstantstrom zu empfangen,

- ein Gate, das über einen ersten Kondensator (C1) und einen ersten Steuerschalter (SW1) mit dem Eingang, über einen dritten Steuerschalter (SW3) mit seinem Drain und über den ersten Kondensator (C1) und einen zweiten Steuerschalter (SW2) mit einer ersten Stromversorgung (GND) verbunden ist; und

- eine Quelle, die mit der ersten Stromversorgung (GND) verbunden ist;

dadurch gekennzeichnet, dass die Spannungspolaritäts-Erfassungsschaltung (30) weiter umfasst:
einen Vergleicher, umfassend einen Operationsverstärker (OA), aufweisend:

- einen nichtinvertierenden Eingang, der mit dem Drain des MOS-Transistors verbunden ist,

- einen invertierenden Eingang, der über einen zweiten Kondensator (C2) mit der ersten Stromversorgung (GND) verbunden ist, und

- einen Ausgang, der mit dem nicht-invertierenden Eingang über einen vierten Steuerschalter (SW4) und mit dem Ausgang (32) verbunden ist; wobei die Spannungspolaritäts-Erfassungsschaltung (30) so konfiguriert ist, dass:

während einer ersten Betriebsphase (ϕ1), die einem Leitungszyklus des Leistungsschalters-FET entspricht, der erste, zweite und vierte Steuerschalter geschlossen sind und der dritte Steuerschalter geöffnet ist, sodass eine Ausgangsspannung (V_Hz) des MOS-Transistors (M1) in den zweiten Kondensator (C₂) geladen wird; und

während einer zweiten Betriebsphase (φ₂), die einem Nichtleitungszyklus des Leistungsschalters-FET entspricht; der erste, zweite und vierte Steuerschalter geöffnet sind und der dritte Steuerschalter geschlossen ist, und die Polarität der Eingangsspannung (VLx) am Ende der ersten Betriebsphase durch Vergleichen der im zweiten Kondensator gespeicherten Spannung mit der Ausgangsspannung (VHz) des MOS-Transistors erfasst wird; und wobei

der erste, zweite und vierte Steuerschalter durch ein erstes Taktsignal und der dritte Steuerschalter durch ein zweites Taktsignal gesteuert werden, das zu dem ersten Taktsignal komplementär ist.

2. Spannungspolaritäts-Erfassungsschaltung nach Anspruch 1, weiter umfassend eine Kaskodenstufe mit einem ersten zusätzlichen MOS-Transistor (M₃), dessen Quelle mit der Quelle des MOS-Haupttransistors (M₁) verbunden ist, dessen Drain mit einer zusätzlichen Stromquelle (62) verbunden ist, die angepasst ist, einen zusätzlichen Konstantstrom (I_aux) ausgeben kann, und dessen Steuer-Gate mit dem Drain des Haupttransistors (M₁) verbunden ist, sowie einen zweiten zusätzlichen MOS-Transistor (M₄), dessen Quelle mit dem Drain des Haupttransistors (M₁) verbunden ist, dessen Drain mit der Hauptstromquelle (61) zum Empfangen des Hauptkonstantstroms (I₀) und dessen Steuer-Gate mit dem Drain des ersten zusätzlichen Transistors (M₃) verbunden ist.

3. Spannungspolaritäts-Erfassungsschaltung nach Anspruch 1 oder 2, wobei der dritte Steuerschalter (SW₃) durch einen Haupttransistor (M₅) implementiert ist, wobei die Spannungspolaritäts-Erfassungsschaltung weiter einen ersten und/oder einen zweiten Blindtransistor umfasst, der in dem Strompfad des Haupttransistors bereitgestellt ist, der den dritten Steuerschalter implementiert, jeweils auf jeder Seite des Haupttransistors, der den dritten Steuerschalter implementiert, nämlich jeweils auf der Drain-Seite und auf der Quellenseite des Haupttransistors, wobei die ersten und/oder zweiten Blindtransistoren jeweils durch das erste Taktsignal gesteuert werden.

4. Spannungspolaritäts-Erfassungsschaltung nach Anspruch 3, wobei die ersten und/oder zweiten Blindtransistoren eine Größe von 0,5xW und 1xL, jeweils verglichen mit der Größe W und L des Haupttransistors, aufweisen.

5. Spannungspolaritäts-Erfassungsschaltung nach einem der Ansprüche 1 bis 4, wobei der vierte Steuerschalter (SW₄) durch einen Haupttransistor (M₁₂) implementiert ist, wobei die Spannungspolaritäts-Erfassungsschaltung weiter einen Blindtransistor umfasst, der im Strompfad des Haupttransistors, der den vierten Steuerschalter implementiert, auf der Seite des zweiten Kondensators (C₂) bereitgestellt ist, wobei der Blindtransistor durch das zweite Taktsignal gesteuert wird.

6. Spannungspolaritäts-Erfassungsschaltung nach einem der Ansprüche 1 bis 5, wobei der erste Steuerschalter (SW₁) durch einen Haupttransistor (M₇) implementiert ist, wobei die Spannungspolaritäts-Erfassungsschaltung weiter eine Reihen- und Nebenschluss-Schaltanordnung (64) umfasst, die dem Haupttransistor zugeordnet ist, der den ersten Steuerschalter (SW₁) implementiert, wobei die Reihen- und Nebenschluss-Schaltanordnung zusätzlich zu dem seriell verbundenen Haupttransistor (M₇), der den ersten Steuerschalter (SW₁) implementiert, einen weiteren seriell verbundenen Transistor (M₈), der durch das gleiche erste Taktsignal (φ₁) gesteuert wird wie der Haupttransistor (M₇), der den ersten Steuerschalter (SW₁) implementiert, und einen parallel verbundenen Transistor (M₈), der durch das zweite Taktsignal (φ₂) gesteuert wird, umfasst.

7. Spannungspolaritäts-Erfassungsschaltung nach einem der Ansprüche 1 bis 6, wobei die beiden komplementären ersten und zweiten Taktsignale (φ₁,φ2) nicht überlappend sind.

8. Spannungspolaritäts-Erfassungsschaltung nach einem der Ansprüche 1 bis 7, weiter umfassend eine Bezugsmasse-Schaltungsanordnung (65), so angeordnet, dass die erste Stromversorgung die Leistungsmasse der Leistungsstufe des DC/DC-Wandlers während der ersten Betriebsphase (φ₁) ist und sich von der Leistungsmasse während der zweiten Betriebsphase (φ₂) unterscheidet.

9. Schaltung nach einem der Ansprüche 1 bis 6, wobei die Schaltung während der ersten Betriebsphase (φ₁) nur so lange mit Leistung versorgt wird, bis die Spannung (V_Hz) am ersten Eingang des Vergleichers die Spannung (V_c2) am zweiten Eingang des Vergleichers erreicht und dann bis zum Beginn des nächsten Leitungszyklus des Leistungsschalters ausgeschaltet wird.

10. Ein DC/DC-Wandler, umfassend:

a. eine Leistungsstufe (10) aufweisend mindestens einen Leistungsschalter-FET (M₂); und

b. mindestens eine Spannungspolaritäts-Erfassungsschaltung (30) nach einem der Ansprüche 1 bis 9.

11. DC/DC-Wandler nach Anspruch 11, wobei der Leistungsschalter-FET (SW₁) einen Leistungs-Metall-Oxid-Halbleiter-, MOS-, Transistor (M₁) umfasst und wobei die Eingangsspannung der Spannungspolaritäts-Erfassungsschaltung (30) die Drain-Quelle-Spannung (V_Ds(M₁)) des Leistungs-MOS-Transistors ist.

12. Mobilgerät, umfassend einen DC/DC-Wandler nach Anspruch 10 oder 11.

Revendications

1. Circuit de détection de polarité de tension (30) comprenant :

une entrée (31) configurée pour recevoir une tension d'entrée (VLx) représentative de la tension de conduction d'un commutateur de puissance FET ;

une sortie (32) configurée pour produire un signal de détection de polarité de tension ;

une source de courant (61) adaptée pour produire un courant constant (I0) ;

un transistor MOS (M1) ayant :

- un drain raccordé à la source de courant pour recevoir ledit courant constant,

- une grille raccordée à l'entrée à travers un premier condensateur (C1) et un premier commutateur de commande (SW1) à son drain à travers un troisième commutateur de commande (SW3) et à une première alimentation électrique (GND) à travers le premier condensateur (C1) et un deuxième commutateur de commande (SW2) ; et

- une source raccordée à la première alimentation électrique (GND) ;

caractérisé en ce que le circuit de détection de polarité de tension (30) comprend en outre :
un comparateur comprenant un Amplificateur Opérationnel (OA) ayant :

- une entrée non inverseuse raccordée au drain du transistor MOS,

- une entrée inverseuse raccordée à la première alimentation électrique (GND) à travers un second condensateur (C2), et

- une sortie raccordée à l'entrée non inverseuse à travers un quatrième commutateur de commande (SW4) et à la sortie (32) ; dans lequel le circuit de détection de polarité de tension (30) est configuré de sorte que :

durant une première phase de fonctionnement (ϕ1) correspondant à un cycle de conduction du commutateur de puissance FET, les premier, deuxième et quatrième commutateurs de commande soient fermés et le troisième commutateur de commande soit ouvert, de sorte qu'une tension de sortie (V_HZ) du transistor MOS (M1) soit chargée dans le second condensateur (C₂) ; et

durant une seconde phase de fonctionnement (φ2) correspondant à un cycle de non-conduction du commutateur de puissance FET, les premier, deuxième et quatrième commutateurs de commande soient ouverts et le troisième commutateur de commande soit fermé, et la polarité de la tension d'entrée (VLx) à la fin de la première phase de fonctionnement soit détectée en comparant la tension stockée dans le second condensateur avec la tension de sortie (VHz) du transistor MOS ; et dans lequel

les premier, deuxième et quatrième commutateurs de commande sont entraînés par un premier signal d'horloge et le troisième commutateur de commande est entraîné par un second signal d'horloge complémentaire au premier signal d'horloge.

2. Circuit de détection de polarité de tension selon la revendication 1, comprenant en outre un étage cascode ayant un premier transistor MOS supplémentaire (M₃) dont la source est raccordée à la source du transistor MOS principal (M₁), dont le drain est raccordé à une source de courant supplémentaire (62) adaptée pour produire un courant constant supplémentaire (I_aux), et dont la grille de commande est raccordée au drain dudit transistor principal (M₁), ainsi qu'un second transistor MOS supplémentaire (M₄) dont la source est raccordée au drain du transistor principal (M₁), dont le drain est raccordé à la source de courant principale (61) pour recevoir le courant constant principal (I₀), et dont la grille de commande est raccordée au drain du premier transistor supplémentaire (M₃).

3. Circuit de détection de polarité de tension selon la revendication 1 ou 2, dans lequel le troisième commutateur de commande (SW₃) est mis en œuvre par un transistor principal (M₅), le circuit de détection de polarité de tension comprenant en outre un premier et/ou un second transistor fictif fourni dans le trajet de courant dudit transistor principal mettant en œuvre le troisième commutateur de commande, sur l'un ou l'autre côté dudit transistor principal mettant en œuvre le troisième commutateur de commande, respectivement, à savoir sur le côté du drain et sur le côté de la source dudit transistor principal, respectivement, lesdits premier et/ou second transistors fictifs étant chacun commandés par le premier signal d'horloge.

4. Circuit de détection de polarité de tension selon la revendication 3, dans lequel les premier et/ou second transistors fictifs ont une taille de 0,5 x W et de 1 x L, comparée à la taille W et L dudit transistor principal, respectivement.

5. Circuit de détection de polarité de tension selon l'une quelconque des revendications 1 à 4, dans lequel le quatrième commutateur de commande (SW₄) est mis en œuvre par un transistor principal (M₁₂), le circuit de détection de polarité de tension comprenant en outre un transistor fictif fourni dans le trajet de courant dudit transistor principal mettant en œuvre le quatrième commutateur de commande, sur le côté du second condensateur (C₂), ledit transistor fictif étant commandé par le second signal d'horloge.

6. Circuit de détection de polarité de tension selon l'une quelconque des revendications 1 à 5, dans lequel le premier commutateur de commande (SW₁) est mis en œuvre par un transistor principal (M₇), le circuit de détection de polarité de tension comprenant en outre un agencement de commutation en série et shunt (64) associé audit transistor principal mettant en œuvre le premier commutateur de commande (SW₁), ledit agencement de commutation en série et shunt comprenant, en plus du transistor principal raccordé en série (M₇) mettant en œuvre le premier commutateur de commande (SW₁), un autre transistor raccordé en série (M₆) qui est commandé par le même premier signal d'horloge (φ1) que ledit transistor principal (M₇) mettant en œuvre le premier commutateur de commande (SW₁), et un transistor raccordé en parallèle (M₈) commandé par le second signal d'horloge (φ2).

7. Circuit de détection de polarité de tension selon l'une quelconque des revendications 1 à 6, dans lequel les deux premier et second signaux d'horloge complémentaires (φ₁, φ2) sont non chevauchants.

8. Circuit de détection de polarité de tension selon l'une quelconque des revendications 1 à 7, comprenant en outre un agencement de commutation de terre de référence (65), agencé de sorte que la première alimentation électrique soit la terre électrique de l'étage électrique du convertisseur CC/CC durant la première phase de fonctionnement (φ₁) et soit distinct de ladite terre électrique durant la seconde phase de fonctionnement (φ₂).

9. Circuit de détection de polarité de tension selon l'une quelconque des revendications 1 à 6, dans lequel le circuit est alimenté durant la première phase de fonctionnement (φ₁), uniquement jusqu'à ce que la tension (V_Hz) au niveau de la première entrée du comparateur croise la tension (V_c2) au niveau de la seconde entrée dudit comparateur, et est alors éteint jusqu'au début du cycle de conduction suivant du commutateur de puissance.

10. Convertisseur CC/CC comprenant :

a. un étage électrique (10) ayant au moins un commutateur de puissance FET (M₂) ; et,

b. au moins un circuit de détection de polarité de tension (30) selon l'une quelconque des revendications 1 à 9.

11. Convertisseur CC/CC selon la revendication 11, dans lequel le commutateur de puissance FET (SW₁) comprend un transistor métal-oxyde-semiconducteur, MOS, de puissance (M₁) et dans lequel la tension d'entrée du circuit de détection de polarité de tension (30) est la tension drain-source (V_DS(M₁)) dudit transistor MOS de puissance.

12. Dispositif mobile comprenant un convertisseur CC/CC selon la revendication 10 ou 11.

Drawing