(19)
(11) EP 2 879 017 A8

(12) CORRECTED EUROPEAN PATENT APPLICATION
Note: Bibliography reflects the latest situation

(15) Correction information:
Corrected version no 1 (W1 A3)

(48) Corrigendum issued on:
24.02.2016 Bulletin 2016/08

(88) Date of publication A3:
02.12.2015 Bulletin 2015/49

(43) Date of publication:
03.06.2015 Bulletin 2015/23

(21) Application number: 14192388.8

(22) Date of filing: 07.11.2014
(51) International Patent Classification (IPC): 
G06F 1/08(2006.01)
G06F 1/32(2006.01)
 G06F 1/10(2006.01)
(84) Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated Extension States:
BA ME

(30) Priority: 27.11.2013 US 201314092034

(71) Applicant: Intel Corporation
Santa Clara, CA 95054 (US)

(72) Inventors:
  • Gendler, Alexander
    27041 Kiriat Motzkin (IL)
  • Sodhi, Inder M.
    Folsom, CA 95630 (US)

(74) Representative: Hufton, David Alan 
HGF Limited Fountain Precinct Balm Green
Sheffield S1 2JA
Sheffield S1 2JA (GB)

   


(54) Performing an operating frequency change using a dynamic clock control technique


(57) In an embodiment, a processor includes a core to execute instructions, where the core includes a clock generation circuit to receive and distribute a first clock signal at a first operating frequency provided from a phase lock loop of the processor to a plurality of units of the core. The clock generation circuit may include a dynamic clock logic to receive a dynamic clock frequency command and to cause the clock generation circuit to distribute the first clock signal to at least one of the units at a second operating frequency. Other embodiments are described and claimed.