(19)
(11) EP 2 889 769 A8

(12) CORRECTED EUROPEAN PATENT APPLICATION
Note: Bibliography reflects the latest situation

(15) Correction information:
Corrected version no 1 (W1 A1)

(48) Corrigendum issued on:
17.02.2016 Bulletin 2016/07

(88) Date of publication A3:
01.07.2015 Bulletin 2015/27

(43) Date of publication:
01.07.2015 Bulletin 2015/27

(21) Application number: 14194407.4

(22) Date of filing: 21.11.2014
(51) International Patent Classification (IPC): 
G06F 9/52(2006.01)
(84) Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated Extension States:
BA ME

(30) Priority: 27.12.2013 US 201314142475

(71) Applicant: Intel Corporation
Santa Clara, CA 95054 (US)

(72) Inventors:
  • Kassa, Rolf
    38110 Braunschweig (DE)
  • Gottschlich, Justin E.
    Santa Clara, CA California 95054 (US)
  • Hu, Shiliang
    Los Altos, CA California 94024 (US)
  • Pokam, Gilles A.
    Fremont, CA California 94555 (US)
  • Knauerhase, Robert C.
    Portland, OR Oregon 97219-4546 (US)

(74) Representative: Jennings, Vincent Louis 
HGF Limited Fountain Precinct Balm Green
Sheffield S1 2JA
Sheffield S1 2JA (GB)

   


(54) Processor with transactional capability and logging circuitry to report transactional operations


(57) A processor is described comprising memory access conflict detection circuitry to identify a conflict pertaining to a transaction being executed by a thread that believes it has locked information within a memory. The processor also includes logging circuitry to construct and report out a packet if the memory access conflict detection circuitry identifies a conflict that causes the transaction to be aborted.