(19)
(11) EP 2 907 161 A1

(12)

(43) Date of publication:
19.08.2015 Bulletin 2015/34

(21) Application number: 13845263.6

(22) Date of filing: 10.10.2013
(51) International Patent Classification (IPC): 
H01L 25/00(2006.01)
(86) International application number:
PCT/US2013/064364
(87) International publication number:
WO 2014/059161 (17.04.2014 Gazette 2014/16)
(84) Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated Extension States:
BA ME

(30) Priority: 11.10.2012 US 201213649510

(71) Applicant: Easic Corporation
Santa Clara, CA 95054 (US)

(72) Inventors:
  • ANDREEV, Alexander
    San Jose, CA 95133 (US)
  • GRIBOK, Sergey
    Santa Clara, CA 95051 (US)
  • SCEPANOVIC, Ranko, L.
    Saratoga, CA 95070 (US)
  • TAN, Phey-Chuin
    11100 Penang (MY)
  • KUNG, Chee-Wei
    11700 Penang (MY)

(74) Representative: Appleyard Lees 
15 Clare Road
Halifax HX1 2HY
Halifax HX1 2HY (GB)

   


(54) VIA-CONFIGURABLE HIGH-PERFORMANCE LOGIC BLOCK INVOLVING TRANSISTOR CHAINS