Cryogenic silicon-based surface-electrode trap and method of manufacturing such a trap

Abstract

 A system for trapping charged or polar particles is provided. The system includes a cryostat and a surface-electrode trap for trapping charged or polar particles. The surface-electrode trap includes a silicon substrate having a front surface and a back surface. Planar electrodes are formed on the front surface of the silicon substrate and configured to generate a trapping potential for trapping the charged or polar particles above the planar electrodes. The planar electrodes include a first radio frequency electrode extending substantially parallel to the front surface of the substrate, and a first direct current electrode extending substantially parallel to the front surface of the substrate and being adjacent to, and electrically insulated from, the first radio frequency electrode. The surface-electrode trap is positioned in the cryostat, and the cryostat is configured for cooling the surface-electrode trap to or below a temperature of 150 K.

Description

FIELD

[0001] The present disclosure relates to a system for trapping charged or polar particles and to a surface-electrode trap for trapping charged or polar particles. Specifically, the trap may be a planar ion trap according to some embodiments, typically for trapping ions and performing controlled quantum interactions between them. The present disclosure also relates to a method for manufacturing such a surface-electrode trap, to the use of such a trap, and to a method of operating such a trap.

BACKGROUND

[0002] Ion traps for storing ions are known. Such ion traps may be used, e.g., for mass spectroscopy by selectively ejecting ions based on their mass-to-charge ratio. Ion traps may also be used for quantum computation by performing controlled quantum interactions between stored ions or may be used for quantum simulation.

[0003] The ions traps may be three-dimensional macroscopic or microscopic structures within which the ions can be stored, such as described in US 7,081,623. Alternatively, the ion traps may be planar structures in which trap electrodes reside in one plane and provide a trapping potential for trapping the ions in the free space above this plane. The planar, two-dimensional structure offers advantages concerning scalability and ease of fabrication as compared to the three-dimensional bulk designs. Scalability is a relevant factor for the development of a quantum computer.

[0004] A surface-electrode ion trap with planar electrodes is described, e.g., in US 7,180,078. There, the ion trap includes planar electrodes formed in an area over the surface of a metal substrate or of a heavily doped semiconductor substrate. Arranged along the axis of the ion trap are two rectangular outer direct-current (DC) electrodes made of doped polysilicon, axially segmented rectangular central DC electrodes made of polysilicon, and two rectangular metal radio-frequency (RF) electrodes between the outer and the central DC electrodes formed on dielectric pedestals in a plane above the DC electrodes. By applying specific DC voltages to the axial segments of the central DC electrode the position of ions in the ion trap can be controlled. However, the structure and fabrication of this trap is rather complex.

[0005] Other surface-electrode ion traps are formed on dielectric substrates, e.g., silica substrates. Dielectric substrates have a low RF power dissipation advantageous for establishing the RF trapping potentials, but are difficult to pattern or process. Further, semiconductor substrates, such as silicon substrates, covered by a metal ground electrode have been used. There, the ground electrode shielded the semiconductor substrate from the RF fields to exclude large power dissipation in the semiconductor substrate. However, the ground electrode makes access by vias to the RF electrodes difficult, and the overall fabrication process is rather complicated.

[0006] Consequently, there is a need for improved traps for trapping charged particles, such as ions, or polar particles, such as polar molecules, and for improved manufacturing methods.

SUMMARY

[0007] According to an embodiment, a system for trapping charged or polar particles is provided. The system includes a cryostat and a surface-electrode trap for trapping charged or polar particles. The surface-electrode trap includes a silicon substrate having a front surface and a back surface. Planar electrodes are formed on the front surface of the silicon substrate and configured to generate a trapping potential for trapping the charged or polar particles above the planar electrodes. The planar electrodes include a first radio frequency (RF) electrode extending substantially parallel to the front surface of the substrate, and a first direct current (DC) electrode extending substantially parallel to the front surface of the substrate and being adjacent to, and electrically insulated from, the first RF electrode. The surface-electrode trap is positioned in the cryostat, and the cryostat is configured for cooling the surface-electrode trap to or below a temperature of 150 K.

[0008] According to another embodiment, a cryogenic surface-electrode trap for trapping charged or polar particles at or below a temperature of 150 K is provided. The cryogenic surface-electrode trap includes a silicon substrate having a front surface and a back surface and at least one planar radio frequency (RF) electrode and at least one planar direct current (DC) electrode. The planar RF and DC electrodes are formed on the front surface of the silicon substrate and are configured to generate a trapping potential for trapping the charged or polar particles above the electrodes. The planar RF and planar DC electrodes include a first RF electrode extending substantially parallel to the front surface of the substrate, and a first DC electrode extending substantially parallel to the front surface of the substrate and being adjacent to the first radio frequency electrode. The silicon substrate has a trench formed therein that separates the first RF electrode from the first DC electrode to provide electrical insulation of these electrodes. The planar RF and DC electrodes are either formed directly on the front surface of the silicon substrate, or the planar RF and DC electrodes are formed directly on a thermal silicon oxide layer formed by thermal oxidation of at least the front surface of the silicon substrate.

[0009] A further embodiment provides for the use, at a temperature of 150 K or less, of a surface-electrode trap for trapping charged or polar particles. The surface-electrode trap includes a silicon substrate having a front surface and a back surface. The surface-electrode trap further includes a first radio frequency (RF) electrode extending substantially parallel to the front surface of the substrate, and a first direct current (DC) electrode extending substantially parallel to the front surface of the substrate and being adjacent to, and electrically insulated from, the first RF electrode.

[0010] According to a further embodiment, a method of manufacturing a cryogenic surface-electrode trap configured for trapping charged or polar particles at temperatures of 150 K or less is provided. The method includes providing a silicon substrate having a front surface and a back surface, forming undercut trenches in the front surface of the silicon substrate, and subsequently depositing a conductive layer on the front surface of the silicon substrate, wherein the trenches electrically insulate regions of deposited conductive material from each other that constitute surface electrodes of the surface-electrode trap.

[0011] Embodiments are also directed to methods for operating the disclosed system. These method steps may be performed manually or automated, e.g. controlled by a computer programmed by appropriate software, by any combination of the two or in any other manner.

[0012] Further advantages, features, aspects and details that can be combined with embodiments described herein are evident from the dependent claims, the description and the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] A full and enabling disclosure to one of ordinary skill in the art is set forth more particularly in the remainder of the specification including reference to the accompanying drawings wherein:

Fig. 1 shows a known surface-electrode ion trap;

Fig. 2 shows a surface-electrode trap according to embodiments described herein;

Fig. 3 shows a system for trapping charged or polar particles according to embodiments described herein;

Figs. 4 shows a surface-electrode trap according to embodiments described herein;

Figs. 5-6 show images of a surface-electrode trap according to embodiments described herein;

Fig. 7 shows a schematic flow diagram illustrating a method of manufacturing a surface-electrode trap according to embodiments described herein;

Figs. 8-15 illustrate different states of the trap during a method of manufacturing a surface-electrode trap according to embodiments described herein;

Fig. 16 shows a perspective view of a surface-electrode trap according to embodiments described herein;

Figs. 17-20 show SEM microscope images of cuts through the surface-electrode trap of Figs. 5-6, illustrating a trench structure;

Figs. 21-24 show images of a system for trapping charged or polar particles according to embodiments described herein;

Fig. 25 shows an equivalent circuit diagram of the system of Fig. 24;

Fig. 26 shows a plot of trap quality factor against temperature of the system of Fig. 24;

Figs. 27-29 show plots and a table of further characteristics of the system of Fig. 24; and

Figs. 30-35 illustrate a method of forming vias or slots through a substrate of a surface-electrode trap according to embodiments described herein.

DETAILED DESCRIPTION

[0014] Reference will now be made in detail to the various exemplary embodiments, one or more examples of which are illustrated in each figure. Each example is provided by way of explanation and is not meant as a limitation. For example, features illustrated or described as part of one embodiment can be used on or in conjunction with other embodiments to yield yet further embodiments. It is intended that the present disclosure includes such modifications and variations.

[0015] Within the following description of the drawings, the same reference numbers refer to the same components. Generally, only the differences with respect to the individual embodiments are described. The structures shown in the drawings are not necessarily depicted true to scale but rather serve the better understanding of the embodiments.

[0016] Fig. 1 shows a known planar, linear ion trap. The ion trap includes direct current (DC) electrodes 10 and radio-frequency (RF) electrodes 20 arranged on a quartz or alumina substrate 1. The outer DC electrodes are segmented while the central DC electrode is not. The RF fields applied to the RF electrodes 20 can confine ions in the vertical direction (direction perpendicular to the plane of the substrate) and in the lateral direction (direction in the plane of the substrate and perpendicular to the trap axis defined by the central DC electrode). The ions are trapped at an RF-null of the generated RF fields that extends along the trap axis above the central DC electrode. The static or quasistatic fields generated by the DC voltages applied to the segmented DC electrodes can confine the ions with respect to the trap axis. Thereby, a linear ion trap is realized. The DC and RF electrodes are typically connected to DC and RF voltage drives via leads that run along the surface of the substrate on which the electrodes are arranged. The leads and voltage drives are not shown in Fig. 1.

[0017] An ion trap of this kind is, e.g., described in PRL 96, 253003 (2006). According to the authors of this PRL article, the trap well depth for the surface-electrode trap is fairly shallow. In US 7 180 078 B2, it is proposed to segment the central DC electrode in order to provide enhanced positional control over the ions. To this end, DC control voltages are applied to the respective segments.

[0018] According to a first embodiment of the present invention, a surface-electrode trap and a system for trapping charged or polar particles is provided. Controlled interactions between the trapped particles may be performed. Charged particles are typically positively charged. In particular, the charged particles may be ions. The ions may exemplarily be ⁴⁰Ca⁺, ¹³⁸Ba+, ⁴³Ca+, ⁹Be+, ²⁴Mg+, ²⁷Al+, ⁸⁸Sr+ or mixtures thereof. Ions of the type ⁴⁰Ca⁺ have electronic and spin states advantageous for quantum manipulations, e.g., with the aid of lasers. In other embodiments, the charged particles are charged dust particles. In further embodiments, the particles are polar particles such as polar molecules which can be trapped due to their intrinsic or induced dipole moment. The trap may be a surface-electrode ion trap, and the system can include such a trap. The trap and the system may be adapted for trapping ions and performing controlled quantum interactions between them. A quantum interaction is an interaction wherein quantum coherence between the particles is maintained. For instance, a quantum interaction could be a quantum gate operation or quantum entangling operation that may be required for gate-based or measurement-based quantum computation. A quantum interaction may also be an interaction for quantum simulation of quantum systems. Unless stated otherwise, the trap will be referred to as an ion trap in the following and the charged particles will be called ions, but without intending limitation and without excluding polar particles.

[0019] The ions may function as carriers of quantum information, e.g., as qubits or higher quantum logical entities (qutrits etc.). The theory of quantum computation is best developed on the basis of qubits at present. Ion qubits can be well isolated from the environment in ion traps and have long coherence times. However, for quantum computation, the ions need to interact, and the quantum operations need to be faster than the coherence time. Two- or multi-qubit operations, also called quantum gates or quantum gate operations, are needed for the creation of quantum entanglement or the implementation of a universal set of quantum gates. For ion qubits multi-qubit operations can be mediated by the Coulomb interaction and are dependent on distance between the ions. Further, to perform complex quantum algorithms it is advantageous to increase the number of qubits participating in the computation. The number of qubits that one can individually control should therefore be scalable.

[0020] According to embodiments described herein, the surface-electrode trap includes a silicon substrate. The silicon substrate may be a high-purity silicon substrate. The specific electric resistivity at 300 K may be larger than 5·10² Ωcm or 5·10³ Ωcm, or even larger than 10⁴ Ωcm or 10⁵ Ωcm. The specific electric resistivity at 25 K may be larger than 10⁷ Ωcm or 10⁹ Ωcm, or even larger than 10¹⁰ Ωcm or 10¹² Ωcm. The silicon substrate is typically an intrinsic silicon substrate, i.e., an undoped silicon substrate. The silicon substrate may be high-purity float-zone silicon wafer. Usually, a silicon substrate essentially consists of silicon, i.e., apart from the low amount of naturally occurring impurities.

[0021] Alternatively, the substrate may be a silicon carbide substrate, a germanium substrate or a gallium arsenide substrate. It could be some other semiconductor substrate as well. A silicon substrate has the advantage that large wafers of high purity are available at a reasonable price, that the structuring techniques and the silicon technology in general are the most advanced and that oxides may be grown on or otherwise deposited on silicon whereas this may be difficult or impossible for other semiconductors such as GaAs. In the following, reference will be made to a silicon substrate, but further embodiments feature other semiconductor substrates.

[0022] The silicon substrate has a front surface and a back surface. The side of the front surface will be called the front side of the substrate or of the trap, and the side of the back surface will be called the backside of the substrate or of the trap. Typically, the front and back surface are parallel to each other. The thickness of the substrate, i.e., the distance between the front and back surface, may be from 300 µm to 1000 µm, typically from 400 µm to 700 µm, more typically from 500 µm to 600 µm, e.g., about 525 µm. The substrate may be planar, and, in particular, be a wafer or a chip. The substrate is typically adapted to provide structural integrity to the trap.

[0023] The surface-electrode trap includes planar electrodes. The planar electrodes may include at least one planar radio-frequency electrode (RF electrode) and at least one planar direct current electrode (DC electrode). Typically, the trap includes more than one DC electrode. The DC electrodes may be segmented electrodes. DC voltages applied to DC electrodes include static voltages and quasistatic voltages, i.e., voltages that very slowly at timescales several orders of magnitude slower than radio frequencies. The RF electrode(s) may be dedicated RF electrodes, and the DC electrodes may be dedicated DC electrodes. Herein, the term "dedicated" means that the electrodes are configured to be driven by DC or RF voltages, respectively, or are arranged such that a trapping potential can be created by driving dedicated DC electrodes with DC voltage and RF electrodes with RF voltage. This may include that a dedicated DC electrode is connectable to a DC voltage source and a dedicated RF electrode is connectable to an RF voltage source. The RF voltage source may include an RF voltage drive, typically an RF voltage drive for providing high-voltage to the RF electrode. A dedicated DC electrode is unconnected to an RF voltage drive. A dedicated DC electrode may be a ground electrode, i.e., an electrode kept at ground potential. By using dedicated electrodes the complexity of the circuit is kept low. Capacitive coupling may exist between RF electrodes driven by RF voltages. Regarding dedicated DC electrodes, capacitive coupling between these electrodes does not exist and need not be considered for designing the trapping potentials.

[0024] The planar electrodes are formed on the front surface of the silicon substrate. They are configured to generate a trapping potential for trapping charged or polar particles above the planar electrodes. Here, the term "above" means in a direction perpendicular to the front surface, more specifically the direction oriented not towards the back surface, but outward from the front surface. The charged or polar particles may be trapped in free space above a plane containing the planar electrodes. The planar electrodes include a first RF electrode and a first DC electrode. The planar electrodes may include second, third, fourth etc. RF electrodes and/or second, third, fourth etc. DC electrodes. The first RF electrode extends substantially parallel to the front surface of the substrate. The first DC electrode extends substantially parallel to the front surface of the substrate. The first RF electrode and the first DC electrode may be coplanar, meaning that they lie in one plane. The planar electrodes may all be coplanar. The first RF electrode is adjacent to the first DC electrode and vice versa. Here, the term "adjacent" means adjacency in a direction parallel to the front surface of the substrate. Directions parallel to the front surface will also be called "lateral directions" (x- and y-directions), and directions perpendicular to the front surface will be called "vertical directions" (z-directions).

[0025] The first RF electrode is electrically insulated from the first DC electrode, and vice versa. Second, third etc. RF or DC electrodes are also electrically insulated from each other, if present. The silicon substrate may have a trench formed therein. In particular the trench may be formed into the substrate from the front surface of the substrate towards its back surface. The trench may be formed such that it does not penetrate the substrate. The trench bottom may lie within the substrate. The trench may separate the first RF electrode from the first DC electrode. The electric insulation between these electrodes may be provided by the trench. The trench may be empty in a region between these electrodes, i.e., not filled with a material in that part. The electrodes may thus be separated by a gap. There may be electrically conductive material at the bottom of the trench which is not electrically connected to the electrodes. The trench may alternatively be filled with an insulating material in the region between said electrodes. The trench may have a width of from 1 µm to 150 µm, typically from 5 µm to 100 µm. The trench may have a portion with a width of from 5 µm to 20 µm and a second portion with a width of from 80 µm to 120 µm. The trench may have a depth of from 10 µm to 300 µm, typically of from 60 µm to 170 µm, more typically from 80 µm to 120 µm, such as about 100 µm. These values may alternatively only relate to a trench with a width of from 5 µm to 20 µm, such as about 10 µm. The trench may be deeper in portions with a larger width. There may be further trenches of the same or similar kind separating the first RF electrode and/or the first DC electrode from other planar electrodes, if present. The surface-electrode trap may include a trench structure formed in the substrate that includes trenches separating the planar electrodes of the trap.

[0026] The trench(es) may be undercut trench(es). A trench is said to be undercut if there is a portion of it that is wider than the top of the trench at the front surface of the substrate. The wider portion is typically at the bottom. A trench is said to be undercut by distance x if the portion that is wider than the top of the trench is wider by distance x than the top of the trench at the front surface of the substrate. The trench may be undercut by from 0.5 µm to 5 µm, typically from 0.5 to 3 µm, such as about 1.5 µm. A trench is said to be undercut by distance x per depth y if the portion that is wider than the top of the trench is at a depth y from the front surface of the substrate and is wider by distance x than the top of the trench at the front surface of the substrate. The trench may be undercut by from 0.5 µm to 5 µm per 100 µm depth, typically from 0.5 to 3 µm per 100 µm depth, such as about 1.5 µm per 100 µm depth. The sidewalls of the trench may fair divergently from the top of the trench towards its bottom. The sidewalls may be substantially straight in vertical direction. Undercut trenches allow for a manufacturing process, described further below with respect to Fig. 7 and Figs. 8-15, that is reliable and does not involve complex and costly steps.

[0027] The first RF electrode and the first DC electrode may be formed on the front surface of the silicon substrate such that the distance between these electrodes and the front surface is not larger than 10 µm, typically not larger than 5 µm, even more typically not larger than 3 µm, e.g., about 2 µm. There may be no electrically conductive layer between these electrodes and the front surface of the silicon substrate, in particular no metal layer. The first RF electrode and the first DC electrode may be formed directly on the front surface of the silicon substrate. The expression "directly on" means that the silicon substrate and the electrodes are in direct physical contact with each other. In other words, the distance between said electrodes and the front surface is zero in this case.

[0028] Alternatively, a barrier layer may be formed on at least the front surface the silicon substrate, typically on all surfaces of the silicon substrate. The barrier layer is configured to hinder or prevent diffusion of the RF or DC electrode material into the silicon substrate. The barrier layer may be an insulator layer, e.g., a semiconductor oxide layer. The semiconductor material in the semiconductor oxide layer may be the same material as that of the semiconductor substrate, e.g. silicon, or may alternatively be a different semiconductor material. The barrier layer may be a thermal oxide layer. A thermal oxide layer is a layer obtained by thermal oxidation of silicon substrate surface(s) in question and is therefore formed directly on the silicon substrate surface(s) in question. The barrier layer, e.g., a thermal oxide layer, if present, has a thickness larger than zero, and typically smaller than or equal to 10 µm, or 5 µm or 3 µm, such as about 2 µm. The first RF electrode and the first DC electrode may be formed directly on the barrier layer, such as directly on a thermal oxide layer.

[0029] The first RF electrode and the first DC electrode may be formed from the same material or from the same materials. The first RF electrode and the first DC electrode may be metal electrodes. They may include, or consist of, gold. They may include, or consist of, other noble metals, e.g., platinum. Noble metals have the advantage that they do not form a natural oxide which could trap surface charges, e.g., introduced by lasers, where such surface charges could negatively influence the trapping potentials. The electrodes may include, or consist of, titanium, chromium, aluminum, niobium or copper. Copper is inexpensive, niobium and aluminum become superconductors at low temperatures. The metal electrodes may include, or consist of, one, two, three or more vertically stacked metal layers. The metal layers may be regarded as sub-layers of a conductive layer representing, when structured accordingly, the metal electrodes. The metal layers may be formed of the materials specified above. Titanium and chromium may be used as thin bonding layers between the silicon substrate and a main electrode layer, e.g., a gold layer. The bonding layer may be at least 10 or even at least 100 times thinner than the main electrode layer. For instance, a metal electrode may consist of a titanium layer and of a gold layer above the titanium layer. Alternatively, the electrodes could be formed as semiconductor electrodes, e.g., by doping the front surface of the silicon substrate. Metal electrodes have the advantage that their conducting properties improve in cryogenic environments, whereas the conducting properties of semiconductors deteriorate. Other planar electrodes, if present, may also be formed in one of these ways and have the same or similar properties.

[0030] The surface-electrode trap may be a cryogenic surface-electrode trap. The term "cryogenic trap" as used herein means that the trap is not operable at about room temperature. In particular, a cryogenic trap is operable only at temperatures below about150 K. Above this temperature, the quality factor of the trap may be too low (see, e.g., Fig. 26 and the description thereof). Some cryogenic traps may be operable only at temperatures below 100 K or below 80 K, or even at or below the temperature of liquefaction of nitrogen. Some cryogenic traps may be operable only at temperatures below 40 K. The cryogenic surface-electrode trap may have a temperature of below 100 K, below 80 K, below 40 K, below 35 K, below 30 K, below 20 K or even below 15 K, such as about 10 K or about 4 K. The trap may be operable, for any semiconductor substrate, at least at or below temperatures where the free charge carriers of that semiconductor substrate freeze out.

[0031] A system for trapping charged or polar particles according to embodiments of the invention includes the surface-electrode trap described herein and a cryostat. The cryostat is configured for cooling the surface-electrode trap to or below a temperature of 150 K, typically to or below a temperature of 100 K, 80 K, 77 K, 40 K, 35 K, 30 K, 25 K, or even 20 K. The cryostat may be configured to cool the trap to or below 10 K, or even to or below 4 K. The cryostat may be configured to cool the trap to or below the temperature of liquefaction of helium. In the system, the surface-electrode trap is positioned within the cryostat.

[0032] Fig. 2 shows an embodiment of a cryogenic surface-electrode trap 100. The surface-electrode trap 100 includes a silicon substrate 101 having a back surface 102 and a front surface 104. The surface-electrode trap 100 includes a DC electrode 110 and an RF electrode 120 formed on the front-surface of the substrate 101 and extending coplanar in a plane 106. The electrodes 110 and 120 are formed from a material 105 directly on the front surface 104 of the silicon substrate or directly on a thermal oxide layer (not shown) covering at least the front surface 104. A trench 132 separates the adjacent electrodes 110 and 120 and electrically insulates them from each other.

[0033] The trap may include further planar electrodes, some or all of which may also extend coplanar in plane 106. The electrodes 110 and 120 may be gold electrodes or other metal electrodes, such as titanium, chromium, niobium, platinum, aluminum or copper electrodes, commonly formed by metal deposition, and thus having the same thickness and composition.

[0034] Fig. 3 shows an embodiment of a system 300 for trapping charged or polar particles. The system includes the cryogenic surface-electrode trap 100 with the silicon substrate 101. The system 300 further includes a cryostat 350 that is adapted to cool the trap 100 to or below a temperature of 150 K, e.g., to or below a temperature of 40 K or even 20 K.

[0035] Embodiments of the cryogenic surface-electrode trap and the system for trapping charged or polar particles described herein provide several advantages. The use of a silicon substrate permits easier and more reliable fabrication as will be describe in more detail later, in particular with respect to Figs. 7-15 and 30-35. Further, while the RF power dissipation, also called RF loss, of silicon at room temperature is high, the RF loss decreases by several orders of magnitude in the cryogenic environment. Details will be described later, e.g., with respect to Fig. 26. The cryogenic trap has no need for a shielding electrode between the DC and RF electrodes and the silicon substrate, and so the trap design and manufacturing can be simplified. The cryogenic environment provides several additional advantages. Ultra-high vacuum can be attained within a few hours due to cryogenic pumping, without baking the system. This facilitates fast set-up times for trap installation (shorter than 1 day). Furthermore, operation at liquid helium temperatures reduces the rate at which higher motional states of the particles are excited. This rate may be lowered by around two orders of magnitude. This is beneficial as it increases the coherence time of the motional quantum state of the particles (ion motional state), which is used to transfer quantum information between different ions.

[0036] The cryostat of the system may include a metal shield, e.g., a copper shield. The metal shield may minimize incident blackbody radiation and/or reduce the number of background gas molecules at the trapping site(s). The background molecules may freeze on the shield walls. The system may include a vacuum chamber for providing a vacuum environment to the surface-electrode trap. The vacuum may be a high vacuum or ultra-high vacuum. High vacuum is said to be present when a residual pressure of less than 10^-3 mbar is achieved, ultra-high vacuum is said to be present when a residual pressure of less than 10^-9 mbar is achieved. The vacuum may even be extremely high vacuum, said to be present when a residual pressure of less than 10^-12 mbar is achieved. The system may include a cryogenic pump for establishing the vacuum environment by cryogenic pumping. The system may include one or more lasers for at least one of: (i) ionization of atoms, (ii) cooling ions (iii) addressing the ions for quantum manipulation, and (iv) imaging the ions. Loading ions into the trap may include ionizing and cooling the ions. There may be one or more lasers for: (v) loading the ions into the trap by ionizing and cooling the ions.

[0037] A specific embodiment of a linear surface-electrode trap will be described with respect to Figs. 4-6. Of course, embodiments are not limited to such linear traps, but may exhibit more complicated designs, e.g., as described in the patent US 8,426,809 incorporated by reference in its entirety and featuring traps with arrays of trapping sites.

[0038] Fig. 4 shows an embodiment of a silicon surface-electrode ion trap 400. The trap 400 includes a silicon substrate 401 having a front surface oriented in the plane of drawing (x- and y-directions as shown by the arrows on the lower left of Fig. 4). A trench structure 430 has been manufactured into the front surface of the silicon substrate. The trenches extend into the plane of drawing (in negative z-direction). The trench 432 running around a DC center electrode 410 separates this center electrode 410 from a surrounding RF electrode 420. The DC center electrode 410 has a terminal 411 at one end. It also has a terminal at the other end which is not labeled. The RF electrode 420 has a terminal 421 at one end. It also has a terminal 422 at the other end. A trench 434 running around the RF electrode 420 separates the RF electrode 420 from outer DC electrodes 412 and from a region 408 outside of the trap electrodes. This region outside of the trap electrodes may be set to ground potential during operation, and will be called ground electrode 408 hereinafter. Of the 14 outer DC electrodes 412 only one is labeled for simplicity and will be discussed as a representative of all the other outer DC electrodes. A trench 436 runs around the outer DC electrode 412, a runway 413 and a terminal 414 of the DC electrode 412. The runway connects the outer DC electrode 412 with the terminal 414. The trench 436, which has a common part with the trench 434, separates the outer DC electrode 412 from the RF electrode 420, the other outer DC electrodes and from regions outside of the trap electrodes. A gold layer 405 has been deposited onto the front surface of the silicon substrate, and the trench structure including the trenches 432, 434 and 436 electrically insulates the planar electrodes from each other and from the ground electrode 408.

[0039] The width of the center DC electrode 410 (in x-direction) is 250 µm in the center part, the width of the RF electrode 420 on the left side of the center DC electrode 410 is 400 µm and the width of the RF electrode 420 on the right side of the center DC electrode 410 is 200 µm. The DC electrode 410 is thus asymmetrically positioned within the RF electrode. An asymmetric positioning and thus unequal widths of the RF electrode(s) on different sides of the center DC electrode are advantageous for laser cooling the ions. Aligning lasers used to Doppler cool the ions parallel to the plane of the trap minimizes scatter from the front surface of the trap. To efficiently cool the ions along all three principal axes of their motion, each axis should have a projection along the direction of the cooling laser beam. Consequently, it is advantageous if none of the principal axes of motion is perpendicular to the trap surface. When the RF electrodes are fabricated with unequal widths, this ensures that the two radial principal axes both have a component parallel to the trap surface. The dimension of the outer DC electrodes 412 is 350 µm in y-direction and 1100 µm in x-direction. The ions are trapped above the center DC electrode 410, wherein several ions may be aligned along the y-direction which is the trap axis here. The RF electrode 420 and the outer DC electrodes 412 provide the trapping potential such that the ion(s) are trapped at about 230 µm above the center DC electrode 410. The trenches are about 10 µm wide at their top, but are wider in those parts adjacent to the terminals of the electrodes. The wider parts adjacent to the terminals reduces capacitive coupling between adjacent electrodes.

[0040] Fig. 5 shows a photograph image taken through an optical microscope of the surface-electrode trap 400 before the gold layer 405 has been applied to form the electrodes. In Fig. 5, the silicon substrate 401 is shown into which the trench structure 430 has been manufactured. Fig. 6 shows the same trap 400 after deposition of the gold layer 405, wherein the trench structure 430 forms the different electrodes by separating regions of the gold layer 405 from each other and providing electrical insulation between these different electrodes.

[0041] According to further embodiments, as schematically illustrated in Fig. 7, a method 500 of manufacturing a cryogenic surface-electrode trap is provided. The method can be used to manufacture the surface-electrode traps described herein. The method includes the following. At reference sign 510, providing a silicon substrate having a front surface and a back surface, at reference sign 520, forming undercut trenches in the front surface of the silicon substrate, and, at reference sign 540, subsequently depositing a conductive layer on the front surface of the silicon substrate, wherein the trenches electrically insulate regions of deposited conductive material from each other that constitute surface electrodes of the surface-electrode trap. The conductive layer may be a metal layer, e.g., of gold or another material described hereinabove.

[0042] The following optional features are shown in dotted lines in Fig. 7. Depositing the conductive layer may include, shown at reference sign 542, directly depositing the conductive layer on the front surface of the silicon substrate. Alternatively, the method may include, shown at reference sign 534, thermal oxidation of at least the front surface of the silicon substrate to form a thermal silicon oxide layer. In this case, depositing the conductive layer may include, shown at reference sign 544, directly depositing the conductive layer on the thermal silicon oxide layer.

[0043] Forming the undercut trenches may include forming a patterned photoresist on the front surface of the silicon substrate, shown at reference sign 522, performing deep reactive ion etching to form the undercut trenches, shown at reference sign 524, and removing the photoresist, shown at reference sign 526. Removing the photoresist may include exposing the photoresist to a plasma such as an oxygen plasma.

[0044] Figs. 8-15 illustrate different states of the trap as it is manufactured according to such a method. Fig. 8 shows a silicon substrate 701 having a back surface 702 and a front surface 704. A photoresist layer 760 has been formed on the front surface. Fig. 9 illustrates the process of developing the photoresist layer 760 by UV radiation in a pattern defined by the photo mask 770. Fig. 10 shows the patterned photoresist layer 760 after the portions of the photoresist layer that were exposed to UV radiation have been removed. The patterned photoresist layer is used for deep reactive ion etching to form a trench structure 730 of undercut trenches in the silicon substrate 701. For instance, a trench 732 has a trapezoidal cross section such that it is wider at a position 732-2 closer to the bottom of the trench than at a position 732-1 closer to the front surface 704. Fig. 12 shows the silicon substrate 701 with the manufactured trench structure 730 after the photoresist 760 has been removed.

[0045] Fig. 13 shows an embodiment where a metal layer 705, such as a gold layer, has been deposited directly on the silicon of the silicon substrate 701. This alternative may be used where diffusion of the electrode material into the substrate is not pronounced. Figs. 14 and 15 illustrate another alternative, where, following the state of Fig. 12, the substrate 701 has been thermally oxidized such that a thermal oxide layer 740 covers the substrate surfaces, including the front surface 704. The metal layer 705 is deposited directly on the thermal oxide layer 740. This alternative is advantageous where diffusion of the electrode material into the substrate poses a problem, but requires a more complicated method than the alternative illustrated in Fig. 13. In both cases, the undercut trenches prevent the deposited electrode material, e.g., gold, to form a connected layer. Some of the deposited electrode material may be found at the bottom of the trench, but does not disturb the electrical insulation between the electrodes provided by the trench structure 730. Thus, the material deposited at the trench bottom need not be removed.

[0046] The method according to embodiments described herein is therefore simple to carry out and provides for reliable manufacturing of silicon-based surface-electrode traps.

[0047] Fig. 16 shows a perspective view of a silicon-based surface-electrode trap 700 manufactured in this way. The trap 700 may be identical to the trap 400 shown in Figs. 4-6, and reference signs starting with the digit 7 in Fig. 16 may then correspond to the features having the same last two digits, but starting with the digit 4 in Figs. 4-6. The trap 700 includes the trench structure 730 with trenches 732, 734 and 736 separating DC electrodes 710 and 712 and RF electrodes 720 and 722 (which may actually be only one RF electrode surrounding the DC electrode 710 as shown in Fig. 4) from each other. The trench structure 730 partitions the electrode layer 705 and thus forms the individual electrically insulated planar electrodes.

[0048] According to an embodiment of the method used for manufacturing the trap shown in Figs. 4-6, the following features are realized. High-purity float-zone silicon wafers with a diameter of 100 mm, a thickness of 525 µm, and with a specific resistivity larger than 5000 Ωcm were used. The wafers were coated by the positive photoresist AZ1518 with a thickness of 2.4 µm. The resist was patterned by optical lithography. The wafers were deep reactive ion etched by gas chopping based on SF₆ and C₄F₈ to create trenches with slight undercuts separating the different electrodes. The 10 µm gaps between the electrodes were etched to a depth of about 100 µm with an undercut of about 1 µm. The resist was then removed by O₂ plasma cleaning. A 2 µm thick SiO₂ layer was grown on the silicon surface by thermal oxidation to prevent metals from diffusing into the silicon. Each wafer provided 52 traps, and the individual trap chips were separated by laser scribing.

[0049] To form the electrodes, titanium with a thickness of 2 nm and a gold layer with a thickness of 500 nm were deposited on the substrate surface by electron-beam evaporation. Due to the undercuts, there were no electrical connections between the different electrodes and no further lift-off or etching steps were necessary. Also, no further cleaning steps were necessary, and, to avoid any contamination of the surface, contact of gold electrodes with liquids was avoided.

[0050] Fig. 17 shows an SEM image of a cross-cut through the wafer 401 of Fig. 4 at the terminal 414 of outer DC electrode 412. The terminal 414 and the runway 413 to the DC electrode 412 are visible, as are similar structures of other outer DC electrodes. The trench 436 is visible, which, at the front surface 404 of the silicon substrate 401, is about 10 µm wide alongside and between the runway 413 and the terminal 414, but is wider at the far end of the terminal 414. On the far end of the terminal, i.e., on the right side of terminal 414 in Fig. 17, the trench 436 is about 100 µm wide at the front surface 404. The trench 436 is about 100 µm deep in the parts where it is about 10 µm wide, and is about 170 µm deep where it is about 100 µm wide. The trench is undercut by about 1.7 µm per 100 µm depth.

[0051] Fig. 18 shows an SEM image of a cross-cut through a trench in the silicon substrate 401. The depth D of the trench is about 108 µm. The region marked with reference sign A is shown in higher magnification in Fig. 19, and the region marked with reference sign B is shown in higher magnification in Fig. 20. The width W1 of the trench at the front surface of the silicon substrate 401 is about 12 µm as shown in Fig. 19, and the width W2 of the trench near its bottom is about 13.7 µm as shown in Fig. 20. As a result of the trench formation process, namely deep reactive ion etching by gas chopping based on SF₆ and C₄F₈, the sidewalls of the trenches can be seen to exhibit the characteristic undulated form with undulations in the sub-micrometer range. However, for all practical purposes the sidewalls can be considered to be substantially straight in vertical direction.

[0052] The surface-electrode trap was mounted on a copper carrier. Fig. 21 shows the copper carrier 480. To ensure good thermal contact between the trap and the carrier, the trap was coated on the back surface of the substrate with a thin layer of heat-conducting grease and then clamped in place by two stainless-steel forks 470. Fig. 22 shows a picture of silicon-based surface-electrode trap 400 taken through the objective of a light microscope. The steel forks 470, the gold layer 405, the trench structure 430 and the terminals 411, 414 and 421 can be clearly seen.

[0053] Printed circuit boards (PCBs) supporting the DC filters and the LC resonator were glued to the carrier. The PCBs are shown in Fig. 24, namely two PCBs 496 and 498 acting as low pass filters with a cut-off frequency of about 4.8 kHz, a PCB 492 acting as a capacitive divider, and a PCB 494 acting, together with the trap 400, as a tunable RLC circuit providing RF drive voltage to the RF electrode 420. The trap electrodes were connected to the PCBs by 25 µm thick gold wirebonds. Fig. 24 shows gold wirebonds 486 and 488 connecting the circuitry of PCBs 496 and 498 to the terminals 414 of the outer DC electrodes 412, and shows gold wirebonds 482 connecting the circuitry of PCB 492 to the terminal 421 of the RF electrode 420, and shows gold wirebonds 484 connecting the circuitry of PCB 494 to the terminal 411 of the center DC electrode 410, to the terminal 422 of the RF electrode 420, and to the ground electrode 408. Fig. 23 shows a picture taken through the objective of a light microscope showing one of the forks 470, and the gold wirebonds 482 connected to the terminal 421 of the RF electrode 420. The copper traces on the PCBs were partially gold electroplated to increase the adhesion of the bonding wires. The entire fabrication and assembly process is performed in a cleanroom to reduce surface contamination. The only exception to this was installing the trap in the cryostat itself which was not located in a cleanroom, though this step took less than ten minutes.

[0054] A closed-cycle, two-stage, Gifford McMahon cryostat was used to cool the silicon ion trap to 10 K. Fig. 24 shows the cryostat 450. It is equipped with a vibration-isolation system to reduce the vibrations at the trap to around 100 nm at 2 Hz. The trap was attached to the second cooling stage of the cryostat. It is enclosed by a copper shield, also cooled to 10 K. This minimizes the incident blackbody radiation and reduces the number of background gas molecules at the trapping site, as they freeze on the shield walls. To reduce surface contamination caused by molecules freezing out on the trap electrodes during the cool down, the second stage of the cryostat was kept at 320 K until the first stage has reached a temperature of 240 K. Thereafter the second stage was cooled to 10 K, while the first stage reached a final temperature of 50 K. ⁴⁰Ca⁺ ions were loaded from a neutral Ca-beam produced by a resistively heated oven located within the vacuum chamber but not mechanically connected to the cold stage. The atoms were introduced to the trapping region through a small hole in the copper shield (diameter about 3 mm) and were ionized by a two-photon process in the trapping region.

[0055] More specifically, the ions were trapped 230 µm above the center electrode 410 by applying an RF voltage of amplitude U₀ = 140V and frequency Ω_T/2π = 20.6 MHz to the RF electrode 420. The voltage was provided by an lumped-circuit RLC resonator driven by a function generator and created a trapping potential with trap depth of 75 meV. The power dissipation in the resonator goes as P_D = U₀²C Ω_T / 2Q where C is the resonator capacitance and Q the quality factor of the resonator. To keep P_D low, C should be small. This was achieved by locating the resonator in vacuum next to the trap on the cold stage of the cryostat. This reduced C to 9.5 pF, which is mainly limited by the capacitance of the RF electrode. The power necessary for trapping is less about 10mW, which is well below the cryostat's cooling power of 500mW and increases the temperature measured next to the trap by only 0.2K.

[0056] The lumped-circuit RLC resonator was formed by a copper air-coil inductor with an inductance of 6.3 µH mounted next to the trap (on the backside of PCB 494 in Fig. 24), a capacitance of 9.5 pF provided by the trap and by a capacitive voltage divider circuit board 492. The capacitors are arranged on the backside of the circuit board 492 in Fig. 24. The circuit's resonance frequency is 20.6 MHz at 10 K. The capacitive divider, which allows the measurement of the voltage on the RF electrodes, has a ratio of 1:400 and a total capacitance of 2.4 pF. Furthermore, there is a matching network for matching the LC circuit to 50 Ω. This consists of a tunable capacitor 493, tunable in the range of 12-100 pF, and an inductor 495 of 186 nH connected in series and parallel, respectively.

[0057] For improving the trapping performance all DC electrodes were RF-grounded by installing capacitors as close as possible to the DC electrodes. For this reason, small surface-mounted NP0 capacitors 499 with a capacitance of 470 pF were put about 15mm from the electrodes. Additionally, RC low-pass filters on the PCBs 496 and 498 were used to filter RF noise on the DC lines. The filters each consist of a 100 Ω thin-film resistor (on the backside of PCBs 496 and 498 in Fig. 24) and a 330 nF NP0 capacitor 497 placed about 30 mm from the trap. The cut-off frequency of these filters is about 4.8 kHz. The resistors and capacitors used are cryo-compatible and do not significantly change performance during cooling. In addition to these filters there are 6th-order RC low-pass filters outside of the vacuum chamber with a cut-off frequency of 80 Hz.

[0058] Fig. 25 shows an equivalent circuit of the RLC resonator realized by the system of Fig. 24. The capacitive divider D1/D2 is realized on PCB 492, the capacitance C stems mainly from the RF electrode of the trap, the inductance L stems mainly from the air-coil inductor mounted on the backside of the PCB 494. The matching network is realized by capacitor 493 on PCB 494 (capacitance M2), and by the air coil 495 (inductance M1).

[0059] The characterization of the RF resonator (including the trap 400) as a function of temperature is shown in Fig. 26. The inductor of the LC resonator is provided by a copper coil with an air (vacuum) core and the capacitance primarily comes from the trap RF electrode. The temperature was measured by a silicon diode 491 mounted on the copper trap carrier. Q follows the relation 1/Q = 1/Q_L + 1/Q_C, where Q_L and Q_C are the quality factors of the inductor and the capacitor, respectively.

[0060] At room temperature the silicon substrate, which supports the RF electrodes, has a very high loss tangent, tan δ, of 1.5 at the driving frequency Ω_T/2π= 20.6 MHz. For comparison, under the same conditions, tan δ of fused silica is around 10^-4. Due to the high loss tangent at room temperature the entire RF driving power is absorbed by the silicon substrate. There is no measurable resonance. Using an impedance analyzer, the resonator Q was indistinguishable from zero. In contrast, a quality factor of 400 was measured in a similar trap fabricated on a fused-silica substrate and operated at room temperature. Without wishing to be bound to any particular theory, it is believed that cooling leads to a reduction of the charge-carrier concentration in the silicon. Below 150 K a steep decrease of the electrical conductivity and loss tangent was measured. The quality factor Q rises steeply at a temperature below about 150 K and becomes higher than 400, comparable to the quality factor of the trap based on the fused silica substrate operated at room temperature. The cryogenic traps according to embodiments described herein are thus operable below temperatures of 150 K. When cooling further down, it is believed that electron-hole pairs freeze out. The curve representing the quality factor Q rises again steeply below about 40 K to achieve a quality factor of more than 1000. At about 25 K the silicon becomes an insulator. In addition to these changes in the silicon, the electrical conductivity of the coil increases with decreasing temperature, and therefore the inductor quality factor, Q_L, goes up. The combined effect of the changes in the silicon and the increasing quality factor Q_L are believed to be responsible for the second steep rise in the overall quality factor Q at about 40 K in Fig. 26. Increasing Q_C and Q_L leads to an increasing overall resonator quality factor, Q, with decreasing temperature, as shown in Fig. 26. Below 20K the value of Q > 1200 is comparable to that measured with a fused-silica trap at the same temperature indicating that Q is then only limited by Q_L and not by RF absorption in the silicon.

[0061] A trapping parameter which is relevant especially with a large number of trapped ions is the length of time for which an ion can be trapped, called the trapped-ion lifetime. Assuming a mean lifetime of 1 hour, which follows an exponential decay, a trap array holding 1000 ions would lose ions at a rate of around one per second, wherein ions are re-loaded continuously so as to maintain 1000 ions in the trap.

[0062] Six traps were produced and tested. Traps #1-#5 were produced from a first wafer, and trap #6 from a second wafer. In trap #1, ion lifetimes of up to 9 hours were observed without laser cooling. With laser cooling, no ion losses were recorded over a total experimental period of more than 50 hours with a single ion. The trap is therefore suitable for scaling up to hundreds of ions without the need for continuous reloading. Five further traps #2 - #6 were tested for shorter periods and the results from these traps were consistent with the more extended observations made with trap #1.

[0063] For controlled interactions between the trapped ions, in particular for quantum interactions, and for controlled interactions with the trapped ions from the outside, e.g., by laser interaction for reading out quantum states, the ion heating rates should be as low as possible to avoid decoherence of the quantum states which would hinder quantum information processing. For many quantum-information applications ions should advantageously be at or near their motional ground state, and exciting the higher motional quantum states of the ions by heating degrades the quality of quantum operations. Trapped ions are predominately heated by electric-field noise resonant with the ions' motional frequencies.

[0064] To measure the heating rate, the axial motion of a single ion was cooled to near the ground state by resolved-sideband cooling. Following a predefined waiting time, the mean phonon number was determined by two different methods: measurement of the transition probability on the red and blue sidebands and Rabi flops on the blue sideband. The heating rate was determined by the change in phonon number with different waiting times. Fig. 27 shows a plot measured on trap #1 showing the mean phonon number of the axial mode (ω_z//2π = 1.069 MHz) as a function of the waiting time after ground state cooling (error bars: 1σ). The mean phonon number was determined by measuring the Rabi flops on the blue sideband. In this instance the heating rate, taken to be the gradient of a linear fit to the data, is 0.37(6) phonons/s. Taking data on different days over a period of six weeks the trap exhibited a heating rate of 0.6(2) phonons/s. The electric-field noise inferred to underlie this heating is S_E = 4.4 - 10^-15 V²m^-2Hz^-1, represented by the black square labeled with the trap name YK802 in Fig. 29.

[0065] Heating rates were measured in the five further traps #2-#6 with the results shown in table form in Fig. 28. Trap #4 exhibits a heating rate of 0.33(4) phonons/s, which is, to the best of knowledge, the lowest rate ever reported. The electric-field noise S_E determined for several other traps (black dots and black crosses symbolizing these traps), and for the trap YK802 are plotted in Fig. 29 against trap size.

[0066] The trap design based on a semiconductor substrate, e.g., a silicon substrate, allows trap fabrication to benefit from well-developed semiconductor fabrication processes and exploits low temperature properties of the semiconductors such as silicon, in particular low RF losses of silicon and other semiconductors at low temperatures. The traps exhibit a high quality factor Q and reproducible low heating rates of the ions or other charged or polar particles.

[0067] While voltage application to the planar electrodes of the trap can be achieved by wirebonds as described above, embodiments are not so limited. The method of manufacturing a cryogenic semiconductor-based surface-electrode trap, i.e., a surface-electrode trap based on a semiconductor substrate such as a silicon substrate, can include one or more of the following. Slots may be formed in the substrate for increased optical access. Through-wafer vias may be formed for electric contact of the electrodes from the side of the back surface of the semiconductor substrate.

[0068] Figs. 30-35 illustrate the formation of vias or slots in a silicon substrate. Forming the vias or slots may include laser cutting the silicon substrate 701 from the backside to form a recess 780 in the back surface 702 of the silicon substrate. Of course, several such recesses may be formed at positions that shall become vias or slots. The laser cutting process is indicated by an arrow in Fig. 30. The formation may further include coating the front surface 704 of the substrate, or parts thereof, with a photoresist 765 as shown in Fig. 31. The formation may include exposing the parts of the photoresist 765 that lie vertically above the formed recess(es) with UV light through a photo mask 775 as shown in Fig. 32. The formation may include developing the photoresist and forming a patterned photoresist layer as shown in Fig. 33. The formation may further include deep reactive ion etching from the front surface of the substrate down to the recess(es) to form slot(s) or via(s) 790 as shown in Fig. 34. The recesses are not undercut.

[0069] Further, depositing the conductive layer 705, e.g., of a metal layer such as a gold layer, may include tilted deposition of the conductive layer 705 from the front side and/or from the back side as shown in Fig. 35. A thermal oxide layer may have been formed previously on the front surface, the back surface and the walls of the via(s). The conductive layer 705 will cover the front and back surfaces of the silicon substrate and the side walls of the vias so that electrical contact can be made from the backside of the substrate. Terminals of the electrodes may be formed on the back surface of the substrate by another trench structure of undercut trenches, manufactured similarly as the trench structure on the front surface. Due to the undercuts the electrodes on the front side and the terminals on the back side remain electrically insulated from each other even if tilted deposition of the conductive layer is carried out. With the aid of vias, very elaborate trap designs may be realized.

[0070] Unlike the case of room-temperature silicon traps, vias of embodiments of the invention work at RF frequencies, allowing the realization of a 2D trap array with adjustable RF electrodes. For instance, trap designs as described in US 8,426,809 can be realized. The heating-rate and lifetime measurements described above indicate that a trap array with several hundred sites is practicable. Such trap arrays can be integrated with a wide variety of other silicon-based technologies including CMOS electronics, micro-optics, micro- and nano-mechanical systems, and sensors, according to further embodiments of the present invention. This means that the entire technology for quantum information processing or other purposes can be integrated on a single substrate providing a quantum lab on a chip.

[0071] According to further embodiments, a cryogenic silicon-based surface-electrode trap and a system for trapping charged or polar particles are provided, wherein the trap includes planar electrodes that form a two-dimensional array of trapping sites.

[0072] Further embodiments relate to the use of a surface-electrode trap for trapping charged or polar particles at a temperature of 150 K or less. The surface-electrode trap includes a silicon substrate and planar electrodes on a front surface of the silicon substrate. The surface-electrode trap may be a surface-electrode trap of the embodiments of the invention, exhibiting some or all of the features described herein.

[0073] While the foregoing is directed to some embodiments of the invention, other and further embodiments may be devised without departing from the scope determined by the claims that follow.

Claims

1. A system for trapping charged or polar particles, the system comprising:

a cryostat; and

a surface-electrode trap for trapping charged or polar particles, the trap comprising:

a silicon substrate having a front surface and a back surface;

planar electrodes formed on the front surface of the silicon substrate and configured to generate a trapping potential for trapping the charged or polar particles above the planar electrodes, the planar electrodes including:

- a first radio frequency electrode extending substantially parallel to the front surface of the substrate, and

- a first direct current electrode extending substantially parallel to the front surface of the substrate and being adjacent to, and electrically insulated from, the first radio frequency electrode;

wherein the surface-electrode trap is positioned in the cryostat, and the cryostat is configured for cooling the surface-electrode trap to or below a temperature of 150 K.

2. The system of claim 1, wherein the planar electrodes are formed directly on the front surface of the silicon substrate, or wherein the planar electrodes are formed directly on a semiconductor oxide layer which is itself directly formed on the silicon substrate.

3. The system of any of the preceding claims, wherein the silicon substrate has a trench formed therein that separates the first radio frequency electrode from the first direct current electrode by a gap to provide the electrical insulation.

4. The system of claim 3, wherein the trench is an undercut trench.

5. The system of any of the preceding claims, wherein the first radio frequency electrode and the first direct current electrode are metal electrodes.

6. The system of any of the preceding claims, comprising:

a vacuum chamber for providing a vacuum environment to the surface-electrode trap; and

a cryogenic pump for establishing the vacuum environment by cryogenic pumping.

7. The system of any of the preceding claims, comprising:

one or more lasers for at least one of: (i) ionization of atoms, (ii) addressing ions for quantum manipulation, (iii) cooling the ions and (iv) imaging the ions.

8. A cryogenic surface-electrode trap for trapping charged or polar particles at or below a temperature of 150 K, comprising:

a silicon substrate having a front surface and a back surface;

at least one planar radio frequency electrode and at least one planar direct current electrode,

wherein these electrodes are formed on the front surface of the silicon substrate and are configured to generate a trapping potential for trapping the charged or polar particles above the electrodes, the planar radio frequency and planar direct current electrodes including:

- a first radio frequency electrode extending substantially parallel to the front surface of the substrate, and

- a first direct current electrode extending substantially parallel to the front surface of the substrate and being adjacent to the first radio frequency electrode,

wherein the silicon substrate has a trench formed therein that separates the first radio frequency electrode from the first direct current electrode to provide electrical insulation of these electrodes, and

wherein the planar electrodes are formed directly on the front surface of the silicon substrate, or wherein the planar electrodes are formed directly on a semiconductor oxide layer which is itself directly formed on the silicon substrate.

9. Use of a surface-electrode trap for trapping charged or polar particles at a temperature of 150 K or less, the surface-electrode trap comprising:

a silicon substrate having a front surface and a back surface;

a first radio frequency electrode extending substantially parallel to the front surface of the substrate; and

a first direct current electrode extending substantially parallel to the front surface of the substrate and being adjacent to, and electrically insulated from, the first radio frequency electrode.

10. A method of manufacturing a cryogenic surface-electrode trap configured for trapping charged or polar particles at temperatures of 150 K or less, the method comprising:

- providing a silicon substrate having a front surface and a back surface;

- forming undercut trenches in the front surface of the silicon substrate; and

- subsequently depositing a conductive layer on the front surface of the silicon substrate,

wherein the trenches electrically insulate regions of deposited conductive material from each other that constitute surface electrodes of the surface-electrode trap.

11. The method of claim 10, wherein the conductive layer includes at least one metal layer.

12. The method of one of claims 10-11, wherein depositing the conductive layer comprises directly depositing the conductive layer on the front surface of the silicon substrate.

13. The method of one of claims 10-11, comprising thermal oxidation of at least the front surface of the silicon substrate to form a thermal silicon oxide layer, and depositing the conductive layer comprises directly depositing the conductive layer on the thermal silicon oxide layer.

14. The method of one of claim 10-13, wherein the conductive layer includes a first sub-layer and a second sub-layer, the first sub-layer being thinner than the second sub-layer and acting as a bonding layer between the second sub-layer and the silicon substrate or the thermal silicon oxide layer.

15. The method of one of claims 10-13, wherein forming the undercut trenches comprises:

- forming a patterned photoresist on the front surface of the silicon substrate,

- performing deep reactive ion etching to form the undercut trenches, and

- removing the photoresist, wherein removing the photoresist optionally includes exposing the photoresist to an oxygen plasma.

Drawing