(19)
(11) EP 2 924 729 A8

(12) CORRECTED EUROPEAN PATENT APPLICATION
Note: Bibliography reflects the latest situation

(15) Correction information:
Corrected version no 1 (W1 A2)

(48) Corrigendum issued on:
24.02.2016 Bulletin 2016/08

(43) Date of publication:
30.09.2015 Bulletin 2015/40

(21) Application number: 15155426.8

(22) Date of filing: 17.02.2015
(51) International Patent Classification (IPC): 
H01L 23/538(2006.01)
 H01L 25/065(2006.01)
(84) Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated Extension States:
BA ME

(30) Priority: 28.03.2014 US 201414228887

(71) Applicant: Intel Corporation
Santa Clara, CA 95054 (US)

(72) Inventors:
  • Chase, Harold Ryan
    Mesa, AZ 85203 (US)
  • Manusharow, Mathew J.
    Phoenix, AZ 85048 (US)
  • Roy, Mihir K.
    Chandler, AZ 85224 (US)

(74) Representative: Rummler, Felix 
RGC Jenkins & Co. 26 Caxton Street
London SW1H 0RJ
London SW1H 0RJ (GB)

   


(54) Electronic package and method of connecting a first die to a second die to form an electronic package


(57) Some embodiments relate to an electronic package. The electronic package includes a substraten (11) that includes a plurality of buildup layers (12A,12B,12C). A first die (13) is embedded in one of the buildup layers on one side of the substrate. A second die(16) is bonded to the substrate within a cavity (17) on an opposing side of the substrate. The first die and the second die may be electrically connected to conductors within the plurality of buildup layers. Other embodiments relate to method of connecting a first die to a second die to form an electronic package. The method includes attaching a first die to a core and fabricating a substrate onto the core. The method further includes creating a cavity in another of the buildup layers on an opposing side of the substrate and attaching a second die to the substrate within the cavity.