(19)
(11) EP 2 927 777 B8

(12) CORRECTED EUROPEAN PATENT SPECIFICATION
Note: Bibliography reflects the latest situation

(15) Correction information:
Corrected version no 1 (W1 B1)

(48) Corrigendum issued on:
25.09.2019 Bulletin 2019/39

(45) Mention of the grant of the patent:
14.08.2019 Bulletin 2019/33

(21) Application number: 15154436.8

(22) Date of filing: 10.02.2015
(51) International Patent Classification (IPC): 
G11C 7/10(2006.01)
G11C 7/22(2006.01)
 G06F 1/10(2006.01)

(54)

Clock tree circuit

Taktverteilungsnetzwerk

Circuit d'arborescence d'horloge

(84) Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30) Priority: 02.04.2014 US 201461973988 P
22.01.2015 US 201514602562

(43) Date of publication of application:
07.10.2015 Bulletin 2015/41

(73) Proprietor: MediaTek Inc.
Hsinchu City 30078 (TW)

(72) Inventors:
  • CHIANG, Chen-Feng
    616 Chiayi County (TW)
  • CHEN, Kai-Hsin
    500 Changhua County (TW)
  • LIOU, Ming-shi
    104 Taipei City (TW)
  • YAO, Chih-Tsung
    302 Hsinchu County (TW)

(74) Representative: Goddar, Heinz J. 
Boehmert & Boehmert Anwaltspartnerschaft mbB Pettenkoferstrasse 22
80336 München
80336 München (DE)


(56) References cited: : 
EP-A1- 0 897 145
US-A1- 2005 057 286
US-A1- 2008 115 004
US-A1- 2010 188 130
US-A1- 2013 049 827
US-B1- 6 262 614
 EP-A2- 0 646 854
US-A1- 2008 031 057
US-A1- 2008 137 471
US-A1- 2012 155 206
US-A1- 2013 314 138
US-B1- 7 176 714
   
  • NITIN NIGAM ET AL: "A COMPARATIVE STUDY OF CLOCK DISTRIBUTION APPROACHES FOR WSI", PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON WAFER SCALE INTEGRATION SAN FRANCISCO, JAN. 20 - 22, 1993; [PROCEEDINGS OF THE ANNUAL INTERNATIONAL CONFERENCE ON WAFER SCALE INTEGRATION (FROM 1996 PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON INNOVAT, vol. CONF. 5, 20 January 1993 (1993-01-20) , pages 243-251, XP000384857,
  • BOYAN SEMERDJIEV ET AL: "Optimal Crosstalk Shielding Insertion along On-Chip Interconnect Trees", 2014 27TH INTERNATIONAL CONFERENCE ON VLSI DESIGN AND 2014 13TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, 6 January 2007 (2007-01-06), pages 289-294, XP055382036, ISSN: 1063-9667, DOI: 10.1109/VLSID.2007.122
  • Gagan Kansal ET AL: "Decreasing parasitic capacitance in IC layouts", , 4 January 2014 (2014-01-04), XP055423096, Retrieved from the Internet: URL:https://www.edn.com/design/analog/4426 479/Decreasing-parasitic-capacitance-in-IC -layouts [retrieved on 2017-11-09]
  • Khosrow Golshan: "Physical Design Essentials : An ASIC Design Implementation" In: "Springer", 14 March 2007 (2007-03-14), XP055426369, page 167,
  • J Bhasker ET AL: "Static Timing Analysis for Nanometer Designs : A Practical Approach" In: "Static Timing Analysis for Nanometer Designs : A Practical Approach", 17 April 2009 (2009-04-17), Springer, XP055423193, page 174,
  • Whitson G. Waldo: "Program Management for System on Chip Platforms: New Product Introduction of Hardware and Software" In: "Program Management for System on Chip Platforms: New Product Introduction of Hardware and Software", 1 September 2010 (2010-09-01), Inkwater Press, XP055423210, page 115,
   
Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).