[Technical Field]
[0001] This invention is a control apparatus for an AC rotary machine and a control apparatus
for an electric power steering, with which an output of the AC rotary machine can
be improved without the need to modify a control period.
[Background Art]
[0002] In a phase current detection device of a conventional three-phase PWM inverter apparatus,
a control period Tsw is varied in length in accordance with a phase command value
θ* and a voltage command value V*. In an example disclosed in the prior art (see PTL
1, for example), when a holding time (t1 or t2) of a switching mode corresponding
to a basic voltage vector other than a zero vector, the basic voltage vector being
determined in accordance with the phase command value θ* and the voltage command value
V*, is longer than a sum (tdd + tsw) of a dead time tdd of an inverter main circuit
and a time tsw required for current detection by a hole CT9, a fixed short control
period Tsw is selected. When the holding time of the switching mode is shorter than
the time (tdd + tsw), on the other hand, the control period Tsw is lengthened so that
the holding time is longer than the time (tdd + tsw).
[Citation List]
[Patent Literature]
[0003] [PTL 1]
Japanese Patent Application Publication No.
H3-230767
[Summary of Invention]
[Technical Problem]
[0004] However, the prior art contains the following problem. When the control period Tsw
is lengthened, a PWM period (which is equal to the control period Tsw) output by the
three-phase PWM inverter apparatus increases in length, leading to a reduction in
a PWM frequency, which is given by the inverse of the PWM period. When an AC rotary
machine is connected to the output of the three-phase PWM inverter, a component having
the PWM frequency is included in a current flowing through the AC rotary machine.
Therefore, when the PWM frequency decreases, the frequency of the component included
in the current also decreases, with the result that noise is generated by the AC rotary
machine.
[0005] In an AC rotary machine used in an electric power steering in particular, quietness
is required, and therefore the PWM frequency is set to be no lower than 20 kHz (a
frequency band exceeding an audible range), for example. Here, when a method of lengthening
the control period Tsw (lowering the PWM frequency), such as that of PTL 1, is applied
to an AC rotary machine used in an electric power steering, the PWM frequency falls
below 20 kHz. As a result, noise is generated by the AC rotary machine, causing a
person traveling in a vehicle installed with the electric power steering to experience
discomfort.
[0006] This invention has been designed to solve the problem described above, and an object
thereof is to provide a control apparatus for an AC rotary machine and a control apparatus
for an electric power steering, with which an output of the AC rotary machine can
be improved without the need to modify a control period.
[Solution to Problem]
[0007] A control apparatus for an AC rotary machine according to this invention includes:
an AC rotary machine that includes a first winding and a second winding which have
a phase difference; a first current detection unit that detects a current of the first
winding; a second current detection unit that detects a current of the second winding;
a control unit that calculates a first voltage command and a second voltage command
on the basis of a detected current value of the AC rotary machine; a first voltage
application unit that applies a voltage to the first winding on the basis of the first
voltage command; a second voltage application unit that applies a voltage to the second
winding on the basis of the second voltage command; and a first detectability determination
unit that determines a detectability of the current of the first winding, detected
by the first current detection unit, on the basis of at least one of the first voltage
command and the second voltage command,
wherein the control unit calculates the first voltage command on the basis of the
current of the first winding, detected by the first current detection unit, when the
first detectability determination unit determines that the current of the first winding
is detectable, and calculates the first voltage command and the second voltage command
on the basis of the current of the second winding, detected by the second current
detection unit, when the first detectability determination unit determines that the
current of the first winding is undetectable.
[0008] Further, a control apparatus for an electric power steering according to this invention
includes the control apparatus for an AC rotary machine according to this invention,
wherein the control unit calculates the first voltage command and the second voltage
command such that the AC rotary machine generates torque for assisting steering torque
of a steering system.
[Advantageous Effects of Invention]
[0009] According to this invention, when the first detectability determination unit determines
that the current of the first winding is detectable, the first voltage command is
calculated on the basis of the current of the first winding, detected by the first
current detection unit, and when the first detectability determination unit determines
that the current of the first winding is undetectable, the first voltage command and
the second voltage command are calculated on the basis of the current of the second
winding, detected by the second current detection unit. As a result, a striking effect
not evident in the prior art, according to which the output of the AC rotary machine
can be increased while reducing noise generated by the AC rotary machine, is obtained.
[Brief Description of Drawings]
[0010]
[Fig. 1]
Fig. 1 is a view showing an overall configuration of a control apparatus for an AC
rotary machine according to a first embodiment of this invention.
[Fig. 2]
Fig. 2 is a view illustrating a configuration of a three-phase AC rotary machine used
as an example of the AC rotary machine according to the first embodiment of this invention.
[Fig. 3]
Fig. 3 is a view showing relationships between a first voltage vector corresponding
to ON/OFF conditions of respective semiconductor switches and a current flowing through
a DC bus line of a first voltage application unit, according to the first embodiment
of this invention.
[Fig. 4]
Fig. 4 is a view showing a relationship between a second voltage vector corresponding
to the ON/OFF conditions of the respective semiconductor switches and a current flowing
through a DC bus line of a second voltage application unit, according to the first
embodiment of this invention.
[Fig. 5]
Fig. 5 is an illustrative view showing a first voltage command vector based on first
voltage commands and a second voltage command vector based on second voltage commands,
according to the first embodiment of this invention.
[Fig. 6]
Fig. 6 is a waveform diagram showing the first voltage commands and the second voltage
commands according to the first embodiment of this invention.
[Fig. 7]
Fig. 7 is a view illustrating relationships between the voltage commands and ON ratios
of upper side arm elements of respective phases with respect to the first voltage
application unit, according to the first embodiment of this invention.
[Fig. 8]
Fig. 8 is a view illustrating relationships between the voltage commands and the ON
ratios of the upper side arm elements of the respective phases with respect to the
second voltage application unit, according to the first embodiment of this invention.
[Fig. 9]
Fig. 9 is a view illustrating operations relating to ON/OFF patterns of the semiconductor
switches and a period of a switching signal in current detection units, according
to the first embodiment of this invention.
[Fig. 10]
Fig. 10 is a view illustrating different operations to those of Fig. 9 relating to
the ON/OFF patterns of the semiconductor switches and the period of the switching
signal in the current detection units, according to the first embodiment of this invention.
[Fig. 11]
Fig. 11 is a view illustrating different operations to those of Figs. 9 and 10 relating
to the ON/OFF patterns of the semiconductor switches and the period of the switching
signal in the current detection units, according to the first embodiment of this invention.
[Fig. 12]
Fig. 12 is an illustrative view relating to a function of a first detectability determination
unit according to the first embodiment of this invention.
[Fig. 13]
Fig. 13 is a flowchart showing a series of operations performed by the first detectability
determination unit according to the first embodiment of this invention.
[Fig. 14]
Fig. 14 is a flowchart showing a series of operations performed by a first detectability
determination unit according to a second embodiment of this invention.
[Fig. 15]
Fig. 15 is a view showing waveforms described in the steps of Fig. 14 in a case where
a third predetermined value is set at 0.1 Vdc, according to the second embodiment
of this invention.
[Fig. 16]
Fig. 16 is a view showing an overall configuration of a control apparatus for an AC
rotary machine according to a fourth embodiment of this invention.
[Fig. 17]
Fig. 17 is a view showing an overall configuration of a control apparatus for an AC
rotary machine according to a fifth embodiment of this invention.
[Fig. 18]
Fig. 18 is a view showing a relationship between the first voltage vector corresponding
to the ON/OFF conditions of the respective semiconductor switches and the currents
of the first windings, according to the fifth embodiment of this invention.
[Fig. 19]
Fig. 19 is a view showing a relationship between the second voltage vector corresponding
to the ON/OFF conditions of the respective semiconductor switches and the currents
of the second windings, according to the fifth embodiment of this invention.
[Fig. 20]
Fig. 20 is a view illustrating an operation relating to the ON/OFF patterns of the
semiconductor switches and the period of the switching signal in the current detection
units, according to the fifth embodiment of this invention.
[Fig. 21]
Fig. 21 is an illustrative view relating to a function of a first detectability determination
unit according to the fifth embodiment of this invention.
[Fig. 22]
Fig. 22 is a flowchart showing a series of operations performed by the first detectability
determination unit according to the fifth embodiment of this invention.
[Fig. 23]
Fig. 23 is a view showing an overall configuration of a control apparatus for an AC
rotary machine according to a sixth embodiment of this invention.
[Fig. 24]
Fig. 24 is a view showing an overall configuration of a control apparatus for an AC
rotary machine according to a seventh embodiment of this invention.
[Fig. 25]
Fig. 25 is a view showing an overall configuration of a control apparatus for an AC
rotary machine according to an eighth embodiment of this invention.
[Fig. 26]
Fig. 26 is a flowchart showing a series of operations performed by a second detectability
determination unit according to the eighth embodiment of this invention.
[Fig. 27]
Fig. 27 is a flowchart showing a series of operations performed by a switch according
to the eighth embodiment of this invention.
[Fig. 28]
Fig. 28 is a view showing an overall configuration of a control apparatus for an AC
rotary machine according to a ninth embodiment of this invention.
[Fig. 29]
Fig. 29 is a view showing a condition in which differential current gains are varied
on the basis of the first voltage commands, according to the ninth embodiment of this
invention.
[Fig. 30]
Fig. 30 is a view showing a condition in which sum current gains are varied on the
basis of the first voltage commands, according to the ninth embodiment of this invention.
[Fig. 31]
Fig. 31 is a view showing an overall configuration of a control apparatus for an AC
rotary machine according to a tenth embodiment of this invention.
[Description of Embodiments]
[0011] Preferred embodiments of a control apparatus for an AC rotary machine and a control
apparatus for an electric power steering according to this invention will be described
below using the drawings.
First Embodiment
[0012] Fig. 1 is a view showing an overall configuration of a control apparatus for an AC
rotary machine according to a first embodiment of this invention. Further, Fig. 2
is a view illustrating a configuration of a three-phase AC rotary machine used as
an example of the AC rotary machine according to the first embodiment of this invention.
As shown in Fig. 2, an AC rotary machine 1a shown in Fig. 1 is a three-phase AC rotary
machine in which first three-phase windings U1, V1, W1 connected at a neutral point
N1 and second three-phase windings U2, V2, W2 connected at a neutral point N2 are
housed in a stator of a rotary machine without being electrically connected to each
other.
[0013] Note that 30 degree phase differences exist respectively between the U1 winding and
the U2 winding, the V1 winding and the V2 winding, and the W1 winding and the W2 winding.
Fig. 2 shows a case in which the first three-phase windings and the second three-phase
windings forming the AC rotary machine 1a are respectively Y-connected. However, this
invention may also be applied to a case in which the windings are Δ-connected.
[0014] A DC power supply 2a outputs a DC voltage Vdc1 to a first voltage application unit
3a, and a DC power supply 2b outputs a DC voltage Vdc2 to a second voltage application
unit 3b. The DC power supplies 2a, 2b include any device that outputs a DC voltage,
such as a battery, a DC-DC converter, a diode rectifier, or a PWM rectifier. Further,
a configuration in which a DC voltage is output to the first voltage application unit
3a and the second voltage application unit 3b using either one of the DC power supplies
2a, 2b is also included in the scope of this invention.
[0015] The first voltage application unit 3a performs PWM on first voltage commands Vu1',
Vv1', Vw1' and switches semiconductor switches Sup1, Sun1, Svp1, Svn1, Swp1, Swn1
(in the following description, these six semiconductor switches will be referred to
as the semiconductor switches Sup1 to Swn1) ON and OFF using an inverter circuit (an
inverter). Thus, the first voltage application unit 3a converts the DC voltage Vdc1
input from the DC power supply 2a into an alternating current and applies an AC voltage
to the first three-phase windings U1, V1, W1 of the AC rotary machine 1a. Here, switches
formed by connecting a semiconductor switch such as an IGBT, a bipolar transistor,
or a MOS power transistor to a diode in anti-parallel are used as the semiconductor
switches Sup1 to Swn1.
[0016] The second voltage application unit 3b performs PWM on second voltage commands Vu2',
Vv2', Vw2' and switches semiconductor switches Sup2, Sun2, Svp2, Svn2, Swp2, Swn2
(in the following description, these six semiconductor switches will be referred to
as the semiconductor switches Sup2 to Swn2) ON and OFF using an inverter circuit (an
inverter). Thus, the second voltage application unit 3b converts the DC voltage Vdc2
input from the DC power supply 2b into an alternating current and applies an AC voltage
to the second three-phase windings U2, V2, W2 of the AC rotary machine 1a. Here, switches
formed by connecting a semiconductor switch such as an IGBT, a bipolar transistor,
or a MOS power transistor to a diode in anti-parallel are used as the semiconductor
switches Sup2 to Swn2.
[0017] A first current detection unit 4a detects a current Idc1 flowing through a DC bus
line of the first voltage application unit 3a using a current sensor such as a shunt
resistor or a current transformer (CT). Fig. 3 is a view showing relationships between
a first voltage vector V0 (1) to V7 (1) corresponding to the ON/OFF conditions of
the semiconductor switches Sup1 to Swn1 and the current Idc1 flowing through the DC
bus line of the first voltage application unit 3a, according to the first embodiment
of this invention. Note that with respect to Sup1 to Swn1 in Fig. 3, "1" and "0" respectively
indicate a condition in which the switch is ON and a condition in which the switch
is OFF.
[0018] The first current detection unit 4a detects currents Iu1, Iv1, Iw1 of the first windings
on the basis of the relationships shown in Fig. 3. Note that the first current detection
unit 4a may detect two of the currents Iu1, Iv1, Iw1 of the first windings from Idc1,
and determine the remaining current by calculation using the fact that the sum of
the currents of the three phases is zero.
[0019] A second current detection unit 4b detects a current Idc2 flowing through a DC bus
line of the second voltage application unit 3b using a current sensor such as a shunt
resistor or a current transformer (CT). Fig. 4 is a view showing relationships between
a second voltage vector V0 (2) to V7 (2) corresponding to the ON/OFF conditions of
the semiconductor switches Sup2 to Swn2 and the current Idc2 flowing through the DC
bus line of the second voltage application unit 3b, according to the first embodiment
of this invention. Note that with respect to Sup2 to Swn2 in Fig. 4, "1" and "0" respectively
indicate a condition in which the switch is ON and a condition in which the switch
is OFF.
[0020] The second current detection unit 4b detects currents Iu2, Iv2, Iw2 of the second
windings on the basis of the relationships shown in Fig. 4. Note that the second current
detection unit 4b may detect two of the currents Iu2, Iv2, Iw2 of the second windings
from Idc2, and determine the remaining current by calculation using the fact that
the sum of the currents of the three phases is zero.
[0021] Further, the numeral (1) in parentheses in the first voltage vector shown in Fig.
3 and the numeral (2) in parentheses in the second voltage vector shown in Fig. 4
are provided to differentiate between the first voltage vector and the second voltage
vector. Hence, (1) is appended to the first voltage vector based on the first voltage
commands, and (2) is appended to the second voltage vector based on the second voltage
commands.
[0022] A first detectability determination unit 12a determines whether or not the currents
of the first windings can be detected on the basis of the first voltage commands Vu1',
Vv1', Vw1', and outputs a first detectability determination signal flag_1.
[0023] Next, a control unit 5a will be described. A coordinate converter 6a calculates currents
Id1, Iq1 of the first windings on two rotational axes by converting the currents Iu1,
Iv1, Iw1 of the first windings, detected by the first current detection unit 4a, into
currents on rotating coordinates on the basis of a rotation position θ of the AC rotary
machine 1a.
[0024] A coordinate converter 6b calculates currents Id2, Iq2 of the second windings on
two rotational axes by converting the currents Iu2, Iv2, Iw2 of the second windings,
detected by the second current detection unit 4b, into currents on rotating coordinates
on the basis of the rotation position θ of the AC rotary machine 1a.
[0025] When the currents of the first windings are determined to be detectable on the basis
of the first detectability determination signal flag_1, a switch 7a is switched so
that the currents Id1, Iq1 of the first windings are output respectively as currents
Id', Iq' on rotating biaxial coordinates. Further, when the currents of the first
windings are determined to be undetectable on the basis of the first detectability
determination signal flag_1, the switch 7a is switched so that the currents Id, Iq
of the second windings are output respectively as currents Id', Iq' on rotating biaxial
coordinates.
[0026] A subtractor 8a calculates a deviation dId between a d axis current command Id* of
the AC rotary machine 1a and the current Id' on rotating biaxial coordinates output
by the switch 7a. Further, a subtractor 8b calculates a deviation dIq between a q
axis current command Iq* of the AC rotary machine 1a and the current Iq' on rotating
biaxial coordinates output by the switch 7a.
[0027] A controller 9a calculates a voltage command Vd on rotating biaxial coordinates using
a P controller and a PI controller so that the deviation dId is controlled to zero.
Further, a controller 9b calculates a voltage command Vq on rotating biaxial coordinates
using a P controller and a PI controller so that the deviation dIq is controlled to
zero.
[0028] A coordinate converter 10a calculates first voltage commands Vu1, Vv1, Vw1 by performing
coordinate conversion to convert the voltage commands Vd, Vq on rotating biaxial coordinates
into three-phase AC coordinates on the basis of the rotation position θ of the AC
rotary machine 1a.
[0029] Further, a coordinate converter 10b calculates second voltage commands Vu2, Vv2,
Vw2 by performing coordinate conversion to convert the voltage commands Vd, Vq on
rotating biaxial coordinates into three-phase AC coordinates on the basis of a position
θ - 30, which is obtained by subtracting 30 degrees from the rotation position θ of
the AC rotary machine 1a.
[0032] The first detectability determination unit 12a outputs the first detectability determination
signal flag_1 on the basis of the first voltage commands Vu1', Vv1', Vw1'.
[0033] Next, the first and second voltage commands and operations performed by the first
detectability determination unit 12a will be described in detail. Fig. 5 is an illustrative
view showing a first voltage command vector V1* based on the first voltage commands
Vu1', Vv1', Vw1' and a second voltage command vector V2* based on the second voltage
commands Vu2', Vv2', Vw2', according to the first embodiment of this invention. As
shown in Fig. 5, the first voltage command vector V1* and the second voltage command
vector V2* are vectors that rotate about aU(1)-V(1)-W(1) axis and a U (2) - V (2)
- W (2) axis, respectively.
[0034] Note that numerals shown in parentheses in Fig. 5 denote either axes corresponding
to the first windings or axes corresponding to the second windings. More specifically,
U (1), V (1), W (1), to which (1) is appended, respectively denote axes corresponding
to the U phase, the V phase, and the W phase of the first windings, while U (2), V
(2), W (2), to which (2) is appended, respectively denote axes corresponding to the
U phase, the V phase, and the W phase of the second windings. Here, phase angles of
the first voltage command vector V1* and the second voltage command vector V2* when
the U (1) axis is used as a reference are both θv. In other words, there is no phase
difference therebetween.
[0035] Fig. 6 is a waveform diagram showing the first voltage commands Vu1, Vv1, Vw1 and
the second voltage commands Vu2, Vv2, Vw2 according to the first embodiment of this
invention. The U (2), V (2), and W (2) axes shown in Fig. 5 are respectively retarded
by a phase of 30 degrees relative to the U (1), V (1), and W (1) axes. Therefore,
as shown in Fig. 6, the second voltage commands Vu2, Vv2, Vw2 are respectively retarded
by a phase of 30 degrees relative to the first voltage commands Vu1, Vv1, Vw1.
[0036] In Fig. 6, the abscissa shows the voltage phase angle θv when the U (1) axis is used
as a reference. Hence, with respect to the AC rotary machine 1a, in which a 30 degree
phase difference exists between the first windings and the second windings, a 30 degree
phase difference exists between the first voltage commands and the second voltage
commands. Similarly, with respect to an AC rotary machine in which a phase difference
of 30 + 60 × N (where N is an integer) exists between the first windings and the second
windings, a 30 + 60 × N degree phase difference exists between the first voltage commands
and the second voltage commands.
[0037] Fig. 7 is a view illustrating relationships between the voltage commands and ON ratios
of upper side arm elements of the respective phases with respect to the first voltage
application unit 3a, according to the first embodiment of this invention. Fig. 7(a)
shows the first voltage commands Vu1, Vv1, Vw1 shown in Fig. 6, which serve as the
output of the coordinate converter 10a. Fig. 7(b) shows the first voltage commands
Vu1', Vv1', Vw1' serving as the output of the offset calculator 11a, which are calculated
using Equations (1) to (3).
[0038] The offset voltage Voffset1 of Equations (1) to (3) is given by Equation (7), shown
below, using a maximum value Vmax1 and a minimum value Vmin1 of the first voltage
commands Vu1, Vv1, Vw1.

[0039] Note, however, that a voltage output range of a phase voltage that can be output
by the first voltage application unit 3a extends from zero to the bus line voltage
Vdc1. Therefore, when the first voltage commands Vu1', Vv1', Vw1' are smaller than
-0.5 Vdc1 or exceed 0.5 Vdc1, the first voltage commands Vu1', Vv1', Vw1' are limited
to -0.5 Vdc1 or 0.5 Vdc1 so as to remain within the voltage Vdc1 that can be output
by the first voltage application unit 3a.
[0040] Further, Voffset1 may be determined using another known offset voltage calculation
method such as a two phase modulation method or a third harmonic wave superimposing
method instead of Equation (7).
[0041] Fig. 7(c) shows ON duties Dsup1, Dsvp1, Dswp1 denoting ON ratios of the upper side
arm elements (Sup1, Svp1, Swp1) of the respective phases of the first voltage application
unit 3a. These ON duties Dsup1, Dsvp1, Dswp1 are determined from

using Vu1', Vv1', Vw1', respectively. Here, x = U, V, W. When Dsup1 is 0.6, for example,
the first voltage application unit 3a sets the ON ratio of Sup1 within a switching
period Tsw at 0.6.
[0042] In the first voltage application unit 3a, either the upper side arm elements (Sup1,
Svp1, Swp1) or lower side arm elements (Sun1, Svn1, Swn1) are switched ON at all times
in each phase. Accordingly, relationships shown below in Equations (8) to (10) are
established between the ON duties (Dsup1, Dsvp1, Dswp1) of the upper side arm elements
of the respective phases and ON duties (Dsun1, Dsvn1, Dswn1) of the lower side arm
elements.

[0043] Therefore, in accordance with Equation (8), when Dsup1 is 0.6, for example, Dsun1
is 0.4. Thus, the ON duties of the respective switching elements in the first voltage
application unit 3a are determined on the basis of the first voltage commands Vu1',
Vv1', Vw1'.
[0044] Fig. 8 is a view illustrating relationships between the voltage commands and the
ON ratios of the upper side arm elements of the respective phases with respect to
the second voltage application unit 3b, according to the first embodiment of this
invention. Fig. 8(a) shows the second voltage commands Vu2, Vv2, Vw2 shown in Fig.
6, which serve as the output of the coordinate converter 10b. Fig. 8(b) shows the
second voltage commands Vu2', Vv2', Vw2' serving as the output of the offset calculator
11b, which are calculated using Equations (4) to (6).
[0045] The offset voltage Voffset2 of Equations (4) to (6) is given by Equation (11), shown
below, using a maximum value Vmax2 and a minimum value Vmin2 of the second voltage
commands Vu2, Vv2, Vw2.

[0046] Note, however, that the voltage output range of the phase voltage that can be output
by the second voltage application unit 3b extends from zero to the bus line voltage
Vdc2. Therefore, when the second voltage commands Vu2', Vv2', Vw2' are smaller than
-0.5 Vdc2 or exceed 0.5 Vdc2, the second voltage commands Vu2', Vv2', Vw2' are limited
to -0.5 Vdc2 or 0.5 Vdc2 so as to remain within the voltage Vdc2 that can be output
by the second voltage application unit 3b.
[0047] Further, Voffset2 may be determined using another known offset voltage calculation
method such as a two phase modulation method or a third harmonic wave superimposing
method instead of Equation (11).
[0048] Fig. 8(c) shows ON duties Dsup2, Dsvp2, Dswp2 denoting ON ratios of the upper side
arm elements (Sup2, Svp2, Swp2) of the respective phases of the second voltage application
unit 3b. These ON duties Dsup2, Dsvp2, Dswp2 are determined from

using Vu2', Vv2', Vw2', respectively. Here, x = U, V, W. When Dsup2 is 0.6, for example,
the second voltage application unit 3b sets the ON ratio of Sup2 within the switching
period Tsw at 0.6.
[0049] In the second voltage application unit 3b, either the upper side arm elements (Sup2,
Svp2, Swp2) or lower side arm elements (Sun2, Svn2, Swn2) are switched ON at all times
in each phase. Accordingly, relationships shown below in Equations (12) to (14) are
established between the ON duties (Dsup2, Dsvp2, Dswp2) of the upper side arm elements
of the respective phases and ON duties (Dsun2, Dsvn2, Dswn2) of the lower side arm
elements.

[0050] Therefore, in accordance with Equation (12), when Dsup2 is 0.6, for example, Dsun2
is 0.4. Thus, the ON duties of the respective switching elements in the second voltage
application unit 3b are determined on the basis of the second voltage commands Vu2',
Vv2', Vw2'.
[0051] Fig. 9 is a view illustrating operations relating to ON/OFF patterns of the semiconductor
switches and a period of a switching signal in the current detection units, according
to the first embodiment of this invention. More specifically, Fig. 9 is a view showing
a relationship between ON/OFF patterns of the semiconductor switches Sup1, Svp1, Swp1
of the first voltage application unit 3a and the semiconductor switches Sup2, Svp2,
Swp2 of the second voltage application unit 3b and the period Tsw of the switching
signal in the first current detection unit 4a and the second current detection unit
4b.
[0052] Note that Sun1, Svn1, Swn1, Sun2, Svn2, Swn2 have inverse relationships to Sup1,
Svp1, Swp1, Sup2, Svp2, Swp2, respectively (i.e. 0 in place of 1 and 1 in place of
0, excluding a dead time period), and are not therefore described.
[0055] At a time t1 (n), Sup1 and Sup2 are set at 1 and Svp1, Swp1, Svp2, and Swp2 are set
at 0, whereupon this condition is maintained until a time t2 (n) arrives following
the elapse of Δt1. In accordance with Figs. 3 and 4, the first voltage vector and
the second voltage vector are at V1 (1) and V1 (2), respectively, between the times
t1 (n) and t2 (n). Idc1 is detected at a time ts1-1 (n) between the times t1 (n) and
t2 (n).
[0056] The time shift Δt1 is set to be longer than a sum of a dead time of the first voltage
application unit 3a and the second voltage application unit 3b and a time required
for the first current detection unit 4a to detect Idc1 or for the second current detection
unit 4b to detect Idc2 (for example, a time required for ringing included in a detected
waveform to converge and a sample holding time). For example, Δt1 = 5 µs.
[0057] In accordance with Fig. 3, the first voltage vector is at V1 (1) between the times
t1 (n) and t2 (n), and therefore Idc1 is equal to Iu1 when detected at the time ts1-1
(n). Further, in accordance with Fig. 4, the second voltage vector is at V1 (2) between
the times t1 (n) and t2 (n), and therefore Idc2 is equal to Iu2 when detected at the
time ts1-1 (n).
[0058] Next, at the time t2 (n), Svp1 and Svp2 are set at 1, and this switching pattern
is maintained until a time t3 (n). In accordance with Figs. 3 and 4, the first voltage
vector and the second voltage vector are at V2 (1) and V2 (2), respectively, between
the times t2 (n) and t3 (n).
[0059] At a time ts1-2 (n), Idc1 and Idc2 are detected again. A time shift Δt2, similarly
to the time shift Δt1, is set to be longer than the sum of the dead time of the first
voltage application unit 3a and the second voltage application unit 3b and the time
required for the first current detection unit 4a to detect Idc1 or for the second
current detection unit 4b to detect Idc2. Typically, Δt1 = Δt2.
[0060] In accordance with Fig. 3, the first voltage vector is at V2 (1) between the times
t2 (n) and t3 (n), and therefore Idc1 is equal to -Iw1 when detected at the time ts1-2
(n). Further, in accordance with Fig. 4, the second voltage vector is at V2 (2) between
the times t2 (n) and t3 (n), and therefore Idc2 is equal to -Iw2 when detected at
the time ts1-2 (n).
[0061] The currents Iu1, Iw1 of the first windings and the currents Iu2, Iw2 of the second
windings can be detected in the manner described above, and therefore the currents
Iu1, Iv1 (= -Iu1 - Iw1), Iw1 of the first windings and the currents Iu2, Iv2 (= -Iu2
- Iw2), Iw2 of the second windings can be detected using the fact that the sum of
the currents of the three phases is zero.
[0062] At a time t3 (n), Swp1 and Swp2 are set at 1. A pulse width (a time during which
"1" is maintained) between Sup1 and Swp2 is determined from a product of the ON duties
Dsup1 to Dswp2 corresponding to the respective switches and the switching period Tsw.
[0063] In the first embodiment, as described above, the switch of the upper side arm element
of the phase corresponding to the first maximum phase voltage Emax1, the switch of
the upper side arm element of the phase corresponding to the first intermediate phase
voltage Emid1, and the switch of the upper side arm element of the phase corresponding
to the first minimum phase voltage Emin1 are switched ON in that order at the time
shifts Δt1 and Δt2. By performing switching in this manner, the two types of first
voltage vectors shown in Fig. 3, with which two of the currents Iu1, Iv1, Iw1 of the
first windings can be detected from Idc1, are formed and the two types of second voltage
vectors shown in Fig. 4, with which two of the currents Iu2, Iv2, Iw2 of the second
windings can be detected from Idc2, are formed.
[0064] Depending on the voltage command value of the phase corresponding to the first intermediate
phase voltage Emid1, however, it may be impossible to form the two types of first
voltage vectors with which two of the currents Iu1, Iv1, Iw1 of the first windings
can be detected from Idc1, and as a result, it may be impossible to detect the currents
Iu1, Iv1, Iw1 of the first windings.
[0065] Fig. 10 is a view illustrating different operations to those of Fig. 9 relating to
the ON/OFF patterns of the semiconductor switches and the period of the switching
signal in the current detection units, according to the first embodiment of this invention,
Fig. 10 showing an example of a case in which the currents Iu1, Iv1, Iw1 of the first
windings cannot be detected. Fig. 10 shows a condition in which Vv1' is small such
that Dsvp1 × Tsw is smaller than Δt2. When Svp1 is switched ON at the time t2 (n)
in this condition, Svp1 is switched OFF before the time t3 (n) arrives, and therefore
the first voltage vector V2 (1) cannot be formed within the time shift Δt2.
[0066] Further, Fig. 11 is a view illustrating different operations to those of Figs. 9
and 10 relating to the ON/OFF patterns of the semiconductor switches and the period
of the switching signal in the current detection units, according to the first embodiment
of this invention, Fig. 11 showing an example of a similar case to that of Fig. 10,
in which the currents Iu1, Iv1, Iw1 of the first windings cannot be detected. Fig.
11 shows a condition in which Vv1' is large such that Dsvp1 × Tsw is larger than Tsw
- Δt1. In this condition, even when Svp1 is switched OFF at a time t4 (n) at which
the switching period Tsw ends, a pulse width corresponding to Dsvp1 × Tsw cannot be
obtained unless Svp1 is switched ON before the time t2 (n) arrives. As a result, V1
(1) cannot be formed within the time zone Δt1.
[0067] Likewise with regard to the second voltage application unit 3b, when Vv2' is small
in Fig. 9, V2 (2) cannot be formed within the time shift Δt2. Moreover, when Vv2'
is large, V1 (2) cannot be formed within the time zone Δt1.
[0068] This problem can be solved by increasing the switching period Tsw described in PTL
1 (referred to as the control period in PTL 1). When the time shift Δt1 and the time
shift Δt2 are set at fixed times, the proportion of Tsw occupied by the time shift
Δt1 and the time shift Δt2 can be reduced by increasing Tsw. As a result, current
detection can be performed even when the intermediate phase voltage is small such
that Dsvp1 is small or when the intermediate phase voltage is large such that Dsvp1
is large, as described above.
[0069] However, when Tsw is increased, a switching frequency given by the inverse of Tsw
decreases, and when this frequency enters the audible range, noise from the switching
frequency component increases. When the AC rotary machine 1a is used as a motor for
an electric power steering, for example, the switching frequency is set to be no lower
than 20 kHz (i.e. outside the band of the audible range).
[0070] The reason for this is that the audible range of a human being is between 20 Hz and
20 kHz, and therefore, by setting the switching frequency to be no lower than 20 kHz
(i.e. outside the band of the audible range), the sound of the switching frequency
component cannot be heard by human ears. When the switching frequency is reduced below
20 kHz in order to secure the time shift Δt1 and the time shift Δt2, however, the
sound of the switching frequency component can be heard by human ears as noise.
[0071] Further, when noise is avoided by limiting an amplitude of the first voltage command
so that the first intermediate phase voltage Emid1 remains within a range in which
the time shifts Δt1 and Δt2 can be secured, the voltage applied to the AC rotary machine
1a is limited, and therefore a high output cannot be generated by the AC rotary machine
1a.
[0072] Returning to this invention, Fig. 12 is an illustrative view relating to a function
of the first detectability determination unit 12a according to the first embodiment
of this invention. More specifically, the first detectability determination unit 12a
determines whether the currents of the first windings can be detected by the first
current detector 4a or whether the currents of the second windings can be detected
by the second current detector 4b by determining whether or not the voltage command
value of the phase corresponding to the first intermediate phase voltage Emid1 and
the voltage command value of the phase corresponding to the second intermediate phase
voltage Emid2 are within a range no lower than a first predetermined value Vs1 and
no higher than a second predetermined value Vs2.
[0073] Here, when the first intermediate phase voltage Emid1 and the second intermediate
phase voltage Emid2 are equal to Vs1, this means that the ON time of the upper side
arm element at the intermediate phase voltage during Tsw is equal to Tsw - Δt1. Hence,
the first predetermined value Vs1 corresponds to an upper limit value at which the
time shift Δt1 can be secured.
[0074] Meanwhile, when the first intermediate phase voltage Emid1 and the second intermediate
phase voltage Emid2 are equal to Vs2, this means that Δt2 can be secured within Tsw
by the ON time of the upper side arm element at the intermediate phase voltage. Hence,
the second predetermined value Vs2 corresponds to a lower limit value at which the
time shift Δt2 can be secured.
[0075] In Fig. 12(a), a dotted line indicates the first voltage commands Vu1', Vv1', Vw1'
shown in Fig. 7(b), a solid line indicates the first intermediate phase voltage Emid1,
and dot-dash lines indicate the first predetermined value Vs1 and the second predetermined
value Vs2. Here, Vs1 = 0.4 Vdc1 and Vs2 = -0.4 Vdc1.
[0076] Fig. 12(b) shows the output of the first detectability determination unit 12a. The
first detectability determination unit 12a determines whether or not the currents
of the first windings can be detected by determining whether or not the first intermediate
phase voltage Emid1 is within the range extending from the first predetermined value
Vs1 to the second predetermined value Vs2. The first detectability determination unit
12a outputs the first detectability determination signal flag_1 at 1 when the first
intermediate phase voltage Emid1 is within the range extending from the first predetermined
value Vs1 to the second predetermined value Vs2, and outputs the first detectability
determination signal flag_1 at 0 when the first intermediate phase voltage Emid1 is
outside the range.
[0077] In Fig. 12(c), a dotted line indicates the second voltage commands Vu2', Vv2', Vw2'
shown in Fig. 8(b), a solid line indicates the second intermediate phase voltage Emid2,
and dot-dash lines indicate Vs1 and Vs2. Fig. 12(d) shows a second detectability determination
signal flag_2 indicating whether or not the second intermediate phase voltage Emid2
is within the range extending from the first predetermined value Vs1 to the second
predetermined value Vs2. The second detectability determination signal flag_2 is set
at 1 when the second intermediate phase voltage Emid2 is within the range extending
from the first predetermined value Vs1 to the second predetermined value Vs2, and
set at 0 when the second intermediate phase voltage Emid1 is outside the range.
[0078] Note that the second detectability determination signal flag_2 serves as the output
of a second detectability determination unit 701 a to be described below in eighth
to tenth embodiments using Figs. 25, 28, and 31. As shown in Fig. 1, a second detectability
determination unit is not used in the first embodiment, but is illustrated in Fig.
12 for descriptive purposes.
[0079] Focusing on the first detectability determination signal flag_1, the first detectability
determination signal flag_1 shifts to 0 in the vicinity of a voltage phase angle θv
of 60 × x (x: 0, 1, 2, 3, 4, 5, 6) degrees. Focusing on the second detectability determination
signal flag_2, the second detectability determination signal flag_2 shifts to 0 in
the vicinity of a voltage phase angle θv of 30 + 60 × x (x: 0, 1, 2, 3, 4, 5) degrees.
Hence, the voltage phase angles θv at which the first detectability determination
signal flag_1 and the second detectability determination signal flag_2 shift to 0
deviate from each other by 30 degrees, and therefore, when flag_1 is at 0, flag_2
is at 1, and conversely when flag_1 is at 1, flag_2 is at 0.
[0080] Fig. 13 is a flowchart showing a series of operations performed by the first detectability
determination unit 12a according to the first embodiment of this invention. In step
S1000a, the first detectability determination unit 12a calculates the first intermediate
phase voltage Emid1 on the basis of the first voltage commands Vu1', Vs1', Vw1'. In
step S1000b, the first detectability determination unit 12a determines whether or
not the first intermediate phase voltage Emid1 is equal to or smaller than the first
predetermined value Vs1. When "YES" is obtained, the routine advances to step S1000c,
and when "NO" is obtained, the routine advances to step S1000e.
[0081] In step S1000c, the first detectability determination unit 12a determines whether
or not the first intermediate phase voltage Emid1 equals or exceeds the second predetermined
value Vs2. When "YES" is obtained, the routine advances to step S1000d, and when "NO"
is obtained, the routine advances to step S1000e.
[0082] In a case where the routine advances to step S1000d, the first detectability determination
unit 12a inserts 1 into the first detectability determination signal flag_1. In a
case where the routine advances to step S1000e, the first detectability determination
unit 12a inserts 0 into the first detectability determination signal flag_1.
[0083] Finally, when the first detectability determination signal flag_1 is at 1, the first
detectability determination unit 12a determines that the currents of the first windings
are detectable, and therefore switches the switch 7a so that the currents Id1, Iq1
on two rotational axes, determined from the first winding currents, are output respectively
as Id', Iq'. When the first detectability determination signal flag_1 is at 0, on
the other hand, the first detectability determination unit 12a determines that the
currents of the first windings are undetectable, and therefore switches the switch
7a so that the currents Id2, Iq2 on two rotational axes, determined from the second
winding currents, are output respectively as Id', Iq'.
[0084] According to the first embodiment, as described above, a determination as to whether
or not the first current detection unit 4a can detect the currents of the first windings
is made on the basis of the first voltage commands. When it is determined that the
currents of the first windings are detectable, the first voltage commands and second
voltage commands are calculated on the basis of the currents of the first windings,
and when it is determined that the currents of the first windings are undetectable,
the first voltage commands and second voltage commands are calculated on the basis
of the currents of the second windings.
[0085] By providing this configuration, the amplitude of the first voltage commands and
the second voltage commands can be increased without lengthening the switching period
Tsw, as in PTL 1, and without limiting the amplitude of the first voltage commands
in order to secure a time shift for the first intermediate phase voltage. As a result,
the output of the AC rotary machine 1a can be increased while keeping noise generated
thereby low.
Second Embodiment
[0086] In a second embodiment, a first detectability determination unit 12b that determines
whether or not the currents of the first windings are detectable by different processing
to that of the first detectability determination unit 12a according to the first embodiment
will be described. The second embodiment is configured basically identically to the
first embodiment shown in Fig. 1, and differs only in that the first detectability
determination unit 12a shown in Fig. 1 is replaced with the first detectability determination
unit 12b. Accordingly, the following description centers on the first detectability
determination unit 12b that differs from the first embodiment.
[0087] Fig. 14 is a flowchart showing a series of operations performed by the first detectability
determination unit 12b according to the second embodiment of this invention. In step
S2000a, the first detectability determination unit 12b determines the first maximum
phase voltage Emax1, the first intermediate phase voltage Emid1, and the first minimum
phase voltage Emin1 from the first voltage commands Vu1', Vv1', Vw1'.
[0088] In step S2000b, the first detectability determination unit 12b determines whether
or not a difference Emax1 - Emid1 between the first maximum phase voltage and the
first intermediate phase voltage equals or exceeds a third predetermined value Vs3.
When "YES" is obtained, the routine advances to step S2000c, and when "NO" is obtained,
the routine advances to step S2000e.
[0089] In step S2000c, the first detectability determination unit 12b determines whether
or not a difference Emid1 - Emin1 between the first intermediate phase voltage and
the first minimum phase voltage equals or exceeds the third predetermined value Vs3.
When "YES" is obtained, the routine advances to step S2000d, and when "NO" is obtained,
the routine advances to step S2000e.
[0090] In a case where the routine advances to step S2000d, the first detectability determination
unit 12b inserts 1 into the first detectability determination signal flag_1. In a
case where the routine advances to step S2000e, the first detectability determination
unit 12b inserts 0 into the first detectability determination signal flag_1.
[0091] Here, the third predetermined value Vs3 may be determined on the basis of a ratio
between the time shift Δt1 or Δt2 and the switching period Tsw. For example, when
the time shift Δt1 = Δt2 = 5 µs and the switching period is set as Tsw, the third
predetermined value Vs3 is Δt1/Tsw × Vdc = 0.1 Vdc.
[0092] Fig. 15 is a view showing waveforms described in the steps of Fig. 14 in a case where
the third predetermined value Vs3 is set at 0.1 Vdc, according to the second embodiment
of this invention. More specifically, Fig. 15(a) shows the first voltage commands
Vu1', Vv1', Vw1', and Fig. 15(b) shows the first maximum phase voltage Emax1, the
first intermediate phase voltage Emid1, and the first minimum phase voltage Emin1
mentioned in step S2000a.
[0093] Fig. 15(c) shows the difference Emax1 - Emid1 between the first maximum phase voltage
and the first intermediate phase voltage and the difference Emid1 - Emin1 between
the first intermediate phase voltage and the first minimum phase voltage, mentioned
respectively in steps S2000b and S2000c. Further, Fig. 15(d) shows the first detectability
determination signal flag_1 mentioned in steps S2000d and S2000e.
[0094] According to the second embodiment, as described above, the difference between the
first maximum phase voltage and the first intermediate phase voltage and the difference
between the first intermediate phase voltage and the first minimum phase voltage are
respectively calculated, and when the values thereof are smaller than the third predetermined
value, the currents of the first windings are determined to be undetectable. By performing
this determination processing, identical effects to those of the first embodiment
can be obtained.
[0095] Note that in the second embodiment, the first detectability determination unit 12b
determines the detectability of the currents of the first windings on the basis of
the first voltage commands Vu1', Vs1', Vw1' serving as the output of the offset calculator
11 a. However, identical calculation results are obtained for Emax1 - Emid1 and Emid1
- Emin1 when Emax1 - Emid1 and Emid1 - Emin1 are calculated on the basis of the first
voltage commands Vu1, Vv1, Vw1 serving as the input of the offset calculator 11a instead
of the first voltage commands Vu1', Vv1', Vw1' serving as the output of the offset
calculator 11a. Hence, identical effects to those obtained when Emax1 - Emid1 and
Emid1 - Emin1 are calculated on the basis of the first voltage commands Vu1', Vv1',
Vw1' are obtained with a configuration in which the first voltage commands Vu1, Vv1,
Vw1 are input into the first detectability determination unit 12b.
Third Embodiment
[0096] In a third embodiment, a first detectability determination unit 12c that determines
whether or not the currents of the first windings are detectable by different processing
to that of the first detectability determination unit 12a according to the first embodiment
and the first detectability determination unit 12b according to the second embodiment
will be described. The third embodiment is configured basically identically to the
first embodiment shown in Fig. 1, and differs only in that the first detectability
determination unit 12a shown in Fig. 1 is replaced with the first detectability determination
unit 12c. Accordingly, the following description centers on the first detectability
determination unit 12c that differs from the first and second embodiments.
[0097] The first detectability determination unit 12c calculates the voltage phase angle
θv on the basis of the first voltage commands Vu1', Vv1', Vw1' using Equation (21),
shown below, and determines the detectability of the currents of the first windings
in accordance with a region of the voltage phase angle θv.
[Math. 1]

[0098] In the first embodiment described above, the currents of the first windings are determined
to be undetectable when the voltage phase angle θv is in the vicinity of 60 × x (x:
0, 1, 2, 3, 4, 5, 6) degrees. Therefore, when θv obtained in the calculation based
on the first voltage commands is within a range no lower than 60 × x - α and no higher
than 60 × x + α (where α is a margin), the first detectability determination unit
12c determines that the currents of the first windings are undetectable, and outputs
0 as flag_1. When θv is outside this range, on the other hand, the first detectability
determination unit 12c determines that the currents of the first windings are detectable,
and outputs 1 as flag_1.
[0099] Note that the margin α is determined from the time shifts Δt1 and Δt2, the maximum
value of the first voltage commands, and so on, but is set at a magnitude no greater
than 30 degrees.
[0100] According to the third embodiment, as described above, the voltage phase angle of
the first voltage commands is calculated, whereupon the detectability of the currents
of the first windings is determined in accordance with the region of the voltage phase
angle. Likewise with this configuration, identical effects to those of the first and
second embodiments can be obtained.
[0101] Note that in the third embodiment, the first detectability determination unit 12c
determines the detectability of the currents of the first windings on the basis of
the first voltage commands Vu1', Vv1', Vw1' serving as the output of the offset calculator
11 a. However, an identical calculation result to that of Equation (21) is obtained
when the detectability of the currents of the first windings is calculated on the
basis of the first voltage commands Vu1, Vv1, Vw1 serving as the input of the offset
calculator 11a instead of the first voltage commands Vu1', Vv1', Vw1' serving as the
output of the offset calculator 11a. Hence, identical effects to those obtained when
the detectability of the currents of the first windings is calculated on the basis
of the first voltage commands Vu1', Vv1', Vw1' are obtained with a configuration in
which the first voltage commands Vu1, Vv1, Vw1 are input into the first detectability
determination unit 12c.
[0102] All other methods of determining the detectability of the currents of the first windings
on the basis of the voltage phase angle θv after determining the voltage phase angle
θv on the basis of the voltage commands, such as a method of determining the voltage
phase angle θv on the basis of the voltage commands Vd, Vq on two rotational axes,
are included in this invention.
Fourth Embodiment
[0103] In a fourth embodiment, a first detectability determination unit 12d that determines
whether or not the currents of the first windings are detectable by different processing
to that of the first detectability determination units 12a, 12b, and 12c according
to the first to third embodiments will be described. Fig. 16 is a view showing an
overall configuration of a control apparatus for an AC rotary machine according to
the fourth embodiment of this invention. In the fourth embodiment, the first detectability
determination unit 12d determines the detectability of the currents of the first windings
on the basis of the second voltage commands Vu2', Vv2', Vw2' rather than the first
voltage commands Vu1', Vv1', Vw1'. Accordingly, the following description centers
on the first detectability determination unit 12d that differs from the first to third
embodiments.
[0104] The first detectability determination unit 12d shown in Fig. 16 calculates the voltage
phase angle θv on the basis of the second voltage commands Vu2', Vv2', Vw2' using
Equation (22), shown below, and determines the detectability of the currents of the
first windings in accordance with the region of the voltage phase angle θv.
[Math. 2]

[0105] In the first embodiment described above, the currents of the first windings are
determined to be undetectable when the voltage phase angle θv is in the vicinity of
60 × x (x: 0, 1, 2, 3, 4, 5, 6) degrees. Therefore, when θv obtained in the calculation
based on the second voltage commands is within a range of no lower than 60 × x - α
and no higher than 60 × x + α (where α is a margin), the first detectability determination
unit 12d determines that the currents of the first windings are undetectable, and
outputs 0 as flag_1. When θv is outside this range, on the other hand, the first detectability
determination unit 12d determines that the currents of the first windings are detectable,
and outputs 1 as flag_1.
[0106] Note that the margin α is determined from the time shifts Δt1 and Δt2, the maximum
value of the first voltage commands, and so on, but is set at a magnitude no greater
than 30 degrees.
[0107] According to the fourth embodiment, as described above, the voltage phase angle of
the second voltage commands is calculated, whereupon the detectability of the currents
of the first windings is determined in accordance with the region of the voltage phase
angle. Likewise with this configuration, identical effects to those of the first to
third embodiments can be obtained.
[0108] Note that in the fourth embodiment, the first detectability determination unit 12d
determines the detectability of the currents of the first windings on the basis of
the second voltage commands Vu2', Vv2', Vw2' serving as the output of the offset calculator
11b. However, an identical calculation result to that of Equation (22) is obtained
when the detectability of the currents of the first windings is calculated on the
basis of the second voltage commands Vu2, Vv2, Vw2 serving as the input of the offset
calculator 11b instead of the second voltage commands Vu2', Vv2', Vw2' serving as
the output of the offset calculator 11b. Hence, identical effects to those obtained
when the calculation is performed on the basis of the second voltage commands Vu2',
Vv2', Vw2' are obtained with a configuration in which the second voltage commands
Vu2, Vv2, Vw2 are input into the first detectability determination unit 12d.
[0109] Furthermore, an average of the voltage phase angle θv based on the first voltage
commands, obtained from the third embodiment, and the voltage phase angle θv based
on the second voltage commands, obtained from the fourth embodiment, may be calculated,
whereupon the detectability of the currents of the first windings may be determined
on the basis of the averaged voltage phase angle θv. In this case, an effect of suppressing
a noise component included in the voltage phase angle θv by averaging the voltage
phase angle θv can be obtained.
Fifth Embodiment
[0110] Fig. 17 is a view showing an overall configuration of a control apparatus for an
AC rotary machine according to a fifth embodiment of this invention. The fifth embodiment
differs from the first to fourth embodiments in including a first current detection
unit 4c, a second current detection unit 4d, and a first detectability determination
unit 12e in place of the first current detection unit 4a, the second current detection
unit 4b, and the first detectability determination unit 12a (12b to 12d). Accordingly,
the following description centers on these differences.
[0111] The first current detection unit 4c according to the fifth embodiment is formed by
providing current sensors such as shunt resistors or current transformers (CTs) respectively
in series with the lower side arm elements of the respective phases (Sun1, Svn1, Swn1)
of the first voltage application unit 3a. Fig. 18 is a view showing relationships
between the first voltage vector V0 (1) to V7 (1) corresponding to the ON/OFF conditions
of the semiconductor switches Sup1 to Swn1 and the currents Iu1, Iv1, Iw1 of the first
windings, according to the fifth embodiment of this invention. Note that with respect
to Sup1 to Swn1 in Fig. 18, "1" and "0" respectively indicate a condition in which
the switch is ON and a condition in which the switch is OFF. The first current detection
unit 4c detects the currents Iu1, Iv1, Iw1 of the first windings individually on the
basis of the relationships shown in Fig. 18.
[0112] In the fifth embodiment, current sensors are provided in series with the lower arm
elements of the respective phases, and therefore current detection is possible only
in a phase where the lower side arm elements are switched ON. For example, when the
first voltage vector is at V1(1), the switches Sup1, Svn1, and Swn1 are switched ON,
and therefore, in the U1 phase, the upper side arm elements are switched ON, whereas
in the V1 phase and the W1 phase, the lower side arm elements are switched ON. As
a result, the current Iv1 that flows in the V1 phase and the current Iw1 that flows
in the W1 phase are detectable, but the current Iu1 that flows in the U1 phase is
undetectable. Accordingly, Iu1 is detected from Iv1 and Iw1 using the fact that the
sum of the currents of the three phases is zero.
[0113] Hence, when the first voltage vector is at V1(1), currents Iu1_s, Iv1_s, Iw1_s flowing
through the current sensors provided on the U1, V1, and W1 phases are 0, -Iv1, and
-Iw1, respectively (see Fig. 18). Similarly, currents Iu_s, Iv_s, Iw_s flowing through
the current sensors when the first voltage vector is at V3 (1) and V5 (1) are as shown
in Fig. 18.
[0114] When the first voltage vector is at V2 (1), V4 (1), and V6 (1), only one of the currents
Iu1, Iv1, Iw1 of the first windings is detectable, and therefore the currents of the
three phases cannot be obtained.
[0115] The second current detection unit 4d is formed by providing current sensors such
as shunt resistors or current transformers (CTs) respectively in series with the lower
side arm elements of the respective phases (Sun2, Svn2, Swn2) of the second voltage
application unit 3b. Fig. 19 is a view showing relationships between the second voltage
vector V0 (2) to V7 (2) corresponding to the ON/OFF conditions of the semiconductor
switches Sup2 to Swn2 and the currents Iu2, Iv2, Iw2 of the second windings, according
to the fifth embodiment of this invention. Note that with respect to Sup2 to Swn2
in Fig. 19, "1" and "0" respectively indicate a condition in which the switch is ON
and a condition in which the switch is OFF. The second current detection unit 4d detects
the currents Iu2, Iv2, Iw2 of the second windings individually on the basis of the
relationships shown in Fig. 19.
[0116] Since the current sensors are provided in series with the lower arm elements of the
respective phases, current detection is possible only in a phase where the lower side
arm elements are switched ON. For example, when the second voltage vector is at V1
(2), the switches Sup2, Svn2, and Swn2 are switched ON, and therefore, in the U2 phase,
the upper side arm elements are switched ON, whereas in the V2 phase and the W2 phase,
the lower side arm elements are switched ON. As a result, the current Iv2 that flows
in the V2 phase and the current Iw2 that flows in the W2 phase are detectable, but
the current Iu2 that flows in the U2 phase is undetectable. Accordingly, Iu2 is detected
from Iv2 and Iw2 using the fact that the sum of the currents of the three phases is
zero.
[0117] Hence, when the second voltage vector is at V1 (2), currents Iu2_s, Iv2_s, Iw2_s
flowing through the current sensors provided on the U2, V2, and W2 phases are 0, -Iv2,
and -Iw2, respectively (see Fig. 19). Similarly, the currents Iu2_s, Iv2_s, Iw2_s
flowing through the current sensors when the second voltage vector is at V3 (2) and
V5 (2) are as shown in Fig. 19.
[0118] When the second voltage vector is at V2 (2), V4 (2), and V6 (2), only one of the
currents Iu2, Iv2, Iw2 of the first windings is detectable, and therefore the currents
of the three phases cannot be obtained.
[0119] Fig. 20 is a view illustrating an operation relating to the ON/OFF patterns of the
semiconductor switches and the period of the switching signal in the current detection
units, according to the fifth embodiment of this invention. More specifically, Fig.
20 is a view showing relationships between the ON/OFF patterns of the semiconductor
switches Sup1, Svp1, Swp1 of the first voltage application unit 3a and the semiconductor
switches Sup2, Svp2, Swp2 of the second voltage application unit 3b and the switching
period Tsw in the first current detection unit 4c and the second current detection
unit 4d.
[0120] In Fig. 20, similarly to Fig. 9 described above, when the first maximum phase voltage
Emax1, the first intermediate phase voltage Emid1, and the first minimum phase voltage
Emin1 are set in descending order in relation to the first voltage commands Vu1',
Vv1', Vw1', the relationships shown in Equations (15) to (17) are assumed to be established.
[0121] Similarly, when the second maximum phase voltage Emax2, the second intermediate phase
voltage Emid2, and the second minimum phase voltage Emin2 are set in descending order
in relation to the second voltage commands Vu2', Vv2', Vw2', the relationships shown
in Equations (18) to (20) are assumed to be established.
[0122] At the time t1 (n), Sup1 and Sup2 are set at 1 and Svp1, Swp1, Svp2, and Swp2 are
set at 0, whereupon this condition is maintained until the time t2 (n) arrives following
the elapse of Δt1. In accordance with Figs. 18 and 19, the first voltage vector and
the second voltage vector are at V1 (1) and V1 (2), respectively, between the times
t1 (n) and t2 (n). The currents of the first windings are detected at the time ts1-1
(n) between the times t1 (n) and t2 (n).
[0123] The first voltage vector is at V1 (1), and therefore, in accordance with Fig. 18,
Iv1_s and Iw1_s are respectively equal to Iv1, Iw1, while Iu1 is determined from Iv1
and Iw1 using the fact that the sum of the currents of the three phases is zero. Further,
at the time ts1-1 (n), the currents of the second windings are detected. Here, the
second voltage vector is at V1 (2), and therefore, in accordance with Fig. 19, Iv2_s
and Iw2_s are respectively equal to Iv2, Iw2, while Iu2 is determined from Iv2 and
Iw2 using the fact that the sum of the currents of the three phases is zero.
[0124] Next, at the time t2 (n), Svp1, Svp2, Swp1, and Swp2 are set at 1. A pulse width
(a time during which "1" is maintained) of Sup1 to Swp2 is determined from a product
of the ON duties Dsup1 to Dswp2 corresponding to the respective switches and the switching
period Tsw.
[0125] In the fifth embodiment, as described above, the switches of the upper side arm elements
are switched ON initially in the phase corresponding to the first maximum phase voltage
Emax1, and then switched ON in the phase corresponding to the first intermediate phase
voltage Emid1 and the phase corresponding to the first minimum phase voltage Emin1
at intervals of the time shift Δt1. By performing switching in this manner, a first
voltage vector (V1 (1) or V1 (3) or V1 (5)) with which two of the currents Iu1, Iv1,
Iw1 of the first windings can be detected is formed, as shown in Fig. 18, and a second
voltage vector (V1 (2) or V3 (2) or V5 (2)) with which two of the currents Iu2, Iv2,
Iw2 of the second windings can be detected is formed, as shown in Fig. 19.
[0126] Depending on the voltage command value of the phase corresponding to the first intermediate
phase voltage Emid1, however, it may be possible to detect only one of the currents
Iu1, Iv1, Iw1 of the first windings. A case of this type is illustrated in the example
shown in Fig. 20. When Vv1 is larger than the first predetermined value Vs1 and Dsvp1
× Tsw is larger than Tsw - Δt1, a pulse width corresponding to Dsvp1 × Tsw cannot
be obtained unless Svp1 is switched ON before the time t2 (n), even in a case where
Svp1 is switched OFF at the time t4 (n) indicating the end of the switching period
Tsw. As a result, V1 (1) cannot be formed within the time zone of Δt1, and therefore
the currents of the first windings cannot be detected.
[0127] Likewise with respect to the second voltage application unit 3b, when Vv2' is larger
than the first predetermined value Vs1 in Fig. 20, V1 (2) cannot be formed within
the time zone of the time shift Δt1, and therefore the currents of the second windings
cannot be detected.
[0128] Fig. 21 is an illustrative view relating to a function of the first detectability
determination unit 12e according to the fifth embodiment of this invention. More specifically,
the first detectability determination unit 12e determines whether or not the voltage
command value of the phase corresponding to the first intermediate phase voltage Emid1
and the voltage command value of the phase corresponding to the second intermediate
phase voltage Emid2 are within a range not exceeding the first predetermined value
Vs1 In Fig. 21(a), a dotted line indicates the first voltage commands Vu1', Vv1',
Vw1' shown in Fig. 7(b), a solid line indicates the first intermediate phase voltage
Emid1, and a dot-dash line indicates the first predetermined value Vs1. Similarly
to the first embodiment, as shown in Fig. 12, Vs1 = 0.4 Vdc1 is set.
[0129] Fig. 21(b) shows the output of the first detectability determination unit 12e. The
first detectability determination unit 12e determines whether or not the currents
of the first windings are detectable by determining whether or not the first intermediate
phase voltage Emid1 is within a range not exceeding the first predetermined value
Vs1. The first detectability determination unit 12e outputs the first detectability
determination signal flag_1 at 1 when the first intermediate phase voltage Emid1 is
within a range not exceeding the first predetermined value Vs1, and outputs the first
detectability determination signal flag_1 at 0 when the first intermediate phase voltage
Emid1 is outside this range.
[0130] In Fig. 21(c), a dotted line indicates the second voltage commands Vu2', Vv2', Vw2'
shown in Fig. 8(b), a solid line indicates the second intermediate phase voltage Emid2,
and a dot-dash line indicates Vs1. Fig. 21(d) shows the second detectability determination
signal flag_2 indicating whether or not the second intermediate phase voltage Emid2
is within a range not exceeding the first predetermined value Vs1. The second detectability
determination signal flag_2 is set at 1 when the second intermediate phase voltage
Emid2 is within this range, and set at 0 when the second intermediate phase voltage
Emid1 is outside the range.
[0131] Note that the second detectability determination signal flag_2 serves as the output
of the second detectability determination unit 701 a to be described below in eighth
to tenth embodiments using Figs. 25, 28, and 31. As shown in Fig. 17, a second detectability
determination unit is not used in the fifth embodiment, but is illustrated in Fig.
21 for descriptive purposes.
[0132] Focusing on the first detectability determination signal flag_1 the first detectability
determination signal flag_1 shifts to 0 in the vicinity of a voltage phase angle θv
of 60 + 120 × x (x: 0, 1, 2) degrees. Focusing on the second detectability determination
signal flag_2, the second detectability determination signal flag_2 shifts to 0 in
the vicinity of a voltage phase angle θv of 90 + 120 × x (x: 0, 1, 2) degrees. Hence,
the voltage phase angles θv at which the first detectability determination signal
flag_1 and the second detectability determination signal flag_2 shift to 0 deviate
from each other by 30 degrees, and therefore, when flag_1 is at 0, flag_2 is at 1,
and conversely when flag_1 is at 1, flag_2 is at 0.
[0133] Fig. 22 is a flowchart showing a series of operations performed by the first detectability
determination unit 12e according to the fifth embodiment of this invention. In step
S4000a, the first detectability determination unit 12e calculates the first intermediate
phase voltage Emid1 on the basis of the first voltage commands Vu1', Vv1', Vw1'. In
step S4000b, the first detectability determination unit 12e determines whether or
not the first intermediate phase voltage Emid1 is equal to or smaller than the first
predetermined value Vs1. When "YES" is obtained, the routine advances to step S4000c,
and when "NO" is obtained, the routine advances to step S4000d.
[0134] In a case where the routine advances to step S4000c, the first detectability determination
unit 12e inserts 1 into the first detectability determination signal flag_1. In a
case where the routine advances to step S4000d, on the other hand, the first detectability
determination unit 12e inserts 0 into the first detectability determination signal
flag_1.
[0135] Finally, when the first detectability determination signal flag_1 is at 1, the first
detectability determination unit 12e determines that the currents of the first windings
are detectable, and therefore switches the switch 7a so that the currents Id1, Iq1
on two rotational axes, determined from the first winding currents, are output respectively
as Id', Iq'. When the first detectability determination signal flag_1 is at 0, on
the other hand, the first detectability determination unit 12e determines that the
currents of the first windings are undetectable, and therefore switches the switch
7a so that the currents Id2, Iq2 on two rotational axes, determined from the second
winding currents, are output respectively as Id', Iq'.
[0136] According to the fifth embodiment, as described above, the currents of the first
windings are detected on the basis of the currents flowing through the lower side
arm elements of the respective phases of the first voltage application unit, and the
currents of the second windings are detected on the basis of the currents flowing
through the lower side arm elements of the respective phases of the second voltage
application unit. Likewise with this configuration, identical effects to those of
the first embodiment can be obtained.
[0137] Further, flag_1 indicates 0 when the voltage phase angle θv is in the vicinity of
60 + 120 × x (x: 0, 1, 2) degrees. Therefore, by referring to the changes implemented
in the third embodiment from the first embodiment, the detectability of the first
windings can be determined on the basis of the voltage phase angle θv calculated from
the first voltage commands likewise in a configuration where the first current detection
unit detects the currents of the first windings on the basis of the currents flowing
through the lower side arm elements of the respective phases of the first voltage
application unit.
[0138] Moreover, by referring to the changes implemented in the fourth embodiment from the
first embodiment, the detectability of the first windings can be determined on the
basis of the voltage phase angle θv calculated from the second voltage commands likewise
in a configuration where the first current detection unit detects the currents of
the first windings on the basis of the currents flowing through the lower side arm
elements of the respective phases of the first voltage application unit.
[0139] Furthermore, in the fifth embodiment, the first current detection unit detects the
currents of the first windings on the basis of the currents flowing through the lower
side arm elements of the respective phases of the first voltage application unit,
while the second current detection unit detects the currents of the second windings
on the basis of the currents flowing through the lower side arm elements of the respective
phases of the second voltage application unit. Instead, however, this invention may
be implemented with a similar configuration in which the first current detection unit
detects the currents of the first windings on the basis of the currents flowing through
the lower side arm elements of any two of the three phases of the first voltage application
unit and the second current detection unit detects the currents of the second windings
on the basis of the currents flowing through the lower side arm elements of any two
of the three phases of the second voltage application unit.
Sixth Embodiment
[0140] Fig. 23 is a view showing an overall configuration of a control apparatus for an
AC rotary machine according to a sixth embodiment of this invention. The sixth embodiment
differs from the first to fifth embodiments, described above, in that the first current
detection unit 4a is used to detect the currents of the first windings and a second
current detection unit 4d is used to detect the currents of the second windings. Accordingly,
the following description centers on this difference.
[0141] In the sixth embodiment, the first voltage application unit 3a generates the ON/OFF
patterns indicated by Sup1, Svp1, Swp1 in Fig. 9, as described in the first embodiment,
while the second voltage application unit 3b generates the ON/OFF patterns indicated
by Sup2, Svp2, Swp2 in Fig. 20, as described in the fifth embodiment.
[0142] As shown in Fig. 12 of the first embodiment, when the currents Iu1, Iv1, Iw1 of the
first windings are detected on the basis of the current flowing through the DC bus
line of the first voltage application unit 3a, which is detected by the first current
detection unit 4a, flag_1 is set at 0 in the vicinity of a voltage phase angle θv
of 60 × x (x: 0, 1, 2, 3, 4, 5, 6) degrees, and in this case, the currents of the
first windings cannot be detected.
[0143] Further, as shown in Fig. 21 of the fifth embodiment, when the currents Iu2, Iv2,
Iw2 of the second windings are detected on the basis of the currents flowing through
the lower arm elements of the second voltage application unit 3b, which are detected
by the second current detection unit 4d, flag_2 is set at 0 in the vicinity of a voltage
phase angle θv of 90 + 120 × x (x: 0, 1, 2) degrees, and in this case, the currents
of the second windings cannot be detected.
[0144] Hence, even when a configuration such as that shown in Fig. 23 is employed, flag_1
and flag_2 do not shift to 0 simultaneously, and at least one of flag_1 and flag_2
is set at 1. Therefore, likewise with the configuration of the sixth embodiment, similarly
to the first to fifth embodiments, the first voltage commands and second voltage commands
can be calculated on the basis of the currents Iu1, Iv1, Iw1 of the first windings
when flag_1 is at 1 (i.e. when the currents of the first windings are detectable),
and the first voltage commands and second voltage commands can be calculated on the
basis of the currents Iu2, Iv2, Iw2 of the second windings when flag_1 is at 0 (i.e.
when the currents of the first windings are undetectable).
[0145] According to the sixth embodiment, as described above, the first current detection
unit detects the currents of the first windings on the basis of the current flowing
through the DC bus line of the first voltage application unit, while the second current
detection unit detects the currents of the second windings on the basis of the currents
flowing through the lower arm elements of the respective phases of the second voltage
application unit. With this configuration, identical effects to those of the first
to fifth embodiments can be obtained.
Seventh Embodiment
[0146] Fig. 24 is a view showing an overall configuration of a control apparatus for an
AC rotary machine according to a seventh embodiment of this invention. The seventh
embodiment differs from the first to sixth embodiments in that a first current detection
unit 4c is used to detect the currents of the first windings and the second current
detection unit 4b is used to detect the currents of the second windings. Accordingly,
the following description centers on this difference.
[0147] In the seventh embodiment, the first voltage application unit 3a generates the ON/OFF
patterns indicated by Svp1, Svp1, Swp1 in Fig. 20, as described in the fifth embodiment,
while the second voltage application unit 3b generates the ON/OFF patterns indicated
by Sup2, Svp2, Swp2 in Fig. 9, as described in the first embodiment.
[0148] As shown in Fig. 21 of the fifth embodiment, when the currents Iu1, Iv1, Iw1 of the
first windings are detected on the basis of the currents flowing through the lower
arm elements of the respective phases of the first voltage application unit 3a, which
are detected by the first current detection unit 4c, flag_1 is set at 0 in the vicinity
of a voltage phase angle θv of 60 + 120 × x (x: 0, 1, 2) degrees, and in this case,
the currents of the first windings cannot be detected.
[0149] Further, as shown in Fig. 12 of the first embodiment, when the currents Iu2, Iv2,
Iw2 of the second windings are detected on the basis of the current flowing through
the DC bus line of the second voltage application unit 3b, which is detected by the
second current detection unit 4b, flag_2 is set at 0 in the vicinity of a voltage
phase angle θv of 30 + 60 × x (x: 0, 1, 2, 3, 4, 5) degrees, and in this case, the
currents of the second windings cannot be detected.
[0150] Hence, even when a configuration such as that shown in Fig. 24 is employed, flag_1
and flag_2 do not shift to 0 simultaneously, and at least one of flag_1 and flag_2
is set at 1. Therefore, likewise with the configuration of the seventh embodiment,
similarly to the first to fifth embodiments, the first voltage commands and second
voltage commands can be calculated on the basis of the currents Iu1, Iv1, Iw1 of the
first windings when flag_1 is at 1 (i.e. when the currents of the first windings are
detectable), and the first voltage commands and second voltage commands can be calculated
on the basis of the currents Iu2, Iv2, Iw2 of the second windings when flag_1 is at
0 (i.e. when the currents of the first windings are undetectable).
[0151] According to the seventh embodiment, as described above, the first current detection
unit detects the currents of the first windings on the basis of the currents flowing
through the lower arm elements of the respective phases of the first voltage application
unit, while the second current detection unit detects the currents of the second windings
on the basis of the current flowing through the DC bus line of the second voltage
application unit. With this configuration, identical effects to those of the first
to sixth embodiments can be obtained.
Eighth Embodiment
[0152] Fig. 25 is a view showing an overall configuration of a control apparatus for an
AC rotary machine according to an eighth embodiment of this invention. The configuration
of the eighth embodiment differs from that of the first embodiment in further including
the second detectability determination unit 701a, and in an internal configuration
of a control unit 5b. Accordingly, the following description centers on these differences.
[0153] The second detectability determination unit 701a outputs the second detectability
determination signal flag_2 for determining whether or not the currents of the second
windings are detectable on the basis of the second voltage commands Vu2', Vv2', Vw2'.
[0154] Next, changes implemented on the control unit 5b according to the eighth embodiment
from the control unit 5a according to the first embodiment will be described. A switch
7b according to the eighth embodiment switches selectively between currents Id1',
Iq1' on two rotational axes and currents Id2', Iq2' on two rotational axes, among
the currents Id1, Iq1 of the first windings and the currents Id2, Iq2 of the second
windings, on the basis of the first detectability determination signal flag_1 and
the second detectability determination signal flag_2, and outputs the selected currents.
[0155] A subtractor 708a calculates a deviation dId1 between a d axis current command Id*
of the AC rotary machine 1a and the current Id1' on two rotational axes, output by
the switch 7b.
A subtractor 708b calculates a deviation dIq1 between a q axis current command Iq*
of the AC rotary machine 1a and the current Iq1' on two rotational axes, output by
the switch 7b.
A subtractor 708c calculates a deviation dId2 between the d axis current command Id*
of the AC rotary machine 1a and the current Id2' on two rotational axes, output by
the switch 7b.
A subtractor 708d calculates a deviation dIq2 between the q axis current command Iq*
of the AC rotary machine 1a and the current Iq2' on two rotational axes, output by
the switch 7b.
[0156] A controller 709a calculates a first voltage command Vd1 for controlling the deviation
dId1 to zero using a P controller, a PI controller, and so on.
A controller 709b calculates a first voltage command Vq1 for controlling the deviation
dIq1 to zero using a P controller, a PI controller, and so on.
A controller 709c calculates a second voltage command Vd2 for controlling the deviation
dId2 to zero using a P controller, a PI controller, and so on.
A controller 709d calculates a second voltage command Vq2 for controlling the deviation
dlq2 to zero using a P controller, a PI controller, and so on.
[0157] A coordinate converter 710a calculates the first voltage commands Vu1, Vv1, Vw1 by
performing coordinate conversion to convert the first voltage commands Vd1, Vq1 to
three-phase AC coordinates on the basis of the first voltage commands Vd1, Vq1 and
the rotation position θ of the AC rotary machine 1a.
A coordinate converter 710b calculates the second voltage commands Vu2, Vv2, Vw2 by
performing coordinate conversion to convert the second voltage commands Vd2, Vq2 to
three-phase AC coordinates on the basis of the second voltage commands Vd2, Vq2 and
the position θ - 30, which is obtained by subtracting 30 degrees from the rotation
position θ of the AC rotary machine 1a.
[0158] In a case where the second current detection unit 4b detects the currents of the
second windings on the basis of the current flowing through the DC bus line of the
second voltage application unit 3b, as in the first embodiment, the currents of the
second windings are detectable when the second intermediate phase voltage Emid2 is
no higher than the first threshold Vs1 and no lower than the second threshold Vs2,
and undetectable when the second intermediate phase voltage Emid2 exceeds the first
threshold Vs1 or is lower than the second threshold Vs2.
[0159] A function of the second detectability determination unit 701a newly added in the
eighth embodiment will now be described on the basis of the above description. Fig.
26 is a flowchart showing a series of operations performed by the second detectability
determination unit 701a according to the eighth embodiment of this invention. In step
S7000a, the second detectability determination unit 701a calculates the second intermediate
phase voltage Emid2 on the basis of the second voltage commands Vu2', Vv2', Vw2'.
[0160] In step S7000b, the second detectability determination unit 701a determines whether
or not the second intermediate phase voltage Emid2 is equal to or lower than the first
predetermined value Vs1. When "YES" is obtained, the routine advances to step S7000c,
and when "NO" is obtained, the routine advances to step S7000e.
[0161] In step S7000c, the second detectability determination unit 701a determines whether
or not the second intermediate phase voltage Emid2 equals or exceeds the second predetermined
value Vs2. When "YES" is obtained, the routine advances to step S7000d, and when "NO"
is obtained, the routine advances to step S7000e. In a case where the routine advances
to step S7000d, the second detectability determination unit 701 a inserts 1 into the
second detectability determination signal flag_2. In a case where the routine advances
to step S7000e, the second detectability determination unit 701a inserts 0 into the
second detectability determination signal flag_2.
[0162] Next, operations of the switch 7b will be described using Fig. 27. Fig. 27 is a flowchart
showing a series of operations performed by the switch 7b according to the eighth
embodiment of this invention. Switching operations are performed by the switch 7b
in steps S7100c, S7100d, and S7100e in accordance with the determination result obtained
in step S7100a as to whether or not the first detectability determination signal flag_1
is equal to 1 and the determination result obtained in step S7100b as to whether or
not the second detectability determination signal flag_2 is equal to 1.
[0163] When flag_1 is equal to 1 and flag_2 is equal to 1, the routine advances to step
S7100c, where the currents Id1, Iq1 of the first windings are selected as Id1', Iq1'
and the currents Id2, Iq2 of the second windings are selected as Id2', Iq2'. The selected
currents are then output.
[0164] When flag_1 is equal to 1 but flag_2 is not equal to 1, the routine advances to step
S7100d, where the currents Id1, Iq1 of the first windings are selected as Id1', Iq1'
and the currents Id1, Iq1 of the first windings are also selected as Id2', Iq2'. The
selected currents are then output.
[0165] When flag_1 is not equal to 1, the routine advances to step S7100e, where the currents
Id2, Iq2 of the second windings are selected as Id1', Iq1' and the currents Id2, Iq2
of the second windings are also selected as Id2', Iq2', regardless of the value of
flag_2. The selected currents are then output.
[0166] In the eighth embodiment, the first voltage commands Vd1, Vq1 are determined by the
subtractors 708a, 708b and the controllers 709a, 709b using the current commands Id*,
Iq* and Id1', Iq1'. As a result, the first voltage commands Vd1, Vq1 are calculated
on the basis of Id1', Iq1'.
[0167] Further, the second voltage commands Vd2, Vq2 are determined by the subtractors 708c,
708d and the controllers 709c, 709d using the current commands Id*, Iq* and Id2',
Iq2'. As a result, the second voltage commands Vd2, Vq2 are calculated on the basis
of Id2', Iq2'.
[0168] When the first detectability determination unit 12a determines that the currents
of the first windings are detectable and the second detectability determination unit
701a determines that the currents of the second windings are detectable (i.e. when
the routine advances to step S7100c), the switch 7b switches the currents Id1, Iq1
of the first windings to Id1', Iq1', respectively, and switches the currents Id2,
Iq2 of the second windings to Id2', Iq2', respectively, and then outputs the switched
currents. Hence, in this case, the first voltage commands are calculated on the basis
of the currents of the first windings and the second voltage commands are calculated
on the basis of the currents of the second windings.
[0169] Further, when the first detectability determination unit 12a determines that the
currents of the first windings are undetectable (i.e. when the routine advances to
step S7100e), the switch 7b switches the currents Id2, Iq2 of the second windings
to Id1', Iq1', respectively, and also switches the currents Id2, Iq2 of the second
windings to Id2', Iq2', respectively, and then outputs the switched currents. Hence,
in this case, the first voltage commands and the second voltage commands are calculated
on the basis of the currents of the second windings.
[0170] Furthermore, when the first detectability determination unit 12a determines that
the currents of the first windings are detectable but the second detectability determination
unit 701a determines that the currents of the second windings are undetectable (i.e.
when the routine advances to step S7100d), the switch 7b switches the currents Id1,
Iq1 of the first windings to Id1', Iq1', respectively, and also switches the currents
Id1, Iq1 of the first windings to Id2', Iq2', respectively, and then outputs the switched
currents. Hence, in this case, the first voltage commands and the second voltage commands
are calculated on the basis of the currents of the first windings.
[0171] In the first to seventh embodiments, when the currents of the first windings are
undetectable, the first voltage commands and second voltage commands are calculated
using the currents of the second windings. In this case, as shown in Fig. 12(b), the
currents of the first windings are undetectable (flag_1 = 0) only in a section where
the voltage phase angle θv is in the vicinity of 60 × x (x: 0, 1, 2, 3, 4, 5) degrees,
and therefore a section in which the currents of the second windings are used is small.
[0172] In the eighth embodiment, on the other hand, the second detectability determination
unit 701a is provided in addition to the first detectability determination unit 12a,
and therefore the second voltage commands can be calculated on the basis of the currents
of the second windings when flag_2 is at 1, as shown in Fig. 12(d). Hence, in addition
to the effects of the first to seventh embodiments, the controllability of the currents
of the second windings can be improved, enabling further reductions in torque ripple,
vibration, and noise from the AC rotary machine 1a.
[0173] Moreover, by referring to the second embodiment, a method of calculating the difference
between the second maximum phase voltage and the second intermediate phase voltage
and the difference between the second intermediate phase voltage and the second minimum
phase voltage, and determining that the currents of the second windings are undetectable
when the respective values thereof are smaller than the third predetermined value,
may be employed as the method used by the second detectability determination unit
701a to determine the detectability of the currents of the second windings.
[0174] Further, by referring to the third and fourth embodiments so as to determine the
detectability of the currents of the second windings by determining the voltage phase
angle θv from at least one of the first voltage commands and the second voltage commands,
identical effects to the first embodiment can be obtained.
Ninth Embodiment
[0175] Fig. 28 is a view showing an overall configuration of a control apparatus for an
AC rotary machine according to a ninth embodiment of this invention. A configuration
of the ninth embodiment differs from the configuration of the eighth embodiment in
that a control unit 5c is used in place of the control unit 5b, and the following
description centers on this difference. Hence, the following description focuses on
changes implemented on the control unit 5c from the control unit 5b.
[0176] An adder 801a outputs an added value (Id1' + Id2') obtained by adding together the
current Id1' on two rotational axes and the current Id2' on two rotational axes.
An adder 801b outputs an added value (Iq1' + Iq2') obtained by adding together the
current Iq1' on two rotational axes and the current Iq2' on two rotational axes.
A subtractor 802a outputs a value (Id1' - Id2') obtained by subtracting the current
Id1' on two rotational axes from the current Id2' on two rotational axes. A subtractor
802b outputs a value (Iq1' - Iq2') obtained by subtracting the current Iq1' on two
rotational axes from the current Iq2' on two rotational axes.
[0177] A multiplier 803a multiplies the added value (Id1' + Id2') output by the adder 801a
by K1, and outputs the result as a sum current Id_sum. Here, K1 = 0.5. A multiplier
803b multiplies the added value (Iq1' + Iq2') output by the adder 801b by K1, and
outputs the result as a sum current Iq_sum. Here, K1 = 0.5. A multiplier 804a multiplies
the subtracted value (Id1' - Id2') output by the subtractor 802a by K2, and outputs
the result as a differential current delta_Id. Here, K2 = 0.5.
A multiplier 804b multiplies the subtracted value (Iq1' - Iq2') output by the subtractor
802b by K2, and outputs the result as a differential current delta_Iq. Here, K2 =
0.5.
[0178] A subtractor 805a calculates a deviation dId_sum between the d axis current command
Id* of the AC rotary machine 1a and the sum current Id_sum.
A subtractor 805b calculates a deviation dIq_sum between the q axis current command
Iq* of the AC rotary machine 1a and the sum current Iq_sum.
[0179] A controller 806a outputs a sum voltage Vd_sum at which the deviation dId_sum is
controlled to zero using a P controller, a PI controller, and the like on the basis
of a product of a proportional gain Kpd_sum of the used controllers and the deviation
dId_sum.
A controller 806b outputs a sum voltage Vq_sum at which the deviation dIq_sum is controlled
to zero using a P controller, a PI controller, and the like on the basis of a product
of a proportional gain Kpq_sum of the used controllers and the deviation dIq_sum.
[0180] A controller 806c outputs a differential voltage delta_Vd at which the differential
current delta_Id is controlled to zero using a P controller, a PI controller, and
the like on the basis of a product of a proportional gain Kpd_delta of the used controllers
and a deviation delta_dId.
A controller 806d outputs a differential voltage delta_Vq at which the differential
current delta_Iq is controlled to zero using a P controller, a PI controller, and
the like on the basis of a product of a proportional gain Kpq_delta of the used controllers
and a deviation delta_dIq.
[0181] An adder 807a outputs a value obtained by adding together the sum voltage Vd_sum
and the differential voltage delta_Vd as the first voltage command Vd1.
An adder 807b outputs a value obtained by adding together the sum voltage Vq_sum and
the differential voltage delta_Vq as the first voltage command Vq1.
A subtractor 808a outputs a value obtained by subtracting the sum voltage Vd_sum from
the differential voltage delta_Vd as the second voltage command Vd2.
A subtractor 808b outputs a value obtained by subtracting the sum voltage Vq_sum from
the differential voltage delta_Vq as the second voltage command Vq2.
[0182] Next, the operations performed by the control unit 5c according to the ninth embodiment
will be described in detail.
When the first detectability determination signal flag_1 and the second detectability
determination signal flag_2 are both at 1 (in other words, when the currents of the
first windings and the currents of the second windings are both determined to be detectable),
the currents Id1', Iq1' on two rotational axes and the currents Id2', Iq2' on two
rotational axes are equal to the currents Id1, Iq1 of the first windings and the currents
Id2, Iq2 of the second windings, respectively.
[0184] Hence, the sum currents are expressed by the sum of the currents of the first windings,
detected by the first current detection unit 4a, and the currents of the second windings,
detected by the second current detection unit 4b, while the differential currents
are expressed by the difference between the currents of the first windings, detected
by the first current detection unit 4a, and the currents of the second windings, detected
by the second current detection unit 4b.
[0185] The sum voltages Vd_sum, Vq_sum are calculated on the basis of the sum currents Id_sum,
Iq_sum and a sum current gain, while the differential voltages delta_Vd, delta_Vq
are calculated on the basis of the differential currents delta_Id, delta_Iq and a
differential current gain. Further, the first current commands Vd1, Vq1 and the second
current commands Vq1, Vq2 are calculated by the adders 807a, 807b and the subtractors
808a, 808b.
[0186] Here, the first three-phase windings U1, V1, W1 and the second three-phase windings
U2, V2, W2 of the AC rotary machine 1a are joined to each other magnetically, but
are not electrically connected. Hence, voltages that are proportionate to products
of respective differential values of the currents of the first windings and a mutual
inductance between the first windings and the second windings are generated in the
second three-phase windings. Meanwhile, voltages that are proportionate to products
of respective differential values of the currents of the second windings and the mutual
inductance between the first windings and the second windings are generated in the
first three-phase windings. In other words, the first windings and the second windings
interfere with each other magnetically.
[0187] In the ninth embodiment, however, the first voltage commands Vd1, Vd2 and the second
voltage commands Vq1, Vq2 are calculated on the basis of the sum currents and the
differential currents. As a result, when the currents of the first windings and the
currents of the second windings are both detectable, the voltage commands Vd1, Vq1
of the first windings are calculated in consideration of not only the currents of
the first windings, detected by the first current detection unit 4a, but also the
currents of the second windings, detected by the second current detection unit 4b.
[0188] Similarly, the second voltage commands Vd2, Vq2 are calculated in consideration of
not only the currents of the second windings, detected by the second current detection
unit 4b, but also the currents of the first windings, detected by the first current
detection unit 4a. Therefore, by providing the configuration of the ninth embodiment,
a more stable control system can be constructed with respect to magnetic interference
between the first windings and the second windings.
[0189] When the first detectability determination signal flag_1 is at 0 and the second detectability
determination signal flag_2 is at 1 (in other words, when the currents of the first
windings are determined to be undetectable but the currents of the second windings
are determined to be detectable), the currents Id1', Iq1' on two rotational axes are
equal to the currents Id2, Iq2 of the second windings and the currents Id2', Iq2'
on two rotational axes are also equal to the currents Id2, Iq2 of the second windings,
as shown in Fig. 27.
[0191] As shown in Equations (27) to (30), the sum currents are expressed by the currents
of the second windings, detected by the second current detection unit 4b, while the
differential currents are 0. Hence, the first voltage commands Vd1, Vq1 and the second
voltage commands Vd2, Vq2 are calculated on the basis of the currents of the second
windings and the sum current gain.
[0192] When the first detectability determination signal flag_1 is at 1 and the second detectability
determination signal flag_2 is at 0 (in other words, when the currents of the first
windings are determined to be detectable but the currents of the second windings are
determined to be undetectable), the currents Id1', Iq1' on two rotational axes are
equal to the currents Id1, Iq1 of the first windings and the currents Id2', Iq2' on
two rotational axes are also equal to the currents Id1, Iq1 of the first windings,
as shown in Fig. 27.
[0194] As shown in Equations (31) to (34), the sum currents are expressed by the currents
of the first windings, detected by the first current detection unit 4a, while the
differential currents are 0. Hence, the first voltage commands Vd1, Vq1 and the second
voltage commands Vd2, Vq2 are calculated on the basis of the currents of the first
windings and the sum current gain.
[0195] Here, the differential currents are set at 0 in accordance with Equations (29) and
(30) when the first detectability determination unit 12a outputs 0 as flag_1, and
are set at 0 in accordance with Equations (33) and (34) when the second detectability
determination unit 701a outputs 0 as flag_2. Accordingly, the differential voltages
obtained by multiplying the differential voltage gain by the sum currents also equal
zero. In this case, therefore, the differential voltages delta_Vd, delta_Vq may be
set at 0, and the subtractors 802a, 802b, the multipliers 804a, 804b, and the controllers
806c, 806d that calculate the differential voltages from the differential currents
may be omitted.
[0196] Further, by varying the differential current gains Kpd_delta, Kpq_delta on the basis
of at least one of the first voltage commands, the second voltage commands, the sum
voltage, and the rotation speed of the AC rotary machine 1a, pulsation in the differential
voltages delta_Vd, delta_Vq caused by pulsation in the differential currents delta_Id,
delta_Iq during switches in the first detectability determination signal flag_1 and
the second detectability determination signal flag_2 from 0 to 1 and from 1 to 0 can
be reduced.
[0197] Fig. 29 is a view showing a condition in which the differential current gains are
varied on the basis of the first voltage commands, according to the ninth embodiment
of this invention. Fig. 29 shows an example of a case in which the differential current
gains Kpd_delta, Kpq_delta are varied in accordance with an amplitude V1 of the first
voltage commands. When the amplitude V1 of the first voltage commands is no higher
than a threshold Vsa1, the differential current gains Kpd_delta, Kpq_delta are set
respectively at fixed values Kpd_delta1, Kpq_delta1. When the amplitude V1 of the
first voltage commands exceeds the threshold Vsa1, on the other hand, the differential
current gains Kpd_delta, Kpq_delta are reduced along a straight line. The threshold
Vsa1 and an incline of the straight line may be determined in accordance with a generated
pulsation level. Here, the amplitude V1 of the first voltage commands may be determined
using Equation (35), shown below.
[Math. 1]

[0198] Further, when a calculation load of a CPU that performs calculations as the control
unit 5c increases due to calculating the square root in Equation (35), the abscissa
of Fig. 29 may be set as the square of the amplitude. Furthermore, an amplitude V2
of the second voltage commands, which is given below in Equation (36), an amplitude
V_sum of the sum voltage, which is given below in Equation (37), or a combination
of V1, V2, and V_sum may be used as the abscissa of Fig. 29.

[0199] By varying the sum current gains Kpd_sum, Kpq_sum on the basis of at least one of
the first voltage commands, the second voltage commands, and the sum voltage, pulsation
in the sum voltages Vd_sum, Vq_sum caused by pulsation in the sum currents Id_sum,
Iq_sum during switches in the first detectability determination signal flag_1 and
the second detectability determination signal flag_2 can be reduced.
[0200] Fig. 30 is a view showing a condition in which the sum current gains are varied on
the basis of the first voltage commands, according to the ninth embodiment of this
invention. Fig. 30 shows an example of a case in which the sum current gains Kpd_sum,
Kpq_sum are varied in accordance with the amplitude V of the first voltage commands.
When the amplitude V1 of the first voltage commands is no higher than the threshold
Vsa1, the sum current gains Kpd_sum, Kpq_sum are set respectively at fixed values
Kpd_sum1, Kpq_sum1. When the amplitude V1 of the first voltage commands exceeds Vsa1,
on the other hand, the sum current gains Kpd_sum, Kpq_sum are reduced along a straight
line. The threshold Vsa1 and the incline of the straight line may be determined in
accordance with the generated pulsation level.
[0201] Further, the amplitude V1 of the first voltage commands is used as the abscissa in
Fig. 29, but the amplitude V2 of the second voltage commands, which is given above
in Equation (36), the amplitude V_sum of the sum voltage, which is given above in
Equation (37), or a combination of V1, V2, and V_sum may be used instead. Moreover,
the gains may be switched in accordance with effective values rather than the amplitude
of the first voltage commands, the second voltage commands, or the sum voltage.
[0202] Furthermore, similar effects are obtained with a configuration in which the abscissae
of Figs. 29 and 30 are set as the rotation speed of the AC rotary machine 1a such
that the sum current gains and differential current gains are set at fixed values
at or below a predetermined threshold relating to the speed and reduced in accordance
with the speed above the predetermined threshold.
Tenth Embodiment
[0203] Fig. 31 is a view showing an overall configuration of a control apparatus for an
AC rotary machine according to a tenth embodiment of this invention. A configuration
of the tenth embodiment differs from the ninth embodiment in that the first current
detection unit 4a is replaced with the first current detection unit 4c and the second
current detection unit 4b is replaced with the second current detection unit 4d. Accordingly,
the following description centers on these differences.
[0204] In the configuration of the ninth embodiment, shown in Fig. 28, the first current
detection unit 4a and the second current detection unit 4b are used. Therefore, as
shown in Fig. 12, the first current detection unit 4a is unable to detect the currents
of the first windings in the vicinity of a voltage phase angle θv of 60 × x (x: 0,
1, 2, 3, 4, 5) degrees, and the second current detection unit 4b is unable to detect
the currents of the second windings in the vicinity of a voltage phase angle θv of
30 + 60 × x (x: 0, 1, 2, 3, 4, 5) degrees.
[0205] In the tenth embodiment, however, the first current detection unit 4c and the second
current detection unit 4d are used. Therefore, as shown in Fig. 21, the first current
detection unit 4c becomes unable to detect the currents of the first windings in the
vicinity of a voltage phase angle θv of 60 + 120 × x (x: 0, 1, 2) degrees, and the
second current detection unit 4d becomes unable to detect the currents of the second
windings in the vicinity of a voltage phase angle θv of 90 + 120 × x (x: 0, 1, 2)
degrees. As a result, in the tenth embodiment, a voltage phase interval in which one
of the first and second current detection units is unable to perform current detection
can be reduced in comparison with the ninth embodiment.
[0206] Accordingly, a period in which the currents of the first windings and the currents
of the second windings are both detectable is increased. As a result, a period in
which the voltage commands Vd1, Vq1 of the first windings are calculated in consideration
of the currents of the second windings, detected by the second current detection unit,
in addition to the currents of the first windings, detected by the first current detection
unit, is increased. Similarly, a period in which the second voltage commands Vd2,
Vq2 are calculated in consideration of the currents of the first windings, detected
by the first current detection unit, in addition to the currents of the second windings,
detected by the second current detection unit, is increased. Therefore, an even more
stable control system than that of the ninth embodiment can be constructed with respect
to magnetic interference between the first windings and the second windings.
[0207] Note that in the first to tenth embodiments described above, an AC rotary machine
including a first winding and a second winding was subjected to control. This invention
is not limited to an AC rotary machine of this type, however, and the control method
of this invention may be applied as is to an AC rotary machine having an Nth (where
N is an integer no smaller than 3) winding indicating a third winding or more windings
by substituting the first winding and the second to Nth windings respectively for
the first and second windings described in the first to tenth embodiments.
[0208] Further, in the first to tenth embodiments described above, an AC rotary machine
including first three-phase windings and second three-phase windings having a 30 degree
phase difference was subjected to control. This invention is not limited to an AC
rotary machine of this type, however, and by providing phase differences between the
first voltage commands Vu1', Vv1', Vw1' and the second voltage commands Vu2', Vv2',
Vw2', the control method of this invention may be applied to an AC rotary machine
including first three-phase windings and second three-phase windings having a phase
difference of 30 + 60 × N (where N is an integer) degrees or an AC rotary machine
including first three-phase windings and second three-phase windings not having a
phase difference.
[0209] For example, when the phase difference is 30 degrees, the first voltage commands
Vu1' Vv1' Vw1' and the second voltage commands Vu2', Vv2', Vw2' are similar to Fig.
12. As a result, the first detectability determination signal flag_1 and the second
detectability determination signal flag_2 do not switch to 0 simultaneously, and therefore
the control method of this invention can be applied.
[0210] Furthermore, the control apparatus for an AC rotary machine described in the first
to tenth embodiments may be applied to control of an electric power steering having
a control apparatus for an AC rotary machine. An electric power steering apparatus
requires a control unit that calculates a first voltage command and a second voltage
command to ensure that the AC rotary machine generates torque for assisting steering
torque of a steering system.
[0211] By applying the control apparatus for an AC rotary machine according to this invention
as a control unit for an electric power steering, the first voltage command and the
second voltage command can be calculated at a high amplitude while maintaining a switching
period Tsw. As a result, a steering system in which the switching frequency, which
is given by the inverse of the switching period, is removed from the audible range
such that increased output is obtained at an identical volume ratio while maintaining
low noise can be constructed. In other words, the apparatus can be reduced in size
while obtaining an identical output ratio, and therefore a steering system that is
easy to install can be realized.