(19)
(11) EP 3 264 706 A3

(12) EUROPEAN PATENT APPLICATION

(88) Date of publication A3:
18.04.2018 Bulletin 2018/16

(43) Date of publication A2:
03.01.2018 Bulletin 2018/01

(21) Application number: 17177264.3

(22) Date of filing: 21.06.2017
(51) International Patent Classification (IPC): 
H04L 27/36(2006.01)
H04B 1/40(2015.01)
 G05F 1/613(2006.01)
(84) Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated Extension States:
BA ME
Designated Validation States:
MA MD

(30) Priority: 01.07.2016 US 201615200495

(71) Applicant: Intel IP Corporation
Santa Clara, CA 95054 (US)

(72) Inventors:
  • SIEVERT, Sebastian
    81539 Munich (DE)
  • DEGANI, Ofir
    Nes-Ammin, 22801 (IL)
  • GORDON, Eshel
    3600500 Aloney Aba, HA (IL)

(74) Representative: 2SPL Patentanwälte PartG mbB 
Postfach 15 17 23
80050 München
80050 München (DE)

   


(54) LOW DROP OUT COMPENSATION TECHNIQUE FOR REDUCED DYNAMIC ERRORS IN DIGITAL-TO-TIME CONVERTERS


(57) An apparatus comprises a radio frequency (RF) transceiver circuit; a phase modulator that comprises digital-to-time converter (DTC) circuitry configured to convert a digital value to a specified signal phase of a signal transmitted by the RF transceiver circuit; low drop out regulator (LDO) circuitry operatively coupled to the DTC circuitry, wherein a bias current of the LDO circuitry is adjustable; and logic circuitry operatively coupled to the LDO circuitry and DTC circuitry, wherein the logic circuitry is configured to set the adjustable bias current of the LDO circuitry according to a digital value input to the DTC circuitry.







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