SYSTEMS AND METHODS FOR REDUCING ARTIFACTS AND IMPROVING PERFORMANCE OF A MULTI-PATH ANALOG-TO-DIGITAL CONVERTER - Patent 3308468

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EP 3 308 468 A1

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(43)	Date of publication:
	18.04.2018 Bulletin 2018/16

(21)	Application number: 16729230.9

(22)	Date of filing: 07.06.2016

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International Patent Classification (IPC):

H03M 1/18^(2006.01)

H04R 3/00^(2006.01)

(86)	International application number:
	PCT/EP2016/062862

(87)	International publication number:
	WO 2016/202636 (22.12.2016 Gazette 2016/51)

(84)	Designated Contracting States:
	AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
	Designated Extension States:
	BA ME
	Designated Validation States:
	MA MD

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Priority:

15.06.2015 US 201514739289

(71)	Applicant: Cirrus Logic International Semiconductor Ltd.
	Edinburgh EH3 9EG (GB)

(72)	Inventors:
	SATOSKAR, Aniruddha Austin, Texas 78728 (US) ALLEN, Daniel Austin, Texas 78704 (US) SCHNEIDER, Edmund Austin, Texas 78739 (US)

(74)	Representative: Haseltine Lake LLP
	Redcliff Quay 120 Redcliff Street Bristol BS1 6HU Bristol BS1 6HU (GB)

(54)	SYSTEMS AND METHODS FOR REDUCING ARTIFACTS AND IMPROVING PERFORMANCE OF A MULTI-PATH ANALOG-TO-DIGITAL CONVERTER