TECHNICAL FIELD
[0001] The present disclosure relates to the field of electronics, and in particular, to
a linear regulator.
BACKGROUND
[0002] A linear regulator is also referred to as a series regulator. A linear regulator
can be used to convert an unstable input voltage into an adjustable direct output
voltage so as to provide a power source to another system. A linear regulator has
a simple structure, less static power consumption, and a small output voltage ripple
etc. As a result, the linear regulator is generally used for the intra-chip power
source management of a chip in a consumer mobile electronic device.
[0003] Fig. 1 is a schematic structural diagram of a linear regulator in the related art.
The linear regulator includes: a bias module 1, a reference voltage module 2, an error
amplifier 3, a power transistor 4, and a sampling resistor network 5.
[0004] An input voltage V
IN of the linear regulator is input into the bias module 1, the reference voltage module
2, and the power transistor 4, respectively. The bias module 1 provides a current
bias and a voltage bias to the reference voltage module 2 and the error amplifier
3 for a normal operation of the reference voltage module 2 and the error amplifier
3. The reference voltage module 2 generates a reference voltage V
REF with a low temperature drift for the error amplifier 3. The error amplifier 3 amplifies
an error between V
REF and a feedback voltage V
FB that is obtained by sampling an output voltage V
O by a sampling resistor network 5, so as to regulate a gate voltage of the power transistor
4 according to an error amplification result and to stabilize an output of the output
voltage Vo.
[0005] With fast development of technologies in the Internet of Things, people have higher
requirements on mobile consumer electronic devices. When a system of an electronic
device is in a sleeping standby state, power consumption of intra-chip power source
management of an electronic device chip should be as low as possible, so as to achieve
a longer device operation time and a relatively long electronic device standby time.
However, a linear regulator in the related art may be difficult to satisfy a requirement
that a static current is in the range of hundreds of nanoamperes or even dozens of
nanoamperes when the electronic device is in a standby state. In addition, the sampling
resistor network 5 in the linear regulator of related art occupies a relatively large
chip area, which is disadvantageous to the development of miniaturizing an electronic
device.
SUMMARY
[0006] One of the objectives of the embodiments of the present disclosure is to provide
a linear regulator with relatively low static power consumption and a relatively small
area on a chip. Also, due to the fact that a voltage bias module with positive temperature
characteristics compensates negative temperature characteristics of a flip voltage
follower, an output voltage of the linear regulator can have good temperature characteristics
even when the linear regulator does not have a reference voltage module.
[0007] To solve the above technical problem, an embodiment the present disclosure provides
a linear regulator including a current bias module, a voltage bias module having positive
temperature characteristics, and a flip voltage follower.
[0008] An input end of the current bias module receives an input voltage of the linear regulator,
and an output end of the current bias module outputs a bias current.
[0009] A first input end and a second input end of the voltage bias module receive the input
voltage and the bias current respectively, and an output end of the voltage bias module
outputs a bias voltage.
[0010] A first input end and a second input end of the flip voltage follower receive the
input voltage and the bias voltage respectively, and an output end of the flip voltage
follower outputs an output voltage of the linear regulator.
[0011] In the embodiment of the present disclosure, as compared with the existing technologies,
the input voltage of the linear regulator is input to the input end of the current
bias module. In the first input end of the voltage bias module and the first input
end of the flip voltage follower, the current bias module generates the bias current,
and the second input end of the voltage bias module receives the bias current. The
voltage bias module generates the bias voltage, and the second input end of the flip
voltage follower receives the bias voltage. The output voltage of the linear regulator
is output by the output end of the flip voltage follower. The flip voltage follower
is provided to follow and compensate the output voltage of the linear regulator, so
that the output voltage of the linear regulator is relatively stable. In addition,
the voltage bias module has the positive temperature characteristics and can mutually
compensate with the flip voltage follower, to offset negative temperature characteristics
of the flip voltage follower, so that the output voltage of the linear regulator has
good temperature characteristics. In this way, the linear regulator has characteristics
of relatively low static power consumption and a relatively small chip occupation
area. Also, the output voltage of the linear regulator can achieve good temperature
characteristics without a need of specifically setting a reference voltage module.
[0012] In addition, the current bias module includes a bias current generation circuit and
an auxiliary output circuit. An input end of the bias current generation circuit is
connected to the input voltage of the linear regulator. An output end of the bias
current generation circuit is connected to an input end of the auxiliary output circuit.
An output end of the auxiliary output circuit is connected to the input end of the
voltage bias module. The input end of the bias current generation circuit and the
output end of the auxiliary output circuit respectively form the input end and the
output end of the current bias module. A required bias current (generally, the required
bias current is a nanoampere-level bias current) is generated by using the bias current
generation circuit, and the bias current of the bias current generation circuit is
output to the voltage bias module by using the auxiliary output circuit.
[0013] In addition, the auxiliary output circuit includes a current mirror circuit and a
field effect transistor, where an input end of the current mirror circuit is connected
to the output end of the bias current generation circuit, and an output end of the
current mirror circuit is connected to a drain of the field effect transistor; and
a source and a gate of the field effect transistor are connected to the input end
and the output end of the current bias module respectively. This embodiment provides
a specific example of the auxiliary output circuit, that is, the bias current in the
bias current generation circuit is copied to the drain of the field effect transistor
by using the current mirror circuit, so that the field effect transistor inputs the
bias current to the voltage bias module. In addition, by using the auxiliary output
circuit including the current mirror circuit, there is a relatively large flexibility
in the circuit design of such a bias current generation circuit.
[0014] In addition, the auxiliary output circuit includes a field effect transistor, where
a drain and a gate of the field effect transistor form the input end and the output
end of the auxiliary output circuit respectively. This embodiment provides a specific
example of the auxiliary output circuit in respect of feasibility of the present disclosure.
[0015] In addition, the voltage bias module includes a series self-cascode MOSFET (SSCM)
circuit, which provides a specific implementation manner of the voltage bias module,
thereby increasing feasibility of the present disclosure. In addition, in the present
disclosure, as the SSCM circuit can work in a sub-threshold region, static power consumption
of the linear regulator can be very small.
[0016] In addition, the flip voltage follower includes a folded cascode amplifier and a
power transistor; a first input end of the folded cascode amplifier and an emitter
of the power transistor form the first input end of the flip voltage follower; a second
input end of the folded cascode amplifier forms the second input end of the flip voltage
follower; a first output end of the folded cascode amplifier is connected to a gate
of the power transistor; and a second output end of the folded cascode amplifier forms
the output end of the flip voltage follower and is connected to a drain of the power
transistor. As the folded cascode amplifier samples an output voltage of the linear
regulator and amplifies an error of the output voltage, and a result of the error
method is output to the gate of the power transistor, a gate voltage of the power
transistor can be regulated to stabilize the output voltage of the linear regulator.
[0017] In addition, the flip voltage follower further includes an output capacitor. The
output capacitor is placed between an output end and a ground end of the flip voltage
follower. The output capacitor is used to stabilize the linear regulator.
BRIEF DESCRIPTION OF THE DRAWINGS
[0018]
Fig. 1 is a schematic structural diagram of a linear regulator in the related art;
Fig. 2 is a schematic structural diagram of a linear regulator according to a first
embodiment of the present disclosure;
Fig. 3 is a schematic circuit diagram of a linear regulator according to the first
embodiment of the present disclosure;
Fig. 4 is a schematic circuit diagram of a nanoampere-level bias current generation
circuit according to the first embodiment of the present disclosure; and
Fig. 5 is a schematic circuit diagram of a linear regulator according to a second
embodiment of the present disclosure.
DETAILED DESCRIPTION
[0019] To make the objectives, technical solutions, and advantages of the present disclosure
clearer, the following describes the details of various embodiments of the present
disclosure with reference to the accompanying drawings. However, a person skilled
in the art can understand that in the embodiments of the present disclosure, many
technical details are provided to make the readers to better understand this application.
However, even if such technical details and various changes and modifications that
are based on the following embodiments are not provided, the technical solutions of
this application can also be achieved.
[0020] A first embodiment of the present disclosure relates to a linear regulator. As shown
in Fig. 2, the linear regulator includes a current bias module, a voltage bias module
having positive temperature characteristics, and a flip voltage follower. The linear
regulator in this embodiment may be applied to mobile terminals having rechargeable
cells, such as a mobile phone, a computer, a tablet computer, and a wearable device.
[0021] An input end of the current bias module 6 receives an input voltage V
IN of the linear regulator, and an output end of the current bias module 6 outputs a
bias current. A first input end and a second input end of the voltage bias module
7 respectively receives the input voltage V
IN and the bias current, and an output end of the voltage bias module 7 outputs a bias
voltage. A first input end and a second input end of the flip voltage follower 8 respectively
receives the input voltage V
IN and the bias voltage, and an output end of the flip voltage follower 8 outputs an
output voltage Vo of the linear regulator.
[0022] Specifically, the current bias module 6 generates the bias current and outputs the
bias current to the voltage bias module 7, and the voltage bias module 7 generates
the bias voltage. The flip voltage follower 8 is configured to follow and compensate
the output voltage Vo of the linear regulator, so that the output voltage Vo of the
linear regulator is relatively stable. In addition, the voltage bias module 7 has
the positive temperature characteristics and can mutually compensate with the flip
voltage follower 8, thus to offset negative temperature characteristics of the flip
voltage follower 8, so that the output voltage V
O of the linear regulator may have good temperature characteristics.
[0023] In this embodiment, the current bias module 6 includes a bias current generation
circuit and an auxiliary output circuit. An input end of the bias current generation
circuit is connected to the input voltage V
IN of the linear regulator; and an output end of the bias current generation circuit
is connected to an input end of the auxiliary output circuit. An output end of the
auxiliary output circuit is connected to the input end of the voltage bias module
7. The input end of the bias current generation circuit and the output end of the
auxiliary output circuit respectively form the input end and the output end of the
current bias module. A required bias current (generally, the required bias current
is a nanoampere-level bias current) can be generated by using the bias current generation
circuit, and the bias current of the bias current generation circuit is output to
the voltage bias module by using the auxiliary output circuit.
[0024] The auxiliary output circuit includes a current mirror circuit and a field effect
transistor. An input end of the current mirror circuit is connected to the output
end of the bias current generation circuit, and an output end of the current mirror
circuit is connected to a drain of the field effect transistor. A source and a gate
of the field effect transistor are respectively connected to the input end and the
output end of the current bias module. The bias current in the bias current generation
circuit is copied to the drain of the field effect transistor by using the current
mirror circuit, so that the field effect transistor inputs the bias current to the
voltage bias module. In addition, by using the auxiliary output circuit with the current
mirror circuit, there is a relative flexibility in selecting a model of the bias current
generation circuit.
[0025] A working principle of the linear regulator may be described below by reference to
a circuit shown in Fig. 3.
[0026] The current bias module 6 includes a bias current generation circuit and an auxiliary
output circuit. The bias current generation circuit may be a nanoampere-level bias
current generation circuit shown in Fig. 3. The auxiliary output circuit includes
a current mirror circuit and a field effect transistor M
2. The current mirror circuit may include field effect transistors M
1 and M
3, a drain of the field effect transistor M
1 is used as the input end of the current mirror circuit, and a drain of the field
effect transistor M
3 is used as the output end of the current mirror circuit. Fig. 4 refers to an embodiment
of a specific circuit of the nanoampere-level bias current generation circuit. As
shown in Fig. 4, sources of field effect transistors Mg, M
11, M
13, and M
15 are used as input ends of the nanoampere-level bias current generation circuit, a
drain of the field effect transistor M
15 is used as an output end of the nanoampere-level bias current generation circuit.
[0027] N, J, and K in Fig. 4 represent mirror ratios of current mirror circuits. N is a
mirror ratio of a current mirror circuit including transistors M
11 and Mg. J is a mirror ratio of a current mirror circuit including transistors M
14 and M
12. K is a mirror ratio of a current mirror circuit including transistors M
11 and M
13. M
9 and M
10 construct a self-cascode transistor (SCM) circuit.
[0028] Transistors Mg to M
14 are main circuits of the nanoampere-level bias current generation circuit, and M
15 is a bias current output end of the nanoampere-level bias current generation circuit.
[0029] Because the current mirror circuit including the M
14 and M
12 works in the sub-threshold region, and the mirror ratio is greater than 1 (J>1),
thus gate-source voltages V
GS of M
12 and M
14 are different, and V
GS14>V
GS12. A source of M
12 generates a voltage, and the voltage is a difference between V
GS14 and V
GS12.
[0030] For the SCM circuit with M
9 and M
10, M
10 works in a linear region, and may be equivalent to a resistor in electrical characteristics.
In addition, because the drain of M
10 is biased by a source voltage of M
12, a generated output current is equal to a ratio of the source voltage of M
12 to an equivalent resistor of M
10.
[0031] Because a difference between V
GS14 and V
GS12 is relatively small and is only dozens of millivolts, and the equivalent resistor
of M
10 is a transistor resistor, in an actual operation, M
10 may be designed into an inverted transistor and a very large equivalent resistance
can be obtained accordingly, so as to obtain output of the nanoampere-level bias current.
[0032] In conclusion, the nanoampere-level bias current generation circuit mentioned in
this embodiment has features of a small output bias current, low static power consumption,
and a small chip occupation area.
[0033] The input end of the nanoampere-level bias current generation circuit or the source
of the field effect transistor M
2 is used as the input end of the current bias module 6 and receive the input voltage
V
IN of the linear regulator. The gate of the field effect transistor M
2 is used as the output end of the current bias module 6 and is connected to the input
end of the voltage bias module 7. The output end of the nanoampere-level bias current
generation circuit is connected to the drain of the field effect transistor M
1. The gate of the field effect transistor M
1 is connected to the drain of the transistor M1, and is also connected to the gate
of the field effect transistor M
3. The drain of the field effect transistor M
3 is connected to the drain of the field effect transistor M
2. The source of the field effect transistor M
1 and the source of the field effect transistor M
3 are both grounded.
[0034] The voltage bias module 7 with positive temperature characteristics can be a series
self-cascode MOSFET (SSCM) circuit, and a number of stages of the SSCM circuit can
be three. The SSCM circuit may include field effect transistors M
B1 to M
B4, M
U1 to M
U3, and M
D1 to M
D3 shown in Fig. 3. In this embodiment, the number of stages of the SSCM circuit is
not limited, and may be selected according to various requirements for an amount of
compensation and for the output voltages Vo. In addition, it should be noted that
a specific structural form of the voltage bias module is not limited in this embodiment.
Any structural form of the voltage bias module having the positive temperature characteristics
can be applied to this embodiment.
[0035] Specifically, the field effect transistors M
B1, M
U1, and M
D1 shown in Fig. 3 may form a first stage circuit of the SSCM circuit, M
B2, M
U2, and M
D2 may form a second stage circuit of the SSCM circuit, and M
B3, M
U3, and M
D3 may form a third stage circuit of the SSCM circuit. Circuits of various stages in
the SSCM circuit are described in details below.
A first stage circuit of the SSCM circuit:
[0036] A source of a transistor M
B1 receives the input voltage V
IN of the linear regulator, a gate of the transistor M
B1 is connected to the gate of the field effect transistor M
2, and a drain of the transistor M
B1 is connected to a drain of a transistor M
U1. A gate and the drain of the transistor M
U1 are connected to each other, and a source of the transistor M
U1 is connected to a drain of the transistor M
D1. A gate of the transistor M
D1 is connected to the gate of the transistor M
U1, and a source of the transistor M
U1 is grounded. The drain of the transistor M
D1 is connected to the source of the transistor M
U1 and is used as an output end of the first stage of the SSCM circuit, and an output
voltage is V
SSCM1.
[0037] Accordingly, V
SSCM1= V
GS_MD1-V
GS_MU1, V
GS_MD1 is a gate-source voltage of the transistor M
D1, and V
GS_MU1 is a gate-source voltage of the transistor M
U1. A current amplification coefficient of M
B1 is k
1, so that a bias current I
0 generated by the nanoampere-level bias current generation circuit can be amplified
to k
1*I
0 after passing through the transistor M
B1.
A second stage circuit of the SSCM circuit:
[0038] A source of a transistor M
B2 receives the input voltage V
IN of the linear regulator, a gate of the transistor M
B2 is connected to the gate of the field effect transistor M
2, and a drain of the transistor M
B2 is connected to a drain of the transistor M
U2. A gate and the drain of the transistor M
U2 are connected to each other, and a source of the transistor M
U2 is connected to a drain of the transistor M
D2. A gate of the transistor M
D2 is connected to the gate of the transistor M
U2, and a source of the transistor is grounded. The drain of the transistor M
D2 is connected to the source of the transistor M
U2 and is used as an output end of the second stage of the SSCM circuit, and an output
voltage is V
SSCM2.
[0039] Accordingly, V
SSCM2= V
GS_MD2-V
GS_MU2, V
GS_MD2 is a gate-source voltage of the transistor M
D2, and V
GS_MU2 is a gate-source voltage of the transistor M
U2. A current amplification coefficient of the transistor M
B2 is k
2, so that a bias current I
0 generated by the nanoampere-level bias current generation circuit may be amplified
to k
2*I
0 after passing through the transistor M
B2.
A third stage circuit of the SSCM circuit:
[0040] A source of a transistor M
B3 receives the input voltage V
IN of the linear regulator, a gate of the transistor M
B3 is connected to the gate of the field effect transistor M
2, and a drain of the transistor M
B3 is connected to a drain of the transistor M
U3. A gate and the drain of the transistor M
U3 are connected to each other, and a source of the transistor M
U3 is connected to a drain of the transistor M
D3. A gate of the transistor M
D3 is connected to the gate of the transistor M
U3, and a source of the transistor is grounded. The drain of the transistor M
D3 is connected to the source of the transistor M
U3 and is used as an output end of the third stage of the SSCM circuit, and an output
voltage is V
SSCM3.
[0041] Accordingly, V
SSCM3= V
GS_MD3-V
GS_MU3, V
GS_MD3 is a gate-source voltage of the transistor M
D3, and V
GS_MU3 is a gate-source voltage of the transistor M
U3. A current amplification coefficient of M
B3 is k
3, so that a bias current I
0 generated by the nanoampere-level bias current generation circuit may be amplified
to k
3*I
0 after passing through the transistor M
B3.
[0042] The flip voltage follower 8 may include a folded cascode amplifier and a power transistor
Mp. The folded cascode amplifier may include field effect transistors M
4 to M
7. A source of the field effect transistor M
4 is a first input end of the folded cascode amplifier and forms the first input end
of the flip voltage follower 8 together with an emitter of the power transistor Mp.
A gate of the field effect transistor M
5 is a second input end of the folded cascode amplifier and forms the second input
end of the flip voltage follower 8. A drain of the field effect transistor M
4 is a first output end of the folded cascode amplifier and is connected to a gate
of the power transistor M
P. A source of the field effect transistor M
7 is a second input end of the folded cascode amplifier, forms the output end of the
flip voltage follower 8, and is connected to a drain of the power transistor Mp.
[0043] Specifically, the nanoampere-level bias current generation circuit generates the
bias current I
0. I
0 is output to the SSCM circuit after being converted by the current mirror circuit.
The SSCM circuit output voltages V
B and V
PTAT respectively acting on the gate of the field effect transistor M
5 and the gate of the field effect transistor M
7. When the input voltage V
IN of the linear regulator powers up and a circuit stably works, the output voltage
of the linear regulator is V
O=V
PTAT+V
GS7. V
GS7=V
TH+V
OVM7, V
TH is a threshold voltage of the field effect transistor M
7, V
OVM7 is an overdrive voltage of the field effect transistor M
7, and when the field effect transistor M
7 works in a sub-threshold region, V
OVM7 may be omitted.
[0044] The source of the field effect transistor M
7 samples the output voltage Vo of the linear regulator, then the folded cascode amplifier
including the field effect transistors M
4 to M
7 performs an error amplification, and a result of the error amplification is output
at a node Y and acts on the gate of the power transistor Mp. The field effect transistor
M
4 and the field effect transistor M
6 provide bias currents I
B1 and I
B2 to the folded cascode amplifier respectively, and I
B2>I
B1. V
B is biased at the gate of the field effect transistor M
5 so that a node X has a proper bias voltage, to ensure that the field effect transistor
M
6 and the field effect transistor M
7 both work at a proper working voltage.
[0045] Because the input voltage V
IN of the linear regulator remains the same, if the output voltage V
O of the linear regulator increases, a voltage V
O-V
IN on the folded cascode amplifier also increases. In this way, a voltage on the Y node
increases, so that the power transistor Mp is closed, and the output voltage V
O of the linear regulator decreases. Otherwise, if the output voltage Vo of the linear
regulator decreases, the voltage V
O-V
IN on the folded cascode amplifier decreases, and the voltage on the Y node also decreases.
In this case, the power transistor Mp increases a supply current, so that the output
voltage V
O of the linear regulator increases.
[0046] It should be noted that in this embodiment, the flip voltage follower 8 may further
include an output capacitor C
0. The output capacitor C
0 is connected between the output end and a ground end of the flip voltage follower
8. Stability of the linear regulator may be enhanced by using the output capacitor
C
0.
[0047] A principle of mutual compensation of the voltage bias module 7 and the flip voltage
follower 8 can be described below.
[0048] It can be known from the above descriptions that V
O=V
PTAT+V
GS7. Because the flip voltage follower 8 has negative temperature characteristics, the
SSCM circuit needs to be reasonably designed, so that the SSCM circuit has proper
positive temperature characteristics, such that the output voltage Vo of the linear
regulator has good accuracy within a full temperature range. That is, V
PTAT in the SSCM circuit needs to be made to have proper positive temperature characteristics,
so that V
PTAT can compensate negative temperature characteristics of the flip voltage follower
8.
[0049] In this embodiment, a number of stages of the SSCM circuit is three, and output of
an ith stage of the SSCM circuit is V
SSCMi=V
GS_MDi-V
GS_MUi. Because the SSCM circuit works in the sub-threshold region, an output of each stage
of the SSCM circuit is obtained according to a current-voltage formula of the sub-threshold
region:

where n is a sub-threshold slope coefficient, V
T is a thermal voltage, I
S0 is a process-related parameter, and S
MDi and S
MUi respectively represent channel width-length ratios of the transistor M
Di and the transistor M
Ui.
[0050] When formula (1) is incorporated with Fig. 3, a formula (2) can be obtained as:

[0051] A known threshold voltage of the field effect transistor may be represented as the
following formula (3):

[0052] T is an absolute temperature, T
0 is a reference absolute temperature (such as a room temperature), and α
VT is a temperature coefficient of the threshold voltage of the field effect transistor.
[0053] Assuming that the field effect transistor M
7 also works in the sub-threshold region, the output voltage V
O may be obtained as the following formula (4) by combining formula (2) and formula
(3):

[0054] It can be seen that when the quantity of stages of the SSCM circuit is N, formula
(4) can be expanded as:

When the output voltage Vo is derived with respect to the temperature, the following
can be obtained:

and formula (7):

where k
b is a Boltzmann constant, and q is a potential-charge constant.
[0055] It can be known from formula (6) and formula (7) that when the quantity of stages
of SSCM, a current amplification coefficient k
i (i=1, 2, ..., N, N+1), sizes of M
Ui and M
Di(i=1, 2, ..., N), and a size of the field effect transistor M
7 are properly designed so that

can be achieved, thus the output voltage Vo can have a zero temperature characteristic.
[0056] It can be seen that in this embodiment, the flip voltage follower 8 is provided to
follow and compensate the output voltage of the linear regulator, so that the output
voltage of the linear regulator is relatively stable. In addition, the voltage bias
module 7 has the positive temperature characteristics and can mutually compensate
with the flip voltage follower 8, to offset negative temperature characteristics of
the flip voltage follower 8, so that the output voltage of the linear regulator has
good temperature characteristics. In this way, the linear regulator does not require
specifically setting a reference voltage module, which saves current consumption and
which results a linear regulator with characteristics of relatively low static power
consumption and a relatively small area on a chip.
[0057] A second embodiment of the present disclosure relates to a linear regulator, as shown
in FIG. 5. The second embodiment and the first embodiment are substantially the same
and mainly differ in that: in the first embodiment of the present disclosure, the
auxiliary output circuit includes a current mirror circuit and a field effect transistor.
In the second embodiment of the present disclosure, the auxiliary output circuit includes
only a field effect transistor M
16.
[0058] Specifically, a drain and a gate of the field effect transistor M
16 respectively form the input end and the output end of the auxiliary output circuit.
The drain of the field effect transistor M
16 is connected to the input end of the nanoampere-level bias current generation circuit,
and the gate is connected to the gate of the field effect transistor M
6 of the folded cascode amplifier. A source of M
16 is grounded, and a gate is further connected to the drain of M
16.
[0059] In this embodiment, there is no need to connect the field effect transistor M
16 to the SSCM circuit, and a function of the field effect transistor M
16 is to receive a bias current and provide the bias current to the flip voltage follower
8.
[0060] A person of ordinary skill in the art can understand that the above embodiments are
specific examples of the present disclosure. However, in an actual application, various
changes or modification can be made to the forms and details of these specific examples
without departing from the spirit and the scope of the present disclosure.