SEMICONDUCTOR STRUCTURE AND ETCH TECHNIQUE FOR MONOLITHIC INTEGRATION OF III-N TRANSISTORS - Patent 3440704

(19)

(11)

EP 3 440 704 A1

(12)

(43)	Date of publication:
	13.02.2019 Bulletin 2019/07

(21)	Application number: 17779582.0

(22)	Date of filing: 03.04.2017

(51)

International Patent Classification (IPC):

H01L 29/66^(2006.01)
H01L 21/336^(2006.01)

H01L 27/088^(2006.01)

(86)	International application number:
	PCT/US2017/025685

(87)	International publication number:
	WO 2017/176612 (12.10.2017 Gazette 2017/41)

(84)	Designated Contracting States:
	AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
	Designated Extension States:
	BA ME
	Designated Validation States:
	MA MD

(30)

Priority:

08.04.2016 US 201615094985

(71)	Applicant: Cambridge Electronics, Inc.
	Cambridge, MA 02142 (US)

(72)	Inventors:
	XIA, Ling Belmont MA 02478 (US) AZIZE, Mohamed Medford MA 02155 (US) LU, Bin Watertown MA 02472 (US)

(74)	Representative: FRKelly
	27 Clyde Road Dublin D04 F838 Dublin D04 F838 (IE)

(54)	SEMICONDUCTOR STRUCTURE AND ETCH TECHNIQUE FOR MONOLITHIC INTEGRATION OF III-N TRANSISTORS