A PULSE WIDTH MODULATION CIRCUIT, CORRESPONDING DEVICE AND METHOD

Description

Technical field

[0001] The description relates to circuits involving pulse width modulation (PWM).

[0002] One or more embodiments may be applied to switching (e.g. Class D) amplifiers.

Technological background

[0003] A demand exists in certain application areas (e.g. the automotive market) for switching amplifiers such as class D audio amplifiers with operating frequencies increased from current values such as 350 kHz towards higher values e.g. 2.2-2.4 MHz.

[0004] Higher operating frequencies may facilitate providing smaller systems with improved electro magnetic interference (EMI) spectrum emission characteristics.

[0005] Current 350 kHz class D power audio amplifiers may comprise a pulse skipping control block to increase output power. Document US 9 595 946 B2 is exemplary of such a solution. Certain arrangements may also comprise a pulse skipping inhibition block in order to contain the EMI spectrum around known frequencies, at the expense of a reduction in output power.

[0006] In this context, also document US 2007/0024365 A1 is exemplary of the prior art.

[0007] Conventional (analog) circuits are hardly able to meet the requirements related to (much) higher switching frequencies for class D amplifiers - e.g. about seven times higher, if one considers the exemplary figures mentioned previously.

Object and summary

[0008] An object of one or more embodiments is to contribute in meeting such requirements.

[0009] According to one or more embodiments, that object can be achieved by means of a circuit having the features set forth in the claims that follow.

[0010] One or more embodiments relate to a corresponding device. A switching (e.g. class D) amplifier may be exemplary of such a device.

[0011] One or more embodiments relate to a corresponding method.

[0012] The claims are an integral part of the technical disclosure of the invention as provided herein.

[0013] One or more embodiments rely on a structure mixing analog features with essentially digital structure in order to address issues related e.g. to limitations in the slew rate of certain analog circuits such as operational amplifiers (op-amps).

[0014] In addition to providing improved performance, one or more embodiments facilitate the adoption of a simple and compact structure.

[0015] One or more embodiments provide both pulse skipping control and pulse skipping inhibit functions within a single circuit, e.g. by simply switching between different reference voltages.

[0016] One or more embodiments make it possible to generate a carrier waveform for a PWM modulator which facilitates a good, controlled near-clipping behavior also in systems operating with a high clock frequencies (e.g. in excess of 2 MHz) with timing precision and robustness in respect of temperature and process variations.

[0017] One or more embodiments rely on simple threshold variations to obtain with a same circuit accurate pulse skipping inhibit. This facilitates achieving controlled EMI characteristics in the PWM spectrum. In one or more embodiments that result is obtained while avoiding additional circuits and facilitating high accuracy with high clock frequencies.

[0018] One or more embodiments are adapted for use in high-quality, high-frequency class D audio systems with the capability of facilitating good clipping behavior and, if desired, control of EMI emissions in operating conditions.

[0019] In one or more embodiments according to the invention, a circuit comprises:

• a first circuit block configured for receiving a square wave input signal having rising and falling edges and producing from the square wave input signal a triangular wave signal
• a second circuit block configured for receiving a modulating signal and producing a PWM modulated signal by comparing the modulating signal with a carrier signal
• a switching circuit block active between the first circuit block and the second circuit block, wherein the switching circuit block includes reference inputs configured for receiving reference signals having upper and lower reference values and is selectively switchable between:
• a carrier transfer setting wherein the switching circuit block couples the first circuit block to the second circuit block to transfer thereto the triangular wave signal as the carrier signal,
• at least one carrier forcing setting wherein the switching circuit block applies to the second circuit block said reference signals by forcing the carrier signal to said upper and lower reference values, respectively.

[0020] In one or more embodiments:

• the second circuit block is configured for receiving the modulating signal having a modulating signal swing between highest and lowest modulating signal values,
• the switching circuit block:
  i) includes reference inputs configured for receiving reference signals having first upper and first lower reference values lying within the modulating signal swing as well as second upper and second lower reference values lying outside the modulating signal swing,

  ii) is selectively switchable between:

  • a first carrier forcing setting, wherein the switching circuit block applies to the second circuit block said reference signals with said first upper and first lower reference values,
  • a second carrier forcing setting, wherein the switching circuit block applies to the second circuit block said reference signals with said second upper and second lower reference values.

[0021] In one or more embodiments:

• the second circuit block is configured for producing the PWM modulated signal with a lowest value for the PWM duty cycle wherein the PWM modulated signal has a lowest pulse active time at the selected lowest value for the duty cycle,
• the switching circuit block is selectively switchable to the at least one carrier forcing setting over carrier forcing intervals equal to said lowest pulse active time.

[0022] One or more embodiments comprising a clock circuit block sensitive to the rising and falling edges of the square wave input signal, the clock circuit block may be configured for driving the switching circuit block to switch between the carrier transfer setting and the at least one carrier forcing setting at the rising and falling edges of the square wave input signal.

[0023] In one or more embodiments, the clock circuit block is configured for driving the switching circuit block to switch to the at least one carrier forcing setting over carrier forcing intervals centered around the rising and falling edges of the square wave input signal.

[0024] A device according to one or more embodiments comprising:

• a PWM modulation circuit according to one or more embodiments producing a PWM modulated signal,
• an input circuit block configured for receiving an input signal and providing to the PWM modulation circuit said modulating signal as a function of said input signal,
• a switching power stage driven by the PWM modulated signal from the PWM modulation circuit, and
• a low-pass filter circuit receiving a switching power signal from the switching power stage and producing therefrom an amplified replica of the input signal.

[0025] One or more embodiments, comprises a feedback path between the switching power stage and the input circuit block.

[0026] In one or more embodiments according to the invention, a method comprises:

• receiving at a first circuit block a square wave input signal having rising and falling edges and producing from the square wave input signal a triangular wave signal,
• receiving at a second circuit block a modulating signal,
• and producing a PWM modulated signal by comparing the modulating signal with a carrier signal,

characterized in that the method comprises

selectively forcing the carrier signal to upper and lower reference values, respectively, over carrier forcing intervals at the rising and falling edges of the square wave input signal, by receiving at a switching circuit block active between the first circuit block and the second circuit block reference signals having upper and lower reference values, and selectively switching said switching circuit block between: - a carrier transfer setting, wherein the switching circuit block couples the first circuit block to the second circuit block to transfer thereto the triangular wave signal as the carrier signal, and

at least one carrier forcing setting wherein the switching circuit block applies to the second circuit block said references signals by forcing the carrier signal to said upper and lower reference values, respectively.

[0027] In one or more embodiments, wherein said carrier forcing intervals are centered around the rising and falling edges of the square wave input signal.

[0028] In one or more embodiments, the modulating signal has a modulating signal swing between highest and lowest modulating signal values, wherein selectively forcing the carrier signal to upper and lower reference values may comprise:

• a first carrier forcing mode wherein the upper and lower reference values are selected at first values lying within the modulating signal swing, and
• a second carrier forcing mode wherein the upper and lower reference values are selected at second values lying outside the modulating signal swing.

[0029] One or more embodiments comprises:

• selecting a lowest value for the duty cycle of the PWM modulated signal wherein the PWM modulated signal has a lowest pulse active time at the selected lowest value for the duty cycle,
• selecting the duration of the carrier forcing intervals to the upper and lower reference values equal to said lowest pulse active time.

Brief description of the several views of the drawings

[0030] One or more embodiments will now be described, by way of example only, with reference to the annexed figures, wherein:

• Figure 1 is an exemplary diagram of a circuit involving pulse width modulation (PWM);
• Figure 2 is a circuit diagram according to an embodiment of the invention;
• Figure 3, comprising portions designated a) to e), shows exemplary time diagrams of signals which may occur in embodiments;
• Figure 4, comprising portions designated a) and b1), b2), shows exemplary time diagrams of signals which may occur in embodiments, and
• Figure 5 is a block diagram of a device according to embodiments.

Detailed description

[0031] In the ensuing description, one or more specific details are illustrated, aimed at providing an in-depth understanding of examples of embodiments of this description. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that certain aspects of embodiments will not be obscured.

[0032] Reference to "an embodiment" or "one embodiment" in the framework of the present description is intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as "in an embodiment" or "in one embodiment" that may be present in one or more points of the present description do not necessarily refer to one and the same embodiment. Moreover, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments.

[0033] The references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments.

[0034] By way of introduction to the concept of "pulse skipping", one may note that, in order to achieve a high output signal dynamics, certain PWM (Pulse Width Modulation) modulators contemplate the possibility for the duty cycle to reach values such as 100% and 0%.

[0035] The designation duty cycle applies to the fraction of the period of a pulsed signal (the period being the time for the signal to complete an on-and-off cycle) where the signal is "on", namely active, that is

where:

D is the duty cycle

T is the (total) period

PW is the pulse width (pulse active time) or "on" time.

[0036] As a result of the duty cycle reaching extreme values such as 100% and 0% the switching frequency (Fsw), near clipping, may decrease by a factor 2, 4 and so on and switching may even be discontinued over the whole interval over which the output voltage is in a saturation state.

[0037] This phenomenon is known as "pulse skipping".

[0038] The behavior in the vicinity of and at saturation (clipping) may play a significant role in a switching PWM modulator (e.g. for audio applications).

[0039] In order to avoid an anomalous behavior, e.g. in those systems contemplating a high feedback factor, pulse skipping should desirably be "optimized", namely confined to take place as close to the saturation thresholds as possible.

[0040] The frequency spectrum (e.g. FFT) of PWM modulated signals before pulse skipping exhibits an essentially regular harmonic contents, with peaks at the switching frequency and multiples thereof. In the presence of pulse skipping, the switching "bursts" generate tones also at zones different from the switching frequency and the multiples thereof, possibly affecting also the frequency domain below the switching frequency Fsw.

[0041] In certain systems, EMI issues suggest that a fixed switching frequency is maintained also in the presence of clipping. For that reason, certain PWM systems contemplate a "pulse skipping inhibition" circuit which is associated to the "pulse skipping optimization" circuit discussed previously.

[0042] The block diagram of Figure 1 is exemplary of a switching circuit (e.g. a PWM modulator) comprising a first circuit block 10 intended to provide "optimized" clipping behavior and a second circuit block 20 intended to provide a pulse skipping inhibit function.

[0043] The circuit block 10 may essentially correspond to the solution disclosed in US 9 595 946 B2 (already cited).

[0044] Briefly, the circuit block 10 may comprise a conventional PWM modulator wherein a triangular carrier waveform Vtri is generated via an integrator 12 driven via a square (rectangular) wave Isq.

[0045] An PWM-modulated output signal Out(PWM1) is obtained by comparing at a comparator 14 the carrier signal Vtri carrier (from the integrator 12) with a modulating signal Vmod.

[0046] In proximity to clipping, small variations in the modulating signal Vmod (possibly due to noise) may result in a pulse being "skipped" which may be the source of instability and undesirable chaotic behavior near clipping. As exemplified in US 9 595 946 B2, this issue can be addressed by superposing to the carrier signal Isq a pulsed signal Ipulse applied to the input of the integrator 12 thus giving rise to narrow "steeper" pulses which, in near-clipping conditions, force switching.

[0047] Such an approach may be regarded as corresponding to a reduction of the gain of the modulator intended to render the discontinuity arising at that point less critical.

[0048] The pulse Ipulse may thus take the form of a short, spike-like, current pulse added in a synchronized manner to the square (rectangular) clock waveform Isq.

[0049] The circuit block 20 may essentially comprise a pulse injector which is configured in order to sense a missing pulse which was "skipped" in the output signal Out(PWM1) of the modulator 10 and add it in a final output signal Out(PWM2).

[0050] It is noted that such an added signal will expectedly exhibit a slight delay with respect to the corresponding transition in the clock signal CLK.

[0051] This may represent one of the issues affecting an arrangement as exemplified in Figure 1 if the PWM frequency is increased e.g. from about 300 kHz to values in excess of 2 MHz, as currently contemplated for various applications.

[0052] Other issues may be related to the slew rate of the integrator 12 which produces the triangular carrier in conjunction with the effect of the second pole therein and/or limitations related to current consumption which may adversely affect the capability of providing a pulse for controlling adequately pulse skipping. These factors, in conjunction with the possible delay of the pulse skipping inhibition action (circuit block 20) as discussed previously, may adversely affect the spectrum of the final output signal Out(PWM2).

[0053] One or more embodiments may address these issues by resorting to a circuit as exemplified in Figure 2.

[0054] In Figure 2 parts or elements like parts or elements already discussed in connection with the Figure 1 are indicated with like references. A corresponding description will not be repeated here for brevity.

[0055] The circuit of Figure 2 is thus again configured for receiving, at one (e.g. inverting) input of the comparator 14, the modulating signal Vmod and producing (in a manner known per se) a PWM modulated signal Out(PWM) by comparing the modulating signal Vmod with a carrier signal Vtri2. Such a carrier signal may again be produced starting from a square wave input (e.g. current) signal Isq having rising and falling edges and by producing from the square (rectangular) wave input signal Isq (e.g. via integration at the integrator 12) a triangular wave (e.g. voltage) signal Vtri comprising alternating peaks and valleys.

[0056] In one or more embodiments as exemplified in Figure 2, the signal Vtri can be applied to a circuit portion indicated 100 (to be discussed in the following), active between the circuit block 12 (integrator) and the circuit block 14 (comparator) to generate the carrier signal Vtri2 from the triangular wave signal Vtri.

[0057] As discussed in the following, the circuit portion 100 is configured for, so-to-say, modifying the signal Vtri by forcing the peaks and valleys of the signal to certain upper and lower reference values, with such modifying/forcing being adapted to be effected selectively (as a result of the occurrence of certain conditions), with the further optional capability for the circuit portion 100 to select a first forcing mode (pulse skipping optimization) and a second forcing mode (pulse skipping inhibit), wherein a first and a second value can be chosen for the upper and lower reference values, respectively.

[0058] By comparing the circuit of Figure 2 with the circuit of Figure 1 one may note that the pulse generator Ipulse at the input of the integrator 12 is no longer present in the circuit of Figure 2.

[0059] In one or more embodiments, in the circuit of Figure 2, the function of providing (e.g. voltage) pulses at the vertexes (peaks and valleys) of the waveform Vtri is implemented by means of a switch 102 in the circuit portion 100.

[0060] In one or more embodiments as exemplified herein, the switch 102 comprises an output node 102a coupled to the input of the comparator 14 to provide the signal Vtri2 as a signal selected out of three possible options applied to three inputs to the switch 102, these inputs being labeled "0", "1" and "2", respectively.

[0061] The input "0" corresponds to the output from the integrator 12, that is the triangular waveform signal Vtri.

[0062] The input "1" is obtained from a circuit block 104 which in turn comprises a switch which may selectively coupled, over a certain forcing time interval, to either one of two "higher" reference (e.g. DC voltage) levels Vp and Vp(max)+dv.

[0063] The input "2" is obtained from a circuit block 106 which in term comprises a switch which may selectively coupled, over a certain forcing time interval, to either one of two "lower" reference (e.g. DC voltage) levels Vm and Vm(max)-dv.

[0064] These reference levels may be obtained from conventional signal (e.g. voltage) sources, not visible in the figures.

[0065] As discussed in the following, these reference levels may be regarded as corresponding to some sort of upper and lower "end of scale" reference values to which the input triangular signal Vtri may be forced upward (to Vp or, alternatively, Vp(max)+dv) or downward (to Vm or, alternatively, Vm(max)-dv), over a certain forcing time interval (that is, not merely as instantaneous pulses) in order to provide pulse skipping control/pulse skipping inhibit functions.

[0066] As exemplified in Figure 2, the circuit blocks 104, 106 operate under the control of a pulse skipping inhibit/enabled signal I/E (operation mode selection) obtained over a line 108 from a source (not visible in the figures), according to principles known per se (see also US 9 595 946 B2, already cited).

[0067] Reference 110 in Figure 2 indicates a timing generator which receives the PWM clock signal (e.g. Isq, generated in any conventional manner) over a line 110a, e.g. with a 50% duty cycle.

[0068] In one or more embodiments as exemplified in the time diagrams of Figure 3, the switch 102 may be controlled by the timing generator 110 based on three clocking signals, comprising:

• the clock signal (PWM clock), e.g. with a duty cycle = 50%, having rising edges RE and falling edges FE: see the diagram a) in Figure 3;
• a first square wave (pulse) signal Sync 1 which goes to a logic level "1", at the rising edges RE of the clock signal for a certain time duration (e.g. centered temporarily on the rising edges RE) which may be selected to correspond to a smallest desired duty cycle value for the output signal: see the diagram b) in Figure 3; and
• a second square wave (pulse) signal Sync 2 which goes to a logic level "1" at the falling edges FE of the clock signal for a time duration (e.g. centered temporarily on the falling edges FE) which again may be selected to correspond to the smallest desired duty cycle value for the output signal: see the diagram c) in Figure 3.

[0069] By observing the diagrams in portions b) and c) in Figure 3 one may note that the square wave signals Sync1 and Sync 2 comprise pulses of a certain time duration (and not merely instantaneous spike-like pulses) with that time duration possibly dictated by a smallest desired duty cycle value for the PWM modulated output signal Out(PWM), e.g. selected equal to the pulse width (pulse active time) or "on" time (PW, in the formula reproduced in the introductory portion of this description) corresponding to a smallest desired duty cycle value for Out(PWM).

[0070] Portions d) and e) of Figure 3 are exemplary of a corresponding possible time behavior of Vtri and Vtri2.

[0071] In one or more embodiments, the switch 102 may thus take:

• the "0" position (carrier transfer setting), with Vtri applied to the comparator 14 as Vtri2, as a result of both signals Sync1 and Sync2 being equal to zero, namely with Sync1 = Sync2 = 0;
• the "1" position (first carrier forcing setting), as a result of Sync1 = 1 and Sync 2 = 0, so that the output from the block 104 is coupled to the comparator 14, with Vtri2 resulting from Vtri being forced "upward" to either one of the upper reference values Vp or Vp(max)+dv (e.g. DC voltages) as a function of the position taken by the switch in the block 104;
• the "2" position (second carrier forcing setting), as a result of Sync1 = 0 and Sync 2 = 1, so that the output from the block 106 is coupled to the comparator 14, with Vtri2 resulting from Vtri being forced "downward" to either one of the lower reference values Vm or Vm(max)-dv (e.g. DC voltages) as a function of the position taken by the switch in the block 106.

[0072] As exemplified in portions d) and e) of Figure 3, while corresponding to Vtri when Sync1 = Sync2 = 0, as a result of Sync1 or Sync2 going to 1, the signal Vtri2 will be "modified" with respect to triangular signal Vtri input to the circuit portion 100 insofar as the vertexes (peaks and valleys) of Vtri will have superposed pulses (upward and downward, respectively) of controlled shape and amplitude over the duration of the forcing time intervals set by Sync1 or Sync 2.

[0073] The modified triangular-with-superposed-pulses waveform of Vtri2 resulting from selectively forcing the alternating peaks and valleys of the triangular wave carrier signal to upper and lower reference values will thus exhibit (as a function of the value of pulse skipping optimization/inhibit signal I/E on the line 108) :

• with the switches 104, 106 connected to Vp and Vm, first reference values Vp (positive) or Vm (negative), or
• with the switches 104, 106 connected to Vp(max)+dv and Vm(max)-dv, second reference values Vp(max)+dv (positive) or Vm(max)-dv (negative), respectively.

[0074] In one or more embodiments, the first reference values Vp and Vm, may be selected to be within the largest expected swing of the modulating signal Vmod, that is smaller (in modulus) of the highest and lowest expected values for Vmod.

[0075] In one or more embodiments, this first option will result in a first forcing mode to produce in Vtri2 upper and lower reference values selected at first values Vp, Vm lying within the modulating signal swing between highest and lowest values.

[0076] In that way, the area near saturation of the PWM signal will be made (more) regular, especially in systems with feedback, reducing the gain of the PWM modulator in that zone.

[0077] In fact, with Vmod reaching values in excess of Vp or lower than Vm the duty cycle will reach corresponding values 100% or 0%, thus achieving a large output signal dynamics, and performing a pulse skipping optimization function.

[0078] In one or more embodiments, in addition to being larger (in modulus) of both Vp and Vm, the second reference values Vp(max)+dv and Vm(max)-dv may be selected to be in excess of the largest expected swing of the modulating signal Vmod, that is larger (in modulus) of the highest and lowest expected values for Vmod.

[0079] In one or more embodiments, this second option will result in a second forcing mode to produce in Vtri2 upper and lower reference values selected at second values (Vp(max)+dv, Vm(max)-dv) lying outside the modulating signal swing between highest and lowest values.

[0080] These may serve the purpose of avoiding that the duty cycle may reach values such as 100% or 0%, thereby maintaining the nominal clock frequency with a lowest duty cycle value as set by the duty cycle of the signals Sync1 and Sync2, thus performing a pulse skipping inhibit function.

[0081] This type of operation is exemplified in Figure 4 wherein portion a) shows a possible behavior of the signal Vtri2 with a possible time behavior of the modulating signal Vmod also shown for direct reference.

[0082] The portions b1) and b2) of Figure 4 show a possible time behavior of the PWM modulated output signal Out(PWM):

• with pulse skipping enabled and optimized (with the switch 104 switched on Vp), and
• with pulse skipping disabled/inhibited, with the switch 104 switched on Vp(max)+dv.

[0083] A similar result will be provided with the switch 106 on Vm and Vm(max)-dv (by taking into account the possible reversed polarity).

[0084] The block diagram of Figure 5 is exemplary of the possible inclusion of a circuit as exemplified in Figure 2 in a high-frequency PWM power circuit (e.g. a class D audio amplifier) receiving an input signal Vin and comprising an input integrator 200 and wherein the output signal Out(PWM) from the comparator 14 is fed to a power switch 202 switching between two values +Vpot and -Vpot. The diagram of Figure 5 also shows a (negative) feedback path 206 with gain 1/K to be subtracted at an input node 208 from the input signal Vin input to the integrator 200. The output from the switch 202 can be applied to an output LC (reconstruction) filter 204 to provide an output amplified signal KVin (that is the input signal Vin having a gain K applied thereto).

[0085] As for the rest, operation of an arrangement as exemplified in Figure 5 (essentially a class D amplifier) is otherwise conventional in the art, thus making it unnecessary to provide a more detailed description herein.

[0086] Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what has been described by way of example only without departing from the extent of protection. The extent of protection is defined by the annexed claims.

Claims

1. A circuit, comprising:

- a first circuit block (12) configured for receiving a square wave input signal (Isq) having rising (RE) and falling (FE) edges and producing from the square wave input signal (Isq) a triangular wave signal (Vtri),

- a second circuit block (14) configured for receiving a modulating signal (Vmod) and producing a PWM modulated signal (Out(PWM)) by comparing (14) the modulating signal (Vmod) with a carrier signal (Vtri2),

characterized by

- a switching circuit block (100) active between the first circuit block (12) and the second circuit block (14), wherein the switching circuit block (100) includes reference inputs (104, 106) configured for receiving reference signals having upper (Vp, Vp(max)+dv) and lower (Vm; Vm(max)-dv) reference values and is selectively (Sync1, Sync2; I/E) switchable (102) between:

- a carrier transfer setting (0), wherein the switching circuit block (100) couples the first circuit block (12) to the second circuit block (14) to transfer thereto the triangular wave signal (Vtri) as the carrier signal (Vtri2), and

- at least one carrier forcing setting (1, 2) wherein the switching circuit block (100) applies to the second circuit block (14) said reference signals by forcing the carrier signal (Vtri2) to said upper (Vp, Vp(max)+dv) and lower (Vm; Vm(max)-dv) reference values, respectively.

2. The circuit of claim 1, wherein:

- the second circuit block (14) is configured for receiving the modulating signal (Vmod) having a modulating signal swing between highest and lowest modulating signal (Vmod) values,

- the switching circuit block (100):

i) includes reference inputs (104, 106) configured for receiving reference signals having first upper (Vp) and first lower (Vm) reference values lying within the modulating signal swing as well as second upper (Vp(max)+dv) and second lower (Vm(max)-dv) reference values lying outside the modulating signal swing,

ii) is selectively switchable (104, 106) between:

- a first carrier forcing setting (E), wherein the switching circuit block (100) applies to the second circuit block (14) said reference signals with said first upper (Vp) and first lower (Vm) reference values,

- a second carrier forcing setting (I), wherein the switching circuit block (100) applies to the second circuit block (14) said reference signals with said second upper (Vp(max)+dv) and second lower (Vm(max)-dv) reference values.

3. The circuit of claim 1 or claim 2, wherein:

- the second circuit block (14) is configured for producing the PWM modulated signal (Out(PWM)) with a lowest value for the PWM duty cycle wherein the PWM modulated signal has a lowest pulse active time at the selected lowest value for the duty cycle,

- the switching circuit block (100) is selectively (Sync1, Sync2) switchable (102) to the at least one carrier forcing setting (1, 2) over carrier forcing intervals equal to said lowest pulse active time.

4. The circuit of any of the previous claims, comprising a clock circuit block (110) sensitive to the rising (RE) and falling (FE) edges of the square wave input signal (Isq), the clock circuit block (110) configured for driving the switching circuit block (100) to switch between the carrier transfer setting (0) and the at least one carrier forcing setting (1, 2) at the rising (RE) and falling (FE) edges of the square wave input signal (Isq).

5. The circuit of claim 4, wherein the clock circuit block (110) is configured for driving the switching circuit block (100) to switch to the at least one carrier forcing setting (1, 2) over carrier forcing intervals centered around the rising (RE) and falling (FE) edges of the square wave input signal (Isq).

6. A device, comprising:

- a PWM modulation circuit (12, 14, 100) according to any of claims 1 to 5 producing a PWM modulated signal (Out(PWM)),

- an input circuit block (200, 208) configured for receiving an input signal (Vin) and providing to the PWM modulation circuit (12, 14, 100) said modulating signal (Vmod) as a function of said input signal (Vin),

- a switching power stage (202) driven by the PWM modulated signal (Out(PWM)) from the PWM modulation circuit (12, 14, 100), and

- a low-pass filter circuit (204) receiving a switching power signal from the switching power stage (202) and producing therefrom an amplified replica (KVin) of the input signal (Vin).

7. The device of claim 6, comprising a feedback path (206) between the switching power stage (202) and the input circuit block (208).

8. A method, comprising:

- receiving at a first circuit block (12) a square wave input signal (Isq) having rising (RE) and falling (FE) edges and producing from the square wave input signal (Isq) a triangular wave signal (Vtri),

- receiving at a second circuit block (14) a modulating signal (Vmod) and producing a PWM modulated signal (Out(PWM)) by comparing (14) the modulating signal (Vmod) with a carrier signal (Vtri2),

characterized in that the method comprises selectively (Sync1, Sync2) forcing the carrier signal (Vtri2) to upper (Vp, Vp(max)+dv) and lower (Vm; Vm(max)-dv) reference values, respectively, over carrier forcing intervals at the rising (RE) and falling edges (FE) of the square wave input signal (Isq) by receiving at a switching circuit block (100) active between the first circuit block (12) and the second circuit block (14) reference signals having upper (Vp, Vp(max)+dv) and lower (Vm; Vm(max)-dv) reference values, and selectively (Sync1, Sync2; I/E) switching (102) said switching circuit block (100) between:

- a carrier transfer setting (0), wherein the switching circuit block (100) couples the first circuit block (12) to the second circuit block (14) to transfer thereto the triangular wave signal (Vtri) as the carrier signal (Vtri2), and

- at least one carrier forcing setting (1, 2) wherein the switching circuit block (100) applies to the second circuit block (14) said reference signals by forcing the carrier signal (Vtri2) to said upper (Vp, Vp(max)+dv) and lower (Vm; Vm(max)-dv) reference values, respectively.

9. The method of claim 8, wherein said carrier forcing intervals are centered around the rising (RE) and falling (FE) edges of the square wave input signal (Isq) .

10. The method of claim 8 or claim 9, wherein the modulating signal (Vmod) has a modulating signal swing between highest and lowest modulating signal (Vmod) values, wherein selectively (Sync1, Sync2) forcing the carrier signal (Vtri2) to upper and lower reference values comprises:

- a first carrier forcing mode wherein the upper and lower reference values are selected at first values (Vp, Vm) lying within the modulating signal swing, and

- a second carrier forcing mode wherein the upper and lower reference values are selected at second values (Vp(max)+dv, Vm(max)-dv) lying outside the modulating signal swing.

11. The method of any of claims 8 to 10, comprising:

- selecting a lowest value for the duty cycle of the PWM modulated signal (Out (PWM)) wherein the PWM modulated signal has a lowest pulse active time at the selected lowest value for the duty cycle,

- selecting the duration of the carrier forcing intervals to the upper (Vp, Vp(max)+dv) and lower (Vm; Vm(max)-dv) reference values equal to said lowest pulse active time.

Ansprüche

1. Schaltung, umfassend:

- einen ersten Schaltungsblock (12), der zum Empfangen eines Quadratwelleneingangssignals (Isq) konfiguriert ist, das steigende (RE) und fallende (FE) Flanken aufweist, und aus dem Quadratwelleneingangssignal (Isq) ein dreieckiges Wellensignal (Vtri) erzeugt,

- einen zweiten Schaltungsblock (14), der zum Empfangen eines Modulationssignals (Vmod) und Erzeugen eines PWM-modulierten Signals (Out(PWM)) durch Vergleichen (14) des Modulationssignals (Vmod) mit einem Trägersignal (Vtri2) konfiguriert ist,

gekennzeichnet durch

- einen Umschaltschaltungsblock (100), der zwischen dem ersten Schaltungsblock (12) und dem zweiten Schaltungsblock (14) aktiv ist, wobei der Umschaltschaltungsblock (100) Referenzeingänge (104, 106) beinhaltet, die zum Empfangen von Referenzsignalen konfiguriert ist, die obere (Vp, Vp(max)+dv) und untere (Vm, Vm(max)-dv) Referenzwerte aufweisen, und selektiv (Sync1, Sync2; I/E) umschaltbar (102) ist, zwischen:

- einer Trägerübertragungseinstellung (0), wobei der Umschaltschaltungsblock (100) den ersten Schaltungsblock (12) mit dem zweiten Schaltungsblock (14) koppelt, um dahin das dreieckige Wellensignal (Vtri) als das Trägersignal (Vtri2) zu übertragen, und

- mindestens einer Trägerforcierungseinstellung (1, 2), wobei der Umschaltschaltungsblock (100) auf den zweiten Schaltungsblock (14) die Referenzsignale durch Forcieren des Trägersignals (Vtri2) jeweils auf die oberen (Vp, Vp(max)+dv) und unteren (Vm; Vm(max)-dv) Referenzwerte anwendet.

2. Schaltung nach Anspruch 1, wobei:

- der zweite Schaltungsblock (14) zum Empfangen des Modulationssignals (Vmod) konfiguriert ist, das einen Modulationssignalhub zwischen höchsten und niedrigsten Modulationssignal-(Vmod)-Werten aufweist,

- der Umschaltschaltungsblock (100):

i) Referenzeingänge (104, 106) beinhaltet, die zum Empfangen von Referenzsignalen konfiguriert sind, die erste obere (Vp) und erste untere (Vm) Referenzwerte aufweisen, die innerhalb des Modulationssignalhubs liegen, sowie zweite obere (Vp(max)+dv) und zweite untere (Vm(max)-dv) Referenzwerte, die außerhalb des Modulationssignalhubs liegen,

ii) selektiv umschaltbar (104, 106) ist zwischen:

- einer ersten Trägerforcierungseinstellung (E), wobei der Umschaltschaltungsblock (100) auf den zweiten Schaltungsblock (14) die Referenzsignale mit den ersten oberen (Vp) und ersten unteren (Vm) Referenzwerten anwendet,

- einer zweiten Trägerforcierungseinstellung (I), wobei der Umschaltschaltungsblock (100) auf den zweiten Schaltungsblock (14) die Referenzsignale mit den zweiten oberen (Vp(max)+dv) und zweiten unteren (Vm(max)-dv) Referenzwerten anwendet.

3. Schaltung nach Anspruch 1 oder Anspruch 2, wobei:

- der zweite Schaltungsblock (14) zum Erzeugen des PWM-modulierten Signals (Out(PWM)) mit einem niedrigsten Wert für den PWM-Arbeitszyklus konfiguriert ist, wobei das PWMmodulierte Signal eine niedrigste aktive Pulszeit am ausgewählten niedrigsten Wert für den Arbeitszyklus aufweist,

- der Umschaltschaltungsblock (100) selektiv (Sync1, Sync2) auf die mindestens eine Trägerforcierungseinstellung (1, 2) über Trägerforcierungsintervalle umschaltbar (102) ist, die gleich der niedrigsten aktiven Pulszeit sind.

4. Schaltung nach einem der vorstehenden Ansprüche, umfassend einen Taktschaltungsblock (110), der empfindlich gegenüber steigenden (RE) und fallenden (FE) Flanken des Quadratwelleneingangssignals (Isq) ist, wobei der Taktschaltungsblock (110) zum Antreiben des Umschaltschaltungsblocks (100) konfiguriert ist, um zwischen der Trägerübertragungseinstellung (0) und der mindestens einen Trägerforcierungseinstellung (1, 2) an den steigenden (RE) und fallenden (FE) Flanken des Quadratwelleneingangssignals (Isq) umzuschalten.

5. Schaltung nach Anspruch 4, wobei der Taktschaltungsblock (110) zum Antreiben des Umschaltschaltungsblocks (100) konfiguriert ist, um auf die mindestens eine Trägerforcierungseinstellung (1, 2) über die Trägerforcierungsintervalle umzuschalten, die um die steigenden (RE) und fallenden (FE) Flanken des Quadratwelleneingangssignals (Isq) herum zentriert sind.

6. Vorrichtung, umfassend:

- eine PWM-Modulationsschaltung (12, 14, 100) nach einem der Ansprüche 1 bis 5, die ein PWM-moduliertes Signal (Out(PWM)) erzeugt,

- einen Eingangsschaltungsblock (200, 208), der zum Empfangen eines Eingangssignals (Vin) konfiguriert ist, und der PWM-Modulationsschaltung (12, 14, 100) das Modulationssignal (Vmod) in Abhängigkeit von dem Eingangssignal (Vin) bereitstellt,

- eine Umschaltleistungsstufe (202), die von dem PWM-modulierten Signal (Out(PWM)) aus der PWM-Modulationsschaltung (12, 14, 100) angetrieben wird, und

- eine Tiefpassfilterschaltung (204), die ein Umschaltleistungssignal von der Umschaltleistungsstufe (202) empfängt und daraus eine verstärkte Nachbildung (KVin) des Eingangssignals (Vin) erzeugt.

7. Vorrichtung nach Anspruch 6, einen Rückkopplungspfad (206) zwischen der Umschaltleistungsstufe (202) und dem Eingangsschaltungsblock (208) umfassend.

8. Verfahren, umfassend:

- Empfangen an einem ersten Schaltungsblock (12) eines Quadratwelleneingangssignals (Isq), das steigende (RE) und fallende (FE) Flanken aufweist, und aus dem Quadratwelleneingangssignal (Isq) ein dreieckiges Wellensignal (Vtri) erzeugt,

- Empfangen an einem zweiten Schaltungsblock (14) eines Modulationssignals (Vmod) und Erzeugen eines PWM-modulierten Signals (Out(PWM)) durch Vergleichen (14) des Modulationssignals (Vmod) mit einem Trägersignal (Vtri2), dadurch gekennzeichnet, dass

das Verfahren selektives (Sync1, Sync2) Forcieren des Trägersignals (Vtri2) jeweils auf obere (Vp, Vp(max)+dv) und untere (Vm; Vm(max)-dv) Referenzwerte über Trägerforcierungsintervalle an den steigenden (RE) und fallenden (FE) Flanken des Quadratwelleneingangssignals (Isq) durch Empfangen an einem Umschaltschaltungsblock (100), der zwischen dem ersten Schaltungsblock (12) und dem zweiten Schaltungsblock (14) aktiv ist, von Referenzsignalen umfasst, die obere (Vp, Vp(max)+dv) und untere (Vm; Vm(max)-dv) Referenzwerte aufweisen, und selektives (Sync1, Sync2; I/E) Umschalten (102) des Umschaltschaltungsblocks (100) zwischen:

- einer Trägerübertragungseinstellung (0), wobei der Umschaltschaltungsblock (100) den ersten Schaltungsblock (12) mit dem zweiten Schaltungsblock (14) koppelt, um dahin das dreieckige Wellensignal (Vtri) als das Trägersignal (Vtri2) zu übertragen, und

- mindestens einer Trägerforcierungseinstellung (1, 2), wobei der Umschaltschaltungsblock (100) auf den zweiten Schaltungsblock (14) die Referenzsignale durch Forcieren des Trägersignals (Vtri2) jeweils auf die oberen (Vp, Vp(max)+dv) und unteren (Vm; Vm(max)-dv) Referenzwerte anwendet.

9. Verfahren nach Anspruch 8, wobei die Trägerforcierungsintervalle um die steigenden (RE) und fallenden (FE) Flanken des Quadratwelleneingangssignals (Isq) herum zentriert sind.

10. Verfahren nach Anspruch 8 oder Anspruch 9, wobei das Modulationssignal (Vmod) einen Modulationssignalhub zwischen höchsten und niedrigsten Modulationssignal-(Vmod)-Werten aufweist, wobei das selektive (Sync1, Sync2) Forcieren des Trägersignals (Vtri2) auf obere und untere Referenzwerte umfasst:

- einen ersten Trägerforcierungsmodus, wobei die oberen und unteren Referenzwerte an ersten Werten (Vp, Vm), die innerhalb des Modulationssignalhubs liegen, ausgewählt werden, und

- einen zweiten Trägerforcierungsmodus, wobei die oberen und unteren Referenzwerte an zweiten Werten (Vp(max)+dv, Vm(max)-dv), die außerhalb des Modulationssignalhubs liegen, ausgewählt werden.

11. Verfahren nach einem der Ansprüche 8 bis 10, umfassend:

- Auswählen eines niedrigsten Werts für den Arbeitszyklus des PWM-modulierten Signals (Out(PWM)), wobei das PWMmodulierte Signal eine niedrigste aktive Pulszeit an dem ausgewählten niedrigsten Wert für den Arbeitszyklus aufweist,

- Auswählen der Dauer der Trägerforcierungsintervalle auf die oberen (Vp, Vp(max)+dv) und unteren (Vm; Vm(max)-dv) Referenzwerte gleich der niedrigsten aktiven Pulszeit.

Revendications

1. Circuit comprenant :

- un premier bloc de circuit (12) configuré pour recevoir un signal d'entrée carré (Isq) ayant des fronts montants (RE) et descendants (FE) et produisant à partir du signal d'entrée carré (Isq) un signal triangulaire (Vtri),

- un deuxième bloc de circuit (14) configuré pour recevoir un signal de modulation (Vmod) et produisant un signal modulé par modulation d'impulsions en durée (Out(PWM)) en comparant (14) le signal de modulation (Vmod) avec un signal porteur (Vtri2), caractérisé par :

- un bloc de circuit de commutation (100) actif entre le premier bloc de circuit (12) et le deuxième bloc de circuit (14), dans lequel le bloc de circuit de commutation (100) comprend des entrées de référence (104, 106) configurées pour recevoir des signaux de référence ayant des valeurs de référence supérieures (Vp, Vp(max)+dv) et inférieures (Vm ; Vm(max)-dv) et peut être commuté (102) au choix (Sync1, Sync2 ; I/E) entre :

- un réglage de transfert de porteuse (0), dans lequel le bloc de circuit de commutation (100) couple le premier bloc de circuit (12) au deuxième bloc de circuit (14) pour transférer vers ce dernier le signal triangulaire (Vtri) en tant que signal porteur (Vtri2), et

- au moins un réglage de forçage de porteuse (1, 2) dans lequel le bloc de circuit de commutation (100) applique au deuxième bloc de circuit (14) lesdits signaux de référence en forçant le signal porteur (Vtri2) à prendre respectivement lesdites valeurs de référence supérieures (Vp, Vp(max)+dv) et inférieures (Vm ; Vm(max)-dv).

2. Circuit selon la revendication 1, dans lequel :

- le deuxième bloc de circuit (14) est configuré pour recevoir le signal de modulation (Vmod) ayant une variation de signal de modulation entre des valeurs de signal de modulation (Vmod) la plus haute et la plus basse,

- le bloc de circuit de commutation (100) :

i) comprend des entrées de référence (104, 106) configurées pour recevoir des signaux de référence ayant une première valeur de référence supérieure (Vp) et une première valeur de référence inférieure (Vm) qui se trouvent dans les limites de la variation du signal de modulation ainsi qu'une deuxième valeur de référence supérieure (Vp(max)+dv) et une deuxième valeur de référence inférieure (Vm(max)-dv) qui se trouvent en dehors de la variation du signal de modulation,

ii) peut être commuté (104, 106) au choix entre :

- un premier réglage de forçage de porteuse (E), dans lequel le bloc de circuit de commutation (100) applique au deuxième bloc de circuit (14) lesdits signaux de référence avec ladite première valeur de référence supérieure (Vp) et ladite première valeur de référence inférieure (Vm),

- un deuxième réglage de forçage de porteuse (I), dans lequel le bloc de circuit de commutation (100) applique au deuxième bloc de circuit (14) lesdits signaux de référence avec ladite deuxième valeur de référence supérieure (Vp(max)+dv) et ladite deuxième valeur de référence inférieure (Vm(max)-dv).

3. Circuit selon la revendication 1 ou 2, dans lequel :

- le deuxième bloc de circuit (14) est configuré pour produire le signal modulé par modulation d'impulsions en durée (Out(PWM)) avec une valeur la plus basse pour le cycle d'utilisation MID où le signal modulé par MID a un temps actif d'impulsion le plus petit à la valeur la plus basse choisie pour le cycle d'utilisation,

- le bloc de circuit de commutation (100) peut être commuté (102) au choix (Sync1, Sync2) sur ledit au moins un réglage de forçage de porteuse (1, 2) sur des intervalles de forçage de porteuse égaux audit temps actif d'impulsion le plus petit.

4. Circuit selon l'une quelconque des revendications précédentes, comprenant un bloc de circuit d'horloge (110) sensible aux fronts montants (RE) et descendants (FE) du signal d'entrée carré (Isq), le bloc de circuit d'horloge (110) étant configuré pour piloter le bloc de circuit de commutation (100) pour le faire commuter entre le réglage de transfert de porteuse (0) et ledit au moins un réglage de forçage de porteuse (1, 2) aux fronts montants (RE) et descendants (FE) du signal d'entrée carré (Isq).

5. Circuit selon la revendication 4, dans lequel le bloc de circuit d'horloge (110) est configuré pour piloter le bloc de circuit de commutation (100) pour le faire commuter vers ledit au moins un réglage de forçage de porteuse (1, 2) sur des intervalles de forçage de porteuse centrés autour des fronts montants (RE) et descendants (FE) du signal d'entrée carré (Isq).

6. Dispositif comprenant :

- un circuit de modulation d'impulsions en durée (12, 14, 100) selon l'une quelconque des revendications 1 à 5 produisant un signal modulé par modulation d'impulsions en durée (Out(PWM)),

- un bloc de circuit d'entrée (200, 208) configuré pour recevoir un signal d'entrée (Vin) et fournissant au circuit de modulation MID (12, 14, 100) ledit signal de modulation (Vmod) en fonction dudit signal d'entrée (Vin),

- un étage de puissance de commutation (202) piloté par le signal modulé MID (Out(PWM)) provenant du circuit de modulation MID (12, 14, 100), et

- un circuit de filtre passe-bas (204) recevant un signal de puissance de commutation de l'étage de puissance de commutation (202) et produisant à partir de celui-ci une copie amplifiée (KVin) du signal d'entrée (Vin).

7. Dispositif selon la revendication 6, comprenant un chemin de rétroaction (206) entre l'étage de puissance de commutation (202) et le bloc de circuit d'entrée (208).

8. Procédé comprenant les étapes suivantes :

- recevoir dans un premier bloc de circuit (12) un signal d'entrée carré (Isq) ayant des fronts montants (RE) et descendants (FE) et produire à partir du signal d'entrée carré (Isq) un signal triangulaire (Vtri),

- recevoir dans un deuxième bloc de circuit (14) un signal de modulation (Vmod) et produire un signal modulé par modulation d'impulsions en durée (Out(PWM)) en comparant (14) le signal de modulation (Vmod) avec un signal porteur (Vtri2),

caractérisé en ce que le procédé comprend le fait de forcer au choix (Sync1, Sync2) le signal porteur (Vtri2) à prendre respectivement des valeurs de référence supérieures (Vp, Vp(max)+dv) et inférieures (Vm ; Vm(max)-dv) sur des intervalles de forçage de porteuse aux fronts montants (RE) et descendants (FE) du signal d'entrée carré (Isq) en recevant dans un bloc de circuit de commutation (100) actif entre le premier bloc de circuit (12) et le deuxième bloc de circuit (14) des signaux de référence ayant des valeurs de référence supérieures (Vp, Vp(max)+dv) et inférieures (Vm ; Vm(max)-dv), et en commutant (102) au choix (Sync1, Sync2 ; I/E) ledit bloc de circuit de commutation (100) entre :

- un réglage de transfert de porteuse (0), dans lequel le bloc de circuit de commutation (100) couple le premier bloc de circuit (12) au deuxième bloc de circuit (14) pour transférer vers ce dernier le signal triangulaire (Vtri) en tant que signal porteur (Vtri2), et

- au moins un réglage de forçage de porteuse (1, 2) dans lequel le bloc de circuit de commutation (100) applique au deuxième bloc de circuit (14) lesdits signaux de référence en forçant le signal porteur (Vtri2) à prendre respectivement lesdites valeurs de référence supérieures (Vp, Vp(max)+dv) et inférieures (Vm ; Vm(max)-dv).

9. Procédé selon la revendication 8, dans lequel lesdits intervalles de forçage de porteuse sont centrés autour des fronts montants (RE) et descendants (FE) du signal d'entrée carré (Isq).

10. Procédé selon la revendication 8 ou 9, dans lequel le signal de modulation (Vmod) a une variation de signal de modulation entre des valeurs de signal de modulation (Vmod) la plus haute et la plus basse, dans lequel le forçage au choix (Sync1, Sync2) du signal porteur (Vtri2) à prendre des valeurs de référence supérieures et inférieures comprend :

- un premier mode de forçage de porteuse dans lequel les valeurs de référence supérieures et inférieures sont choisies à des premières valeurs (Vp, Vm) se trouvant dans les limites de la variation du signal de modulation, et

- un deuxième mode de forçage de porteuse dans lequel les valeurs de référence supérieures et inférieures sont choisies à des deuxièmes valeurs (Vp(max)+dv, Vm(max)-dv) qui se trouvent en dehors de la variation du signal de modulation.

11. Procédé selon l'une quelconque des revendications 8 à 10, comprenant les étapes suivantes :

- choisir une valeur la plus basse pour le cycle d'utilisation du signal modulé par MID (Out(PWM) où le signal modulé par MID a un temps actif d'impulsion le plus petit à la valeur la plus basse choisie pour le cycle d'utilisation,

- choisir la durée des intervalles de forçage de porteuse aux valeurs de référence supérieures (Vp, Vp(max)+dv) et inférieures (Vm ; Vm(max)-dv) égale audit temps actif d'impulsion le plus petit.

Drawing