PARALLEL PROCESSING ON DEMAND USING PARTIALLY DYNAMICALLY RECONFIGURABLE FPGA - Patent 3555760

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EP 3 555 760 A1

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(43)	Date of publication:
	23.10.2019 Bulletin 2019/43

(21)	Application number: 17818135.0

(22)	Date of filing: 19.12.2017

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International Patent Classification (IPC):

G06F 15/78^(2006.01)

G06F 15/80^(2006.01)

(86)	International application number:
	PCT/EP2017/083555

(87)	International publication number:
	WO 2018/114957 (28.06.2018 Gazette 2018/26)

(84)	Designated Contracting States:
	AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
	Designated Extension States:
	BA ME
	Designated Validation States:
	MA MD TN

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Priority:

19.12.2016 EP 16306730

(71)	Applicants:
	Centre National de la Recherche Scientifique 75794 Paris Cedex 16 (FR) Université de Lille 59800 Lille (FR)

(72)	Inventor:
	DEKEYSER, Jean-Luc 62840 Sailly-sur-la-Lys (FR)

(74)	Representative: Nony
	11 rue Saint-Georges 75009 Paris 75009 Paris (FR)

(54)	PARALLEL PROCESSING ON DEMAND USING PARTIALLY DYNAMICALLY RECONFIGURABLE FPGA