(19)
(11) EP 3 675 179 A8

(12) CORRECTED EUROPEAN PATENT APPLICATION
Note: Bibliography reflects the latest situation

(15) Correction information:
Corrected version no 1 (W1 A1)

(48) Corrigendum issued on:
12.08.2020 Bulletin 2020/33

(43) Date of publication:
01.07.2020 Bulletin 2020/27

(21) Application number: 18001016.7

(22) Date of filing: 28.12.2018
(51) International Patent Classification (IPC): 
H01L 29/423(2006.01)
H01L 21/28(2006.01)
 H01L 21/265(2006.01)
(84) Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated Extension States:
BA ME
Designated Validation States:
KH MA MD TN

(71) Applicant: Infineon Technologies AG
85579 Neubiberg (DE)

(72) Inventors:
  • JELINEK, Moriz
    9500 Villach (AT)
  • KHOR, Kang Nan
    14300 Nibong Tebal (MY)
  • SCHIEBER, Armin
    9500 Villach (AT)
  • STADTMUELLER, Michael
    9500 Villach (AT)
  • SUN, Wei-Lin
    9500 Villach (AT)

(74) Representative: Lambsdorff & Lange Patentanwälte Partnerschaft mbB 
Grillparzerstraße 12A
81675 München
81675 München (DE)

   


(54) METHOD OF MANUFACTURING A TRENCH OXIDE IN A TRENCH FOR A GATE STRUCTURE IN A SEMICONDUCTOR SUBSTRATE


(57) A method of manufacturing a trench oxide in a trench for a gate structure in a semiconductor substrate is described. The method comprises generating the trench (110) in the semiconductor substrate (101); generating an oxide layer (120) over opposing sidewalls (110A, 110B) of the trench; damaging at least a portion (121) of the oxide layer by ion implantation; coating the oxide layer with an etching mask (130); generating at least one opening (131) in the etching mask adjacent to one of the opposing sidewalls; and partly removing the oxide layer by etching the oxide layer beneath the etching mask down to an etching depth (ED) at the one of the opposing sidewalls (110A) by introducing an etching agent into the opening.