(19)
(11) EP 3 693 993 A8

(12) CORRECTED EUROPEAN PATENT APPLICATION
Note: Bibliography reflects the latest situation

(15) Correction information:
Corrected version no 1 (W1 A1)

(48) Corrigendum issued on:
02.09.2020 Bulletin 2020/36

(43) Date of publication:
12.08.2020 Bulletin 2020/33

(21) Application number: 19156506.8

(22) Date of filing: 11.02.2019
(51) International Patent Classification (IPC): 
H01L 27/02(2006.01)
H01L 21/762(2006.01)
 H01L 27/12(2006.01)
(84) Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated Extension States:
BA ME
Designated Validation States:
KH MA MD TN

(71) Applicant: Infineon Technologies AG
85579 Neubiberg (DE)

(72) Inventor:
  • Barrenscheen, Jens
    81669 München (DE)

(74) Representative: Müller Hoffmann & Partner 
Patentanwälte mbB St.-Martin-Strasse 58
81541 München
81541 München (DE)

   


(54) SEMICONDUCTOR DEVICE INCLUDING PROTECTION STRUCTURE AND MANUFACTURING METHOD THEREFOR


(57) An embodiment of a semiconductor device (100) comprises an isolation structure (104). A first active area (108), a protection area (112), and a second active area (116) are formed on the isolation structure (104). A first trench isolation structure (110) electrically separates the first active area (108) and the protection area (112). A second trench isolation structure (114) electrically separates the protection area (112) and the second active area (116). A protection structure (118) is formed in the protection area (112). A first pin (120) of the protection structure (118) is electrically connected to the first active area (108) and a second pin (122) of the protection structure (118) is electrically connected to the second active area (116).